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JPS60260178A - Optical integrated circuit device - Google Patents

Optical integrated circuit device

Info

Publication number
JPS60260178A
JPS60260178A JP59115442A JP11544284A JPS60260178A JP S60260178 A JPS60260178 A JP S60260178A JP 59115442 A JP59115442 A JP 59115442A JP 11544284 A JP11544284 A JP 11544284A JP S60260178 A JPS60260178 A JP S60260178A
Authority
JP
Japan
Prior art keywords
light
semiconductor laser
photo
receiving part
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59115442A
Other languages
Japanese (ja)
Inventor
Takashi Sugino
隆 杉野
Akio Yoshikawa
昭男 吉川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59115442A priority Critical patent/JPS60260178A/en
Publication of JPS60260178A publication Critical patent/JPS60260178A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To form an optical integrated circuit having an inverter, to be turned to the base of a digital circuit, composed of a photo element by a method wherein an element to be used to detect a light and a light-emitting element are integrated in the state of parallel connection on a semiconductor substrate. CONSTITUTION:A light-emitting element 7 and a light-receiving element 8 are connected in parallel. When a terminal 21 is plus-biased and a terminal 22 is minus-biased, a current runs on the active layer 13 of a semiconductor laser, and a laser oscillation is generated. A photo conductive element, which is a light- receiving part 18, is connected to the semiconductor laser in parallel, but when no photo signal is inputted from outside, no current runs because the light-receiving part 18 is in the state of high resistance. Then, when a photo signal is inputted, the resistance of a high resistance layer is reduced as it is absorbed by the light-receiving part 18. As a result, a part of the current running to the semiconductor laser runs to the light-receiving part, the current running to the semiconductor laser is attenuated, and the photo output is decreased. The oscillation of the semiconductor laser can be stopped by working out the design of this device in such a manner that the voltage running on the semiconductor laser is reduced to the threshold voltage or below by the input of photo signal.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は論理回路に用いられる光集積回路に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an optical integrated circuit used in a logic circuit.

(従来例の構成とその問題点) 近年、光デバイスの研究開発が進み、個々の半導体レー
ザ、フォトディテクター等と電子デバイスの集積化が試
みられている。これは光通信における発信、受信部の小
型化等をめざすものである。
(Structure of conventional example and its problems) In recent years, research and development of optical devices has progressed, and attempts have been made to integrate individual semiconductor lasers, photodetectors, etc. with electronic devices. This aims to miniaturize the transmitting and receiving sections in optical communications.

従来例の最も典型的なものとして、半導体レーザーとト
ランジスター又は電界効果トランジスタ(FgT )が
モノリシックに集積された素子を挙げることかできる。
The most typical conventional example is a device in which a semiconductor laser and a transistor or field effect transistor (FgT) are monolithically integrated.

第1図はその基礎回路を示す。Figure 1 shows its basic circuit.

第1図において1は抵抗、2は半導体レーザ、3はFE
T、4.5は端子を示し、FET 3のゲート6に変調
信号を入力することによシ半導体レーザ2から光信号が
取シ出される。このアナログ素子に対し、論理回路に不
可欠なディジタル回路を光素子を用いて構成した集積回
路の研究開発が望まれている。光デイジタル回路は光コ
ンピューターを実現する基盤を築くものである。
In Figure 1, 1 is a resistor, 2 is a semiconductor laser, and 3 is an FE.
T, 4.5 indicates a terminal, and by inputting a modulation signal to the gate 6 of the FET 3, an optical signal is extracted from the semiconductor laser 2. In contrast to analog elements, research and development of integrated circuits in which digital circuits essential to logic circuits are constructed using optical elements is desired. Optical digital circuits lay the foundation for realizing optical computers.

(発明の目的) 本発明はこのような状況に鑑み、ディジタル回路の基礎
となるインバーターを光素子により構成した光集積回路
を提供するものである。
(Objective of the Invention) In view of the above circumstances, the present invention provides an optical integrated circuit in which an inverter, which is the basis of a digital circuit, is constituted by an optical element.

(発明の構成) で集積された構成となっている。この構成によって入力
光信号が低準位の場合、受光素子の両端の抵抗が高く、
電流は発光素子側へ流れ、出力として高準位の光信号を
出す。又、入力光信号が高い場合、受光素子の両端の抵
抗が低下し、発光素子側の電流が減少するため、低準位
の光信号が得られることになる。
(Structure of the invention) The invention has an integrated structure. With this configuration, when the input optical signal is at a low level, the resistance at both ends of the photodetector is high;
The current flows to the light emitting element side and outputs a high-level optical signal as an output. Furthermore, when the input optical signal is high, the resistance at both ends of the light-receiving element decreases, and the current on the light-emitting element side decreases, so that a low-level optical signal is obtained.

(実施例の説明) 以下本発明の一実施例について、図面を参照しながら説
明する。
(Description of Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の基本回路を示すもので、発光素子7と
受光素子8を並列に接続される。第3図(a) 、’ 
(b)は発光素子に半導体レーザ、受光素子に7オトコ
ンダクテイブ素子を使った光集積回路の一実施例を示す
。すなわち、まずn−GaAs基板11上およびp−G
a2At1−2As層16 、n−GazAtl−2A
s層17によって形成される埋め込み型レーザを形成す
る(第3図(a) )、つぎに埋め込み層であるp −
Ga zA!−1−ZAsAs層、n−Ga2fit+
−2As層17の一部を除去し、その部分へ高抵抗Ga
wAt1−wAs層18を成長させ、表面および基板1
1側ヘオーミック電極19.20を形成する(第3図(
b))。以上のように構成された光集積回路素子につい
て、その動作を以下に説明する。端子21をプラス、端
子22をマイナスにバイアスすると、電流は半導体レー
ザの活性層13を流れ、レーザ発振を起こす。前述した
ように半導体レーザと並列に受光部(18)であるフォ
トコンダクティブ素子が接続されているが、外部から光
信号が入力されない場合、受光部(18)は高抵抗のた
め、電流は流れない。次に、光信号が入力されると受光
部(18)で吸収されるので、前記高抵抗層の抵抗が減
少する。このため半導体レーザに流れていた電流の一部
が受光部に流れ、半導体し〜ザに流れる電流が減少し、
光出力が低下する。光信号の入力で半導体レーザに流れ
る電流をしきい値電流以下に減少させるように設計する
ことにより、半導体レーザの発振を停止させることがで
きる。この素子は光インバーターとして動作し、その特
性を第4図に示す。半導体レーザを使うことにより光出
力の変化を急峻にすることができる。
FIG. 2 shows a basic circuit of the present invention, in which a light emitting element 7 and a light receiving element 8 are connected in parallel. Figure 3(a),'
(b) shows an embodiment of an optical integrated circuit using a semiconductor laser as a light emitting element and seven otoconductive elements as a light receiving element. That is, first, on the n-GaAs substrate 11 and on the p-G
a2At1-2As layer 16, n-GazAtl-2A
A buried laser is formed by the S layer 17 (FIG. 3(a)), and then the p-layer which is the buried layer is formed.
GazA! -1-ZAsAs layer, n-Ga2fit+
- A part of the 2As layer 17 is removed and high resistance Ga is applied to that part.
A wAt1-wAs layer 18 is grown to cover the surface and substrate 1.
1 side heomic electrodes 19 and 20 are formed (Fig. 3 (
b)). The operation of the optical integrated circuit element configured as described above will be explained below. When terminal 21 is biased positively and terminal 22 is biased negatively, current flows through the active layer 13 of the semiconductor laser, causing laser oscillation. As mentioned above, the photoconductive element, which is the light receiving section (18), is connected in parallel with the semiconductor laser, but if no optical signal is input from the outside, the light receiving section (18) has a high resistance, so no current flows. . Next, when an optical signal is input, it is absorbed by the light receiving section (18), so that the resistance of the high resistance layer decreases. For this reason, part of the current flowing through the semiconductor laser flows into the light receiving section, and the current flowing between the semiconductor and the laser decreases.
Light output decreases. The oscillation of the semiconductor laser can be stopped by designing the semiconductor laser so that the current flowing through the semiconductor laser upon input of an optical signal is reduced below the threshold current. This device operates as an optical inverter, and its characteristics are shown in FIG. By using a semiconductor laser, the change in optical output can be made steeper.

なお、本実施例では発光素子として埋め込み型半導体レ
ーザを用いたが、いかなる構造の半導体レーザでも用い
られる。また、GaAs系、GaAlAs系のレーザだ
けでな(InP系をはじめ、その他の半導体を用いるこ
とができる。さらに、受光素子としてGaAs又はGa
AtAsフォトコンダクティブ素子を用いたが、それ以
外の材料を使用することができ、検知する光の波長に対
しても材料の選択ができる。まだ、受光素子としてフォ
トコンダクティブ素子以外の受光素子集集積可能であシ
、受光素子に抵抗を接続することもできる。
Note that although a buried semiconductor laser is used as the light emitting element in this embodiment, a semiconductor laser of any structure can be used. In addition, not only GaAs-based and GaAlAs-based lasers (InP-based and other semiconductors can also be used. Furthermore, as a light receiving element, GaAs or Ga
Although an AtAs photoconductive element is used, other materials can be used, and the material can be selected depending on the wavelength of the light to be detected. It is still possible to integrate a light receiving element other than a photoconductive element as a light receiving element, and it is also possible to connect a resistor to the light receiving element.

以上のように本発明は少なくとも元を検知する素子と発
光素子が並列に接続された集積回路装置により、インバ
ーターの特性を示すことができ、その実用的効果は犬な
るものがある。
As described above, the present invention can exhibit the characteristics of an inverter by using an integrated circuit device in which at least an element for detecting a source and a light emitting element are connected in parallel, and its practical effects are significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の元−FET集積基礎回路、第2図は本
発明の基礎回路、第3図(a)、(b)は半、導体レー
ザと受光素子を集積した素子の断面図、第4図は集積回
路の特性図である。 1・・抵抗、2,7・・・半導体レーザ、3・・・FE
T 。 4.5,6,9.10121.22・・・端子、8・・
・受光素子、11−n−GaAs基板、12− n−G
axAZl−xAsクラッド層、13− Ga2A71
−yAs活性層、14 ・・・p−GaxAtl−xA
Sクラッド層、15− p−GaAs層、16− p−
Ga2A71−2As層、17・・・n−Ga、LAt
l−2As層、18 ・・・高抵抗Ga、、A71−A
s層、19 、20−・・オーミック電極。 (O≦W≦/くχ、 )J、Z )。 第1図 第2図 第3図 (a) (b) 第4 九入力
FIG. 1 is a basic FET integrated circuit of a conventional example, FIG. 2 is a basic circuit of the present invention, and FIGS. 3 (a) and (b) are cross-sectional views of an element that integrates a semiconductor laser and a light receiving element. FIG. 4 is a characteristic diagram of the integrated circuit. 1...Resistance, 2,7...Semiconductor laser, 3...FE
T. 4.5,6,9.10121.22... terminal, 8...
・Photodetector, 11-n-GaAs substrate, 12-n-G
axAZl-xAs cladding layer, 13-Ga2A71
-yAs active layer, 14...p-GaxAtl-xA
S cladding layer, 15-p-GaAs layer, 16-p-
Ga2A71-2As layer, 17...n-Ga, LAt
l-2As layer, 18...High resistance Ga,, A71-A
s layer, 19, 20--ohmic electrode. (O≦W≦/kuχ, )J, Z). Figure 1 Figure 2 Figure 3 (a) (b) 4th 9th input

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に少なくとも光を検知する素子と発光素子
が並列接続で集積されたことを特徴とする光集積回路装
置。
An optical integrated circuit device characterized in that at least a light-detecting element and a light-emitting element are integrated in parallel connection on a semiconductor substrate.
JP59115442A 1984-06-07 1984-06-07 Optical integrated circuit device Pending JPS60260178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59115442A JPS60260178A (en) 1984-06-07 1984-06-07 Optical integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59115442A JPS60260178A (en) 1984-06-07 1984-06-07 Optical integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60260178A true JPS60260178A (en) 1985-12-23

Family

ID=14662657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59115442A Pending JPS60260178A (en) 1984-06-07 1984-06-07 Optical integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60260178A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268352A (en) * 1990-03-16 1991-11-29 Nippon Telegr & Teleph Corp <Ntt> Optical integrated circuit
US5401600A (en) * 1991-09-27 1995-03-28 Fuji Electric Co., Ltd. Photosensitive body for electrophotography

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03268352A (en) * 1990-03-16 1991-11-29 Nippon Telegr & Teleph Corp <Ntt> Optical integrated circuit
US5401600A (en) * 1991-09-27 1995-03-28 Fuji Electric Co., Ltd. Photosensitive body for electrophotography

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