JPS60256878A - Picture processor - Google Patents

Abstract

PURPOSE:To check many picture planes and items of a matter to be checked, and to process many check areas at a high speed by controlling a digitizing means and an arithmetic processing means according to the control information on processing of both means. CONSTITUTION:The picture data obtained from ITV cameras 25 and 26 are supplied to comparators 27-29 respectively, and discriminating levels of these comparators are changed under the control of a control circuit 23. A logical circuit 30 performs a logical operation according to the state of the memory data 22 of a picture processing condition memory 24. The outputs of the circuit 30 are counted by counters CNT1-CNTn. The window numbers are supplied to those counters after an window number bit 22a is decoded by a decoder 31. These counters are activated in response to the output of the decoder 31, an the outputs of these counters are supplied to a multiplexer 32. The multiplexer 32 outputs selecively these counter outputs to the circuit 23. The circuit 23 transfers selectively the data 22 equivalent to a screen within a main memory 21 to the memory 24.

Description

TECHNICAL FIELD The present invention relates to an apparatus for processing digitized image data.

BACKGROUND ART FIG. 1 is a block diagram of an image processing apparatus 1 showing a prior art. Image data of an object to be inspected captured by an industrial television camera I is digitized by a digitization circuit. The arithmetic processing circuit P calculates data from the digitization circuit in chronological order in synchronization with the scanning of the industrial television camera I. Control circuit C is industrial television camera I
, the digitization circuit and the arithmetic processing circuit P. The image processing circuit 1 of the prior art has a drawback in that it can only perform one type of calculation because there is generally only one arithmetic processing circuit P.

FIG. 2 is a block diagram of an image processing device 2 showing another prior art. This prior art is similar to the prior art described above, and corresponding parts are given the same reference numerals. In the image processing system 2 of this prior art, image data for one screen digitized by a digitizing circuit is stored in a frame memory F, and then written in the frame memory F by a control device C. This is a device that processes image data.

Image path 3 like this! ! ! The device 2 has the disadvantage that since the image data is once stored in the frame memory F, the processing time is long and real-time processing cannot be performed. In addition, in such an image processing device 2, when there are a plurality of industrial television cameras I, a number of 7-frame memories F corresponding to the number of industrial television cameras I are required, which makes it expensive. There were some drawbacks. Furthermore, in such an image processing device 2, when two or more levels of digitization are required due to the digitization circuit, multi-level processing is performed, so if the processing time becomes longer, ν, defects, and d may occur. Ta.

OBJECT It is an object of the present invention to provide an image processing apparatus that can process, for example, multiple screens, multiple inspection items, and multiple inspection areas of an object to be inspected at a high speed.

Embodiment FIG. 3 is a block diagram of an image processing apparatus 10 according to an embodiment of the present invention. The image processing device 10 performs various processes in response to the memory data 11 shown in FIG. Memory data 11 includes, for example, window number bit 11a, logical operation mode bit 1! '1b and switching pin)llc
Consists of. The quantity of memory data corresponds to the quantity of all pixels of one of the industrial television cameras TTV, to ITVn. The main memory device MS has memory data 11 for the entire surface. The control device CPU is connected to the main storage device MS.
Memory data 11 for one screen out of the memory data stored in is outputted to the image processing condition memory l) PM at high speed as required.

The industrial television cameras ITV, to ITVn image the object to be inspected and output image data to the digitization circuit DE. The digitization circuit DE consists of comparison circuits COl-COn. The comparison circuits CO1 to COD select the industrial television cameras ITV, -ITV according to the respective set discrimination levels.
Performs binarization or multi-value processing of the image data from n. The discrimination level of the comparison circuits CO1 to Con is determined by the switching pin 11c of the memory data 11 stored in the image processing condition memory PM. Logic operation circuit LP
The output from the digitization circuit DE is converted into an image "memory data recorded in the processing condition memory P'M (logical product S, . . . according to the logical operation bit 11b of Liu Yu 11).

Do this. The logic operation circuit LP is, for example, AND.

Performs logical calculations such as OR and X-0R. The real-time processing calculation circuit RP is recorded in the image processing condition memory PM! The window number of memory data 11 that is being displayed is 14
In response to the contents of a, processing is performed for each window number. The real-time processing arithmetic circuit RP has functions such as addition/subtraction, multiplication, division, averaging, and correlation, and performs calculations such as area or center of gravity position. The logic operation circuit LP of the digital north circuit DE1 and the real-time processing operation circuit RP perform processing in synchronization with the scanning of the industrial television cameras ITV to ITVn. Therefore, the image processing device 10 can perform real-time processing and can perform processing at high speed.

In this way, the control circuit CPU 1. JrB, by selectively transferring one screen worth of memory data 11 stored in the device MS to the image processing condition memory PM, image data of the object to be inspected can be instantly generated under the conditions stored in the memory data 11. can be processed.

FIG. 5 is a waveform diagram showing the operation of the control means CPU.

FIG. 5(1) shows the time required to transfer one screen worth of memory data 11 from the main storage device MS to the image processing condition memory ljPM. FIG. 5(2) shows the logic operation circuit LP and the real-time processing operation circuit RP open during processing. FIG. 5(3) shows the time during which the control device CPtJ reads out the calculation results stored in the real-time processing calculation circuit RP. During the period W1, one screen worth of memory data 11 is transferred to the image processing condition memory ljPM.

The period W2 indicates the processing time of the logic operation circuit LP and the real-time processing operation circuit RP, and is approximately 16 to 33+os. The period W3 indicates the readout time of the calculation results stored in the real-time processing calculation circuit RP. The period W4 is required only when changing the processing item. In other words, when performing the same process as the above-mentioned process item, period W4
is not required. The periods ws and w6 are similar to the periods W2 and W3. In this way, the image processing device 10 can perform instant processing.

, FIG. 6 is a block diagram of an image processing device 20 according to another embodiment of the present invention. The main storage device 21 stores data for the plan side of the memory data 22 as shown in FIG. The control circuit 23 selectively transfers one screen worth of memory data 22 stored in the main storage device 21 to the image processing condition memory 24 . Industrial TV camera 2
5.26 images the object to be inspected. The image data output from the industrial television camera 26 is sent to a comparison circuit 27.2.
8 is input. The discrimination levels of the ratio V circuits 27 and 28 are different. Image data output from the industrial television camera 26 is input to two comparison circuits. The two discrimination levels of the comparison circuit 27 can be changed under the control of the control circuit 23. logic circuit 3
0 performs a logical operation according to the state of the memory data 22 stored in the image processing condition memory 24. Counter CN
T1 to CNTn are outputs from the logic operation circuit 30,
Count. The window number is decoded by the decoder 31 from the window number bit 22a of the condition memory data 22 stored in the image processing condition memory 24, and is input to the counters CNT, -, to CNTn. Counters CNT1-CNTn are activated in response to the output from clock 31.

Outputs from counters CNT, -CNTn are input to multiplexer 32. The multiplexer 32 selectively outputs the outputs from the counters CNT to CNTn to the control device 2.
Output to 3. In this way, 1! is written in the main memory 21! It is possible to process multiple screens, multiple inspection items, and multiple inspection areas of an object to be inspected by simply transferring one screen's worth of memory data 22 out of the memory data 22 for planned planes to the image processing condition memory 24. can.

The multi-screen processing of the object to be inspected refers to the industrial television cameras ITV to ITVn in the above-mentioned embodiments.

25 and 26 and the temporally switched imaging regions. The multiple inspection items of the object to be inspected refer to the inspection items of the logical operation circuits LP, 30, the real-time processing operation circuit RP, and the counters CNT, to C1NTn, whose processing items change according to the contents of the memory data 11.22. The multi-inspection area of the object to be inspected is the memory data 11,
This is the meaning of the processing area indicated by window number 22, 22a, and 22a. In the above-mentioned implementation, the main storage device MS stores the memory data 11 and 22 for the planning side.
, 21 to one screen worth of memory data il as needed,
22 is transferred to the image processing condition memory PM, 24, but if each screen is processed the same, one screen's worth of memory data 11.12 is transferred to the image processing condition memo 'JPM, 24 from the beginning.
It is better to remember 1.

In the embodiments described above, the image of the object to be inspected is taken, but graphic data may be processed by a computer or the like.

In addition, in the above-mentioned embodiment, memory data is stored for each pixel.
Although the processing is performed in addition, memory data may be added and processed for each plurality of pixels.

Effects As described above, according to the present invention, the denotalizing means and the arithmetic processing means are controlled in accordance with the information for controlling the processing operations of the denotalizing means and the arithmetic processing means. Inspection items and multiple inspection areas can be processed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing device 1 showing the prior art;
2 is a block diagram of another prior art image processing device 2, FIG. 3 is a block diagram of an image processing device 10 according to an embodiment of the present invention, and FIG. 4 is a diagram for explaining memory data 11. , FIG. 5 is a waveform diagram showing the operation of the control means CPU, and FIG. 6 is a block diagram of an image processing device 20 according to another embodiment of the present invention.
FIG. 7 is a diagram showing the memory data 22. 10.20... Image processing device, 11.22... Memory data, 21. MS...main storage device, 23. CPU・
...control circuit, 24. PM...image processing condition memory,
25.26. ITV, ~ITV mouth...Industrial television camera, 27~29. CO, ~CON... Comparison circuit, 30
, LP... logic circuit, DE... digitization circuit,
RP... Real-time processing arithmetic circuit, CNT, ~CN
Tn...Counter Figure 5 Figure 6

Claims (1)

[Scope of Claims] A memory for rewritably storing processing conditions for at least one frame of digitized image data; and an arithmetic circuit for processing the image data in response to the contents stored in the memory. An image processing device comprising: