JPS60254961A - Image signal processing circuit - Google Patents

Abstract

PURPOSE:To constitute the inexpensive image signal processing circuit of simplified circuit constitution by dividing video signals outputted from respective sensors into plural pieces in every picture element, and switching the outputs of the sensors successively and performing processing. CONSTITUTION:The line sensors 21-24 are driven at the same timing with clock pulses from a clock generating circuit 3 to scan an original surface, etc. Video signals outputted by those line sensors 21-24 are amplified by amplifiers 41-44 to a proper value and then sent to sample and hold circuits 51-54. The sample holding circuits 51-54 sample and hold every picture element of the signals according to a timing signal from the clock generating circuit 3. The outputs of the sample holding circuits 51-54 are switched successively by a multiplexer 10 according to the switching signal from the clock generating circuit 3, and the composite signal of the outputs of the line sensors 21-24 is sent to an A/D converter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image signal processing circuit that is used in, for example, a facsimile machine or a copying machine, and uses a photoelectric converter formed by arranging a plurality of line sensors.

[Technical Background of the Invention] Conventionally, for example, in a facsimile machine or a copying machine that electrically captures and processes an image of a document, a photoelectric converter 1 as shown in FIG. 3 has been used to sufficiently resolve the image of the document. ing. This photoelectric converter 1 includes a plurality of (for example, four) photoelectric converters each having a plurality of light receiving elements arranged in a line.
The line sensors 21 to 24 are arranged in a row as shown in the figure.

Signal processing is performed by an image signal processing circuit configured as shown in FIG. 4, and the details thereof will be explained below. First, each of the line sensors 21 to 24 shown in FIG. 3 is driven at the same timing by a glue lock pulse from the slip-off generating circuit 3 to scan the surface of the original. The video signals output from each of the line sensors 21 to 24 are amplified to appropriate values by amplifiers 41 to 44, respectively, and then sent to sample and hold circuits (S/H) 51 to 54, where each one pixel is The signal is sampled and held every time. The outputs of the sample and hold circuits 51 to 54 are connected to A/D converters (A/D) 6s to 64, respectively.
After being converted into digital signals by , they are stored in buffer memories 71 to 74 and 81 to 84, respectively. The buffer memories 71-74.8t-84 are used alternately for writing and reading, and are controlled by a memory control circuit. In this way, the buffer memory 71~
The image information stored in 74 or 81 to 84 is sent as one line information to the next processing circuit (not shown) under the control of the memory control circuit 9.

[Problems with the Background Art] However, the conventional circuit configuration described above requires expensive A/D converters and buffer memories corresponding to the number of line sensors used, and also has the problem that the circuit also has a very complicated configuration. there were.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide an inexpensive image signal processing circuit with a simple circuit configuration.

[Summary of the Invention] In order to achieve the above object, the present invention divides the video signal output from each sensor into multiple parts per pixel, and processes the outputs of each sensor by sequentially switching them. be.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the same parts as in FIG. 3 will be described with the same reference numerals. In FIG. 1, each line sensor 21 to 24 is
They are driven at the same timing by clock pulses from the clock generation circuit 3, and scan the surface of a document. The video signals outputted from each of the line sensors 21-24 are amplified to appropriate values by amplifiers 41-44, respectively, and then sent to sample-and-hold circuits 51-54, respectively. The sample and hold circuits 51 to 54 each sample and hold a signal for each pixel in response to a timing signal from the clock generation circuit 3.

Here, an example of a sampled and held video signal is shown in FIG. 2(a). Note that f in the figure is one pixel length. Therefore, each output of the sample and hold circuits 51 to 54 is sent to the clock generation circuit 3 by the multiplexer 10.
Each of the line sensors 21 to 24 is sequentially switched and synthesized according to the switching signal (see Figure 2, c, d, e) from
The video signal is sent to the A/D converter 6. A/D converter 6 converts the video signal from multiplexer 1o into a digital signal in accordance with the timing signal from clock generation circuit 3, and this digitized video signal is stored in buffer memory 7.8. Buffer memory 7.8 is used alternately for writing and reading, and is controlled by memory control circuit 9 which operates in response to timing signals from clock generation circuit 3. The video signal thus stored in the buffer memory 7 or 8 is sent as one line information to the next processing circuit (not shown) under the control of the memory control circuit 9.

In this way, by using the photoelectric converter 1 formed by arranging a plurality of line sensors 21 to 24 in a row, and driving each of the line sensors 21 to 24 at the same timing, one
In a circuit that captures and processes line information, the analog video signal obtained from each line sensor 21 to 24 is divided into multiple parts in one pixel, and each line sensor 21 to 24
By switching and processing the output of 4, the subsequent A/D
The number of converters and buffer memories can be significantly reduced, and an image signal processing circuit with an inexpensive and simple configuration can be obtained.

In the above embodiment, a sample and hold circuit was provided after the amplifier, but since the frequency of the clock pulse that drives the line sensor is low, the signal of one pixel can be sufficiently large in terms of time, and the signal component of one pixel can be transferred to the next signal. If there is no change until the pixel changes, a sample and hold circuit is not necessary. Further, in the above embodiment, the case where a line sensor is used has been described, but the present invention is not limited to this, and can also be applied to a case where a sensor called a so-called surface array is used.

[Effects of the Invention] As described in detail above, according to the present invention, the circuit configuration is simplified and an inexpensive image signal processing circuit can be provided.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of the main parts in the same embodiment, and Fig. 3 is a photoelectric conversion formed by arranging a plurality of line sensors. FIG. 4 is a block diagram showing an example of a conventional image signal processing circuit. DESCRIPTION OF SYMBOLS 1...Photoelectric converter, 21-24...Line sensor, 3...Return-off generation circuit, 6...
...A/D converter, 7.8...Buffer memory, 9...Memory control circuit, 10...
・Multiplexer. Figure 1 Prisoner 2 Figure 3

Claims (4)

[Claims] (1) In an image signal processing circuit using a photoelectric converter formed by arranging a plurality of sensors each having a plurality of light-receiving elements arranged, the video signal output from each sensor is divided into a plurality of pixels in one pixel. The sensor is characterized by comprising a switching means for sequentially switching the output of each sensor, an A/D conversion means for converting the output of the switching means into a digital signal, and a storage means for storing the output of the A/D conversion means. Image signal processing circuit. (2) The image signal processing circuit according to claim 1, wherein each of the sensors is driven at the same timing. (3) The image signal according to claim 1, wherein the photoelectric converter is formed by arranging a plurality of line sensors each having a plurality of light receiving elements arranged in a line. processing circuit. (4) The image signal processing circuit according to claim 1, wherein the switching means is a multiplexer.