JPS60254625A - Test method for short gate type FET - Google Patents

Abstract

PURPOSE:To do an accelerated life test precisely in a short time, by inputting an alternating-current signal having a higher level than the allowable operating signal level into the gate of the field effect transistor to operate it. CONSTITUTION:A direct current bias from a DC source 22 as well as an alternating-current signal from an AC source 24 are applied to the gate of a field effect transistor 22. By the AC signal whose level is larger than the signal level being possible to be allowed at normally operating time, the gate bias voltage is swung around the load line in the output characteristic of the field effect transistor to cause the schottky junction to flow a reverse breakdown current and a forward gate current alternately, so that occurrence of consumed defects can be accelerated owing to the sum of both the currents and a leak current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for testing a Schottky gate type FET for microwave use, and particularly relates to a method for testing a Schottky gate type FET for microwave use.
This invention relates to an accelerated life test method for estimating the life of an ET in a short time.

Microwave radio waves have superior straightness, making them indispensable as a medium for satellite communication.Also, the frequency is more than two orders of magnitude higher than that of ordinary high-frequency waves, significantly increasing the amount of information that can be transmitted in a given period of time. Therefore, it has recently come to be widely used in the field of terrestrial communications.

Schottky gate type FETs made of gallium arsenide (GaAs) are mainly used as active elements when configuring the above-mentioned microwave communication system, but in order to improve the reliability of the communication system, it is necessary to extend the life of the FET. Strong (required)

The main cause of shortening the life of Schottky gate type FFs and Ts is so-called wear-out failures.

A wear-out failure is a failure in which when the FET is operated for a long period of time, defects such as grooves occur in the gate electrode, the gate no longer functions normally, and the performance of the FET is lost.

This wear-out failure is caused by the forward or reverse leakage current of the gate during operation, that is, the current flowing through the Schottky junction formed between the gate electrode and the semiconductor substrate, which causes metal atoms in the gate electrode to move toward the semiconductor substrate, especially the drain side. This is caused by the so-called electromigration phenomenon.

Therefore, in order to prevent wear-out failures and extend the life of the FET, it is extremely important to reduce the forward or reverse leakage current that constantly flows through the Schottky junction.

However, the leakage current has the property of varying depending on the surface condition of the semiconductor substrate, process conditions, etc. when forming the Schottky junction, and the value of the leakage current is uniformly within a limited and very small value. It is extremely difficult to manufacture FETs that are

Therefore, in the Schottky gate type FET for microwaves mentioned above, the lifespan of the product in that loft can be guaranteed by performing the accelerated life test for wear failure on samples from each manufacturing loft, for example, where the product manufacturing conditions are approximately uniform. The product is then shipped.

This method of accelerated life testing makes it possible to predict the lifespan in a short period of time since the product cannot be shipped until the test is completed, and since it is incorporated into the manufacturing process, the equipment can be simplified as much as possible. desired.

[Conventional technology]

In the accelerated life test described above, the leakage current that causes wear-out failure increases by increasing the reverse bias applied to the Schottky junction, and the rate of increase increases when the saturation current is large, that is, when the reverse characteristics are blunted. Taking advantage of the large size of the Schottky gate FET for microwaves, applying a reverse bias higher than that during normal operation to the gate accelerates the occurrence of the wear-out failure, and from this result, the Schottky gate FET for microwave
A selection of loft quality is made.

The simplest accelerated life test method is the so-called DC test method in which the reverse bias of the gate is deepened. However, in this method, if the DC bias is deep enough, a breakdown current will flow in the junction, so the gate will wear out and fail and an accelerated test can be performed, but the bias will shift along the load line and the gate will deviate from normal operation. This results in an accelerated test for estimating the lifetime of the FET, which has the disadvantage that it is not possible to accurately estimate the lifetime of the FET.

Therefore, in this method, only a gate current comparable to the leakage current can be passed, so there is a problem that the test time becomes extremely long.

Conventionally, as an accelerated testing method to eliminate the above-mentioned problem of prolonging the test time, a method has often been used in which a microwave signal larger than that during normal operation is input to the gate, centering on the normal gate operating voltage.

However, in this method, since microwaves are used as the additional signal for acceleration, a complicated and large-scale device such as the microwave burn-in device shown in FIG. 6 is required, which increases costs and complicates the work. I was invited.

In Figure 6, 1 is a microwave oscillator, 2 is a variable attenuator, 3 is an amplifier, 4.7 is an isolator, 5 is a directional coupler, 6 is a power level monitor, and 8 is a D
C bias power supply, 9 is the real plate, 10 is the attenuator,
11 indicates the FE'T to be tested.

[Problem that the invention seeks to solve]

The present invention has been made in order to solve the problems of the conventional accelerated life test method described above, that the equipment cost becomes enormous and the work becomes complicated. [Means for solving the problems] The present invention described above The purpose of this is to estimate the operating life of a Schottky gate type FET for microwaves by inputting an AC signal below the radio frequency having a signal level higher than the allowable operating signal level of the FET to the gate of the FET.
This is achieved by the Schottky gate FET testing method according to the present invention, which accelerates the deterioration of the Schottky gate junction by activating the Schottky gate FET.

[Effect]

That is, in the accelerated life test method of the present invention, the drain voltage, drain current, and gate voltage of a microwave Schottky gate FET are fixed at values used during normal operation, and the gate voltage is adjusted to the value used during normal operation. By superimposing an AC signal below the radio frequency (10 hHz) with a signal level greater than that, the bias voltage applied to the gate is greatly swung around the DC bias point of the gate. This is to promote the occurrence of wear-out failures by passing a reverse current and further a forward current.

Since wear-out failures depend on the current value, and this average current value is independent of frequency, this method uses conventional microcontrollers for the AC signal input to the gate to promote wear-out failures. Since an alternating current signal below the radio frequency, for example a commercial frequency signal of 50 to 6 Hz, is used instead of the wave signal, the acceleration test apparatus is greatly simplified and the operation thereof becomes easier.

〔Example〕

The present invention will be described below with reference to embodiments and drawings.

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an output characteristic diagram of the FET, and Fig. 3 shows the current-voltage (1-V
) characteristic diagram, Figure 4 is a correlation diagram between gate current and average life, Figure 5 is an I-V characteristic diagram showing another example of gate input signal, Figure 1 is a graph of commercial frequency (50 to 60 Hz). By inputting an alternating current signal to the gate, a reverse breakdown current and a forward current are alternately passed through the gate metal (e.g. aluminum)-semiconductor (GaAs) Schottky junction to promote wear-out failure of the gate electrode. FIG. 2 is a circuit diagram of an accelerated test device for estimating the life of an FET.

In the figure, 21 is the FET to be tested, 22 is a first DC power supply that applies a DC bias (about -2V) to the gate, and 23 is a DC voltage (about 5V) between the drain and source.
24 is an AC power source (50 to 60 Hz) that applies an AC signal to the gate, 25 is a transformer that adjusts the signal voltage, 26 is an ammeter that measures the gate current, and 27 is a drain-source RL is a load resistance, R is a resistance, C is a capacitor, E is a voltage needle, and GND is a grounding point.

The accelerated life test of the present invention uses, for example, a simple device like the one shown in the figure, and further tests the desired amplitude, that is, the signal level v, on the gate to which the same DC gate bias as in normal operation is applied.
This is done by inputting an alternating current signal with g.

Then, the signal level vg of the AC signal is made higher than the permissible signal level during normal operation, and the gate bias voltage is adjusted by this AC signal at point b along the load line, for example, a in the FET output characteristic diagram shown in FIG. The Schottky junction is swung up and down, causing reverse breakdown current and forward gate current to flow alternately through the Schottky junction, and the sum of these two types of current and leakage current accelerates the occurrence of wear-out failures. In addition, in Fig. 2, Ids
is the drain current, Vds is the drain voltage, v6 is the gate voltage, Idss is the saturation current, and Vd5s is the saturation voltage.

For example, if the reverse breakdown voltage of the gate of FET21 is 115V, if the voltage of the AC signal φ input to the gate is set to about 13V and the DC bias of the gate is set to, for example, -2V, the gate shown in FIG. 1-■ As shown in the characteristic diagram, the gate bias voltage V (, 3 is ±
It swings with a width vg of 13V, and when the bias voltage reaches point C3, breakdown current IGII flows to the gate, and when it reaches point 02, forward current I'GF flows to the gate.

Note that the temporal average value of the gate current, which is the sum of these currents, depends only on the amplitude of the AC signal and does not depend on the frequency. Therefore, if the amplitudes, that is, the signal levels are made equal, the average gate current value when using the above-mentioned commercial frequency signal will be equal to the average gate current value when using the conventional microwave signal.

Therefore, the amount of migration of the gate metal depending on the gate current becomes equal, and the acceleration rate of wear-out failure in the above embodiment is as high as that when using the conventional microwave burn-in device.

Figure 4 shows the gate (Schottky junction) as in the above example.
This is a diagram showing the relationship between the gate current IG (mA) and the average lifespan (hrs) of occurrence of wear-out failure when current is applied to the
In the figure, A is the forward current based on the design theory that the lifetime Ta decreases in proportion to the reciprocal of the square of the gate current J, as shown by the formula Ta = k-J −” ・exp(Eat/KT). In the curve for Note that these curves were obtained with the channel temperature Tch set to 110° C. during normal operation.

In the embodiment described above, since the gate current flows in both forward and reverse directions, the wear-out failure occurrence life is further shortened.

It is well known that the above lifetime decreases in proportion to an exponential function of the reciprocal of the channel temperature, so if FET0 temperature increasing means is used in conjunction with the above test, the test time can be further shortened. Note that the channel temperature is usually selected in the range of 150 to 250°C.

In the above embodiment, an alternating current signal having a sinusoidal waveform below the radio frequency is used as the gate input signal, but the same effect can of course be obtained by using a rectangular wave, a triangular wave, etc. which are extremely easy to form below the radio frequency.

If it is desired that the reverse current mainly contributes to the life test, an AC pulse signal having a wide reverse pulse width wb and a narrow forward pulse width Wf may be applied to the gate as shown in FIG. (Va is the gate bias, I6 is the gate current, IGF is the forward gate current, IGS is the saturation gate current, TGB is the breakdown gate voltage i!) [Effects of the Invention] As explained above, according to the present invention, the radio frequency By superimposing the following low frequency signals on the DC gate bias, accelerated life tests for wear-out failure of microwave Schottky gate FETs can be performed in the same short time and accurately as when conventional microwave signals are used. .

Therefore, compared to conventional tests using microwave burn-in equipment, accelerated life tests for wear-out failures can be performed using a significantly simplified test equipment, reducing testing costs for microwave Schottky gate FETs and making work easier. Become.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an output characteristic diagram of an FET, Fig. 3 is a current-voltage characteristic diagram of a Schottky gate, which also shows the state in which an AC signal is input to the gate. FIG. 4 is a correlation diagram between gate current and average life, FIG. 5 is a current-voltage characteristic diagram showing another example of a gate input signal, and FIG. 6 is a block configuration diagram of a conventional accelerated life test apparatus. In the figure, 21 is the FET to be tested, 22 is the first DC power supply, and 23 is the FET to be tested.
is the second DC power supply, 24 is the AC power supply (50 to 60Hz)
, 25 is a transformer, 26.27 is an ammeter, RL is a load resistance, R is a resistance, E is a voltmeter, and GND is a grounding part. 1st Ku 2nd @ 3rd Kyoho 4th printing Q, / /, (1) lOθ 'T”t; LIe C7F143 5th

Claims (1)

[Claims] When estimating the operating life of a Schottky gate type FET for microwaves, an alternating current signal below a radio frequency having a signal level higher than the allowable operating signal level of the FET is input to the gate of the FET to operate the FET. A method for testing a Schottky gate type FET, characterized by promoting deterioration of a junction of the Schottky gate.