JPS60253341A - Transmission and reception circuit for data transmission - Google Patents

Abstract

PURPOSE:To obtain an inexpensive transmission/reception circuit which transfers data through a short-distance transmission line at a low speed, by using just several units of transistors with no compensation needed for waveform distortions. CONSTITUTION:Transistors TrQ1-Q4 constitute a BTL type transmission circuit, and TrQ1 and Q4 are turned on with TrQ2 and Q3 turned off respectively with the transmission signal given from a logical circuit CC for control of transmission. Then a forward current flows to the primary side of a pulse transformer PT, and the ''+'' codes are transmitted via terminals T3 and T4 of the secondary side. While the ''-'' codes are transmitted when the TrQ1 and Q4 are turned off with the TrQ2 and Q3 turned on respectively. Thus the transmission is possible for a double-current binary code. Then the transmission of a ternary code is possible by turning off all TrQ1-Q4. A TrQ5 is turned on when an input code is fetched via the PT and an end T1 has a higher potential than the other end T2. Then the variation of the collector potential of the TrQ5 is fetched by a logical circuit CC. If the T1 has a lower potential than the T2, the variation of the collector potential of a TrQ6 is fetched by the circuit CC. In case the ternary code is received, the TrQ5 is separated from the TrQ6 and the variations of collector potentials of both TrQs are fetched independently by the circuit CC.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention is directed to a simple method suitable for low-speed digital data transmission over a transmission line that is short enough to eliminate the need to compensate for transmission waveform distortion. The present invention relates to a transmitting/receiving circuit for data transmission.

More specifically, in response to the increasing sophistication and complexity of household devices, including new media devices, disaster prevention and crime prevention devices, and the computerization of the home, these home information devices can be housed centrally and organically. Home'Area, Infor
The present invention relates to a data transmission transmitter/receiver circuit suitable for use in such a HAN, etc.

To give a specific example, in a home, if you want to control the blinking of lights in each room 1, span, etc. from the kitchen, you would use a network that runs through the home, and from the transmission circuit in the kitchen to the lights in each room, etc. Control commands are transmitted to the receiving circuit in digital data format, and the present invention can be said to relate to a simple transmitting/receiving circuit suitable for such uses.

[Prior art and its problems]

Traditionally, when talking about data transmission, for example, LAN (local
Targeted at computer-to-computer communication systems in business offices such as area networks, high-speed data transmission over relatively long distance transmission paths was considered, so it was necessary to synchronize bits between sending and receiving. can be,
Therefore, a differential operational amplifier with high sensitivity and hysteresis characteristics, a waveform equalizer to compensate for waveform distortion, and a PLL circuit to extract the clock are required. ° in
A scrambler and descrambler was needed to perform 0" continuous suppression.

In addition, even when the transmission distance is relatively short and the transmission speed is low, if start-stop synchronization is achieved and DC superposition is applied to the data transmission line, the DC component is small and the output power is low. A Z code with a small duty ratio is often used as a transmission code, but in order to extend the pulse width as a reception margin, a monostable multivibrator triggered by the rising edge of the RZ code or a monostable multivibrator that is The structure of the transmitter/receiver circuit is complicated, such as requiring a noise filter to prevent triggers, and is expensive to ensure reliability. For use in short-distance, low-speed transmission lines, complex,
It had the disadvantage of being too expensive and unsuitable.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to apply it to very short distance and low speed transmission lines such as home information communication networks. It is an object of the present invention to provide a simple, low-cost data transmission transmitting/receiving circuit suitable for use in the field of data transmission.

[Key points of the invention]

The transmitting/receiving circuit for data transmission according to the present invention includes a first transistor and a second transistor connected in series between one polarity (first polarity) and the other polarity (second polarity) of a power supply. 1 transistor pair and a second transistor pair consisting of a series connection of third and fourth transistors are connected in parallel, and a connection point between both transistors in the 11111 pair (first transistor connection point) to the first communication terminal, and that in the second pair (transistor connection point of drop 2) to the second communication terminal, and the transmission control #
By turning on the first transistor and the fourth transistor, or the second transistor and the third transistor, or not turning on any of the transistors, the first and fourth transistors are turned on depending on the control output from the m logic circuit. a transmitting circuit capable of transmitting a binary code or a ternary code through each communication terminal of tlEx; and a series connection of two resistors between the communication terminal of tlEx and the polarity of II of the power supply. A #11 resistor circuit consisting of the above, and a second resistor circuit similarly consisting of two resistors connected in series are connected between the second communication terminal and the first polarity of the power source, respectively, Said #! Two diodes connected with opposite polarities between the connection point between both resistors in the first resistance circuit (#11 resistance connection point) and that in the second resistance circuit (second resistance connection point) One end and the other end of the circuit are connected, and the base of the fifth transistor is connected to the first resistor connection point, and the base of the sixth transistor is connected to the second resistor! Ij! The emitters of the fifth and sixth transistors are respectively connected to the first polarity of the power source, and the flip-flops are led to the signal input button of the logic circuit, respectively, and the emitters of the fifth and sixth transistors are respectively connected to the first polarity of the power supply.
Either the fifth or the sixth transistor is turned on depending on which of the communication terminal and the second communication terminal receives the higher potential signal, or the first communication terminal and the second communication terminal are turned on. When a signal of the same potential is received at the terminal, the fifth @
◇ A receiving circuit that can input a binary code or a ternary code into the logic circuit by not turning on both 7 transistors of 6; [Embodiment of the Invention] Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The transmitting/receiving circuit shown in the figure has a transmitting circuit format of BTL (Ba
1anced transformers) circuit format, and shows a transmission/reception circuit in the case of performing balanced transmission with metallic pair cable CAi (DC superimposition).

In the same figure, Ql to Q4 are transmitting transistors, C5 and C6 are receiving transistors, Dl
and D2 are diodes, R1 and R2#'i, respectively.
The input impedance setting resistors R3 and 4 of the receiving circuit are transistors Q5. Q6 is the bias setting resistor, R5 is the receiving transistor Q5. Q6 collector load m resistor, pW is power supply, ■+ and V are electric wm resistors, C
1 and c2 are AC/DC separation capacitors, FT is a pulse transformer, T1 to T4 are terminals of the pulse transformer FT, and are also input/output terminals for transmitting/receiving signals.

CC is a transmission control logic circuit, and when a CCK transmission command is given to the circuit by means not shown, a required output is generated at its transmission output terminals TOutl to TOut4, and turns on and off the transmission transistors Q1 to Q4. It is meant to be controlled.

Further, when a reception command is given to the logic circuit CC by means not shown, the logic circuit CC receives the reception input terminal R.
The received codes from the receiving transistors Q5 and C6 are taken in and decoded through the receiving transistors 1n.

Next, the circuit operation will be explained. First, the operation of the transmitting circuit will be explained.

The transmitting transistors Q1 to Q4 constitute a BTL type transmitting circuit, and the transistor Q1 is activated by the transmitting signal output from the transmission control logic circuit CC.

When C4 is on, transistor Q2. When Q3 is off, ■+→Q l-+T t→llI 2-+Q4-*Vo
A positive current flows through the primary side of the pulse transformer PT through the circuit (RI5;7)"). As a result,
The cable CA is connected via the terminals T3 and T4 on the secondary side of the transformer PT, and further via the capacitors CI and C2.
6+level" code is sent out.

Similarly, when the transmitting transistors Ql and Q4 are off, C2,
When C3 turns on, V+-+Q a -+T 2-+T 1 →Q 2+V
o (ground) circuit causes a current in the opposite direction to flow through the primary side of the pulse transformer PT. As a result, 6 through terminals T3 and T4 on the secondary side of pulse transformer PT
- Level” code is sent.

In this way, it is possible to send out double-stream binary codes. Also, if all transistors Q1 to Q4 are turned off, this state corresponds to a high impedance of 60", which results in a high impedance of "1" and a high impedance of 0.
It becomes possible to send out 3-value codes.If the power supply voltage is 5
(V), if the turns ratio of the pulse transformer PT is set to 1=1, and the saturation voltage of the m transistors Ql to Q4 and the transmission loss of the pulse transformer PT are ignored, a transmission level of ±5 [V] can be obtained. Can be done.

Both terminals Tl of the transmission/reception circuit side winding of the pulse transformer PT,
T2 is connected to the input impedance setting resistor hole 1. R
2, both ends of silicon diodes DI and D2 connected in opposite directions to each other and an NPN type) transistor Q5.
Connect each base of Q6 and both diodes DI
, D2 and the emitters of both transistors Q5 and Q6 are connected to the ground potential terminal Vo.
By configuring a diode bridge, a relatively simple receiving circuit can be obtained.

Next, the operation of the receiving circuit will be explained. The code (current pulse) transmitted by cable CA is transferred to capacitor c1. c.
2 and the pulse transformer PT, and as a result, one end T1 of the pulse transformer winding becomes a higher potential than the other end T2 (in this case, it is assumed that a ten-level '1' is received). ), forward biases the transistor Q50 between the emitter and the diode D2, so the transistor Q5 turns on, creating a circuit of T1 → 几1 → Q5 → D2 → T2, and the potential change is taken out from the collector of the transistor Q5, It is taken into the Rin terminal of the transmission control logic circuit CC.

As a result of the code transmitted by cable CA being taken in via pulse transformer PT, contrary to the above, if terminal T1 becomes lower potential than terminal T2 (in this case, -
level 11'' is received), the base-emitter of the transistor Q6 and the diode Dlt are biased in the forward direction, so the transistor Q6 is turned on.
A circuit of T2→几2→Q6→D1→'r1 is completed, and the potential change at the collector of the transistor Q6 is taken out and taken into the Rin terminal of the transmission control logic circuit CC.

In this way, the reception signal (code) at the digital level can be received after being double-wave rectified. i.e. 1 of ten bells
When 1'' is received, either transistor □Q5 or Q6 is turned on, and when 0' is received, transistor Q5#Q is turned on.
Since transistors Q5 and Q6 are both turned off, a wired transistor like the one shown in the figure simply connects the collectors of transistors Q5 and Q6.
Easy single flow from Oadaka 2. Obtain the value sign and convert the logic circuit cc
It can be taken into the IR terminal of

When receiving a ternary code AMI (bipolar code), instead of connecting the collectors of transistors Qs and Q6, they are separated and each is taken into the logic circuit CC independently (therefore, the 1n terminal is also (two transistors are required) to identify 51" at the 10th level and '1' at the - level, and when both transistors Q5 and Q6 are off, identify it as receiving "θ". .

Note that depending on the logic processing in the logic circuit CC, an inverter may be connected to the s gin terminal, and the transistor Q
5. Of course, the output from the collector of Q6 may be inverted by the inverter before being input into the logic circuit cc.

Next, when a transmission/reception collision phenomenon occurs, in which reception occurs during a transmission operation, this is detected. Since the transmitter/receiver circuit according to the present invention has the following function, this will be explained below.

In FIG. 1, when the transmitting transistors Ql to Q4 are both off and transmitting "0", the receiving transistor Q5. Since Q6 can receive ``l'' at the level from another transmitting circuit (not shown), the receiving operation may occur during the transmitting operation in this way.The transmission m-use logic circuit CC that has determined this is , knowing that there has been a transmission/reception collision, the transmitting circuit stops transmitting 1121 burst 7c and can continue only receiving operations.

Furthermore, in the transmitting/receiving circuit shown in Fig. m1, when the transmitting transistors Ql and Q4 are on, the transistor Q5 is on at the same time.

2 # Q Transistor when 3 is on. 6 is turned on, the transmitting signal can also be monitored by the receiving circuit.

In this case, the lowest receiving level is the transistor.

5, C60 base-emitter and diode D1. D
If the forward voltage drop of 2 is Vbe, more than 2be is required, but in order to ensure the stability of the receiving operation and to adjust the bias voltage, resistors R3 and R4, which are larger than the transistors Q5 and R2, are connected. When connected between the base and emitter of Q6, the minimum reception level will be within the range of 2.beta. to 4.beta. Assuming Vbe = 0.7 (V), if the minimum reception level is 4vbe = 2.5 (V), the maximum allowable transmission loss for a transmission level of 5 [V] is approximately 5 (dB)0 or If Schottky diodes with a low forward voltage drop of, for example, 0.2 (V) are used for the diodes DI and D2, the maximum allowable transmission loss can be set to about 9 (dB),
Transmission speed is several 10 Ckb/s or less, transmission distance is several 10 Ckb/s or less
100 (in the following cases, the receiving circuit of the present invention can be fully put to practical use).

In addition,#! In Figure 1, when direct current is superimposed on the transmission line,
As the AC/DC separation capacitor, only one of C1 and C2 may be connected. Of course, if DC superposition is not performed, both the AC and DC separation capacitors CI and C2 are unnecessary.

FIG. 2 shows an embodiment in which the transmitting/receiving circuit shown in FIG. 1 and the cable CA serving as a transmission line are coupled by capacitors C1 and C2 without intervening a pulse transformer.

Further, FIG. 3 shows an embodiment in which the transmitting/receiving circuit and the cable CAO are directly connected without intervening a pulse transformer or a capacitor.

The transmission and reception operations of each embodiment shown in FIGS. 2 and 3 are similar to those of the embodiment shown in FIG.
BTL circuit type transmitter circuits can provide differential balanced output without a pulse transformer, and if a large common-mode component rejection ratio or complete isolation is not required, the transmitter/receiver circuit and transmission line as shown in Figure @2. A capacitor may be used for coupling between the two, or if direct current superposition is not required in the transmission line, a direct connection may be made as shown in FIG.

In Fig. 2, if AC/DC separation is simply performed using a capacitor between the transmission path where DC is superimposed and the transmitting/receiving circuit, it is sufficient to connect only one of C1 or C2.

In each of the embodiments shown in FIGS. 1 to 3, the noise resistance can be further improved by adding capacitors between the bases and emitters of the receiving transistors Q5 and C6. Also, as mentioned earlier, the transistor Q5
If the collector outputs of C6 and C6 are taken out individually, ten levels of the violation λMI code or the double-flow binary code can be used individually.

〔Effect of the invention〕

As explained above, according to the present invention, a transmitting/receiving circuit for transmitting data at low speed over a short distance transmission path can be configured with only a few transistors without the need for compensating for waveform distortion. The transmitter/receiver circuit according to the present invention has the advantage that even when the transmitter/receiver circuit is constructed from individual parts, the cost can be reduced, and it is also suitable for implementing an IC together with a transmission control circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figures 2 and 3 are circuit diagrams showing one embodiment of the present invention.
The figures are circuit diagrams showing other embodiments of the present invention. Code explanation Ql~Q7...Transistor, Dl and D2.
...Diode, R1-R5...Resistance,
C1 and C2...Capacitor, PW...
...Power supply, ■Junin-biV. ...Power supply m, PT... tune pulse transformer, T
l~T4...Terminals of the pulse transformer as well as input/output terminals for transmitting/receiving signals, logic circuit for controlling transmission between CC Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki

Claims (1)

[Claims] 1) One polarity (first polarity) and the other polarity (#
A transistor pair III consisting of series connection of @1 and a second transistor is connected between the polarity of I2 and
and #! consisting of a series connection of each of the fourth transistors. 2
The #! transistor pairs are connected in parallel. The connection point between both transistors in one pair (first transistor connection point) is connected to the 16th communication terminal, and that in the second pair (
second transistor connection point) #! 2 communication terminals, respectively, and control outputs from the transmission control logic circuit. by turning on the first transistor and the fourth transistor, the second transistor and the third transistor, or turning on none of the transistors, through the first and second communication terminals. between the first communication terminal and the polarity of the power supply terminal 1;
a first resistance circuit consisting of two resistors connected in series, and between the second communication terminal and the first polarity of the power source;
Similarly, a second resistance circuit consisting of two resistors connected in series is connected, and the connection point between both resistors in the H1 resistance circuit (first resistance connection point) and that in the fM2 resistance circuit (first resistance connection point) are connected. connecting one end and the other end of a circuit consisting of two diodes connected with opposite polarities to the first resistor connecting point), and connecting the base of the fifth transistor to the first resistive connecting point; connecting the paces of a sixth transistor to the second resistor connection points, respectively;
The emitters of each of the fifth and sixth transistors are connected to the polarity of the power source, respectively, and the collectors are led to the signal input side of the logic circuit, respectively, and the first communication terminal and the second communication terminal. Depending on which of the terminals receives a higher potential signal, one of the fifth and sixth transistors is turned on, or if a signal with the same potential is received at the first communication terminal and the second communication terminal. data characterized by comprising one or both of the following: a receiving circuit that is capable of inputting a binary code or a ternary code into the logic circuit by not turning on both the fifth and sixth transistors; Transmission/reception circuit for transmission.