JPS60250455A - Interruption processing system - Google Patents

Abstract

PURPOSE:To facilitate easy connection between a processor and peripheral controller by producing artificially the bus error signals which execute agin bus cycles up to the number of times with which a vector can be read. CONSTITUTION:An interruption control circuit 10 in a processor 1 sets an acknowledge signal (a) at L by an interruption signal given from a peripheral controller 3. A timer 13 is started when a flag 12 is set at L, and the timer output is set at L after a prescribed period of time. This output of the timer 13 is informed to the circuit 10 in the form of a command signal (c) for second execution of bus cycle. The circuit 10 executes the bus cycle again. Thus the signal (a) is set again at L. The vector (b) delivered from a vector generating circuit 14 is read to a vector address register 11 of the processor 1.

Description

Detailed Description of the Invention [Field of Industrial Applicability] The present invention relates to an interrupt processing method in a computer system, and in particular, in bus 1 vector interrupts, a processor uses a vector output from a peripheral control device. The present invention relates to an interrupt processing method having a means for arbitrarily controlling the timing jig for reading.

[Prior art]

One of the interrupt methods used in computer systems is the bus vector interrupt method. bus·
In the vector interrupt method, an interrupt request is sent to the processor from the outside, and when the interrupt request is accepted by the processor, the processor starts an interrupt acknowledge cycle, and takes in the vector □- outputted on the data bus by the interrupt side. Execute the corresponding interrupt processing.

The vector is used to directly or indirectly specify the start address of the interrupt processing program.

Next, a specific example will be explained.

FIG. 2 shows one conventional example, in which 1 is a block recorder 4J, 2 is a memory, 3 to 5 are peripheral control devices, 6 is a data bus, 7 is a control bus, 8 is an interrupt signal line, 9
indicates the interrupt acknowledge/noise signal line. For the sake of simplicity, it is assumed that interrupts from the peripheral control devices 3 to 5 are prioritized by daisy chain control. Therefore, even if an interrupt cause occurs simultaneously in a plurality of peripheral control devices, it will depend on the order in which the peripheral control devices are connected. An interrupt from one higher-level peripheral control device is accepted.

When Prop No. 1 detects an interrupt signal from a peripheral control device, it checks whether interrupt prohibition is masked or not, and if it is not masked, executes an interrupt acknowledge cycle. , outputs an interrupt acknowledge signal.

3 shows an interrupt acknowledge signal outputted from the processor, and 3 shows a vector outputted onto the data bus by the peripheral control device on the interrupt side in response to the interrupt acknowledge signal. As shown, the vector can be read by the processor if it is output from the peripheral controller within the interrupt acknowledge cycle.

[Problem that the invention seeks to solve]

Generally, the processor IC and the peripheral control device 1c are designed to have a combined interface as one family. There is no problem when using such a combination of ICs, but the response of the peripheral control device IC used does not match the processor, and in order to output the vector shown in As shown in (2), for example, there are cases where two interrupt acknowledge cycles are required. Conventionally, when there was a mismatch between the processor d and the peripheral control device IC, it was necessary to abandon the use of the peripheral control device IC or to add a special adapter circuit for timing alignment. Ta.

[Means for solving problems]

The present invention utilizes a hash cycle re-execution function that the processor normally has when it is not possible to return a vector within the interrupt acknowledge cycle of the processor due to poor compatibility with the peripheral control device. All are generated virtually multiple times, allowing the vector to be read. The hash cycle re-execution function of this processor is generally activated by a hash error signal sent to the processor by a peripheral control device when a data transfer failure occurs during a hash cycle, and is used to re-execute the hash cycle. has been done.

In the present invention, attention is paid to the fact that the interrupt 7 logic cycle is a bus cycle for reading the vector of the data bus 10, and a hash error signal that causes the hash cycle to be re-executed is used as a hash cycle re-execution command signal for the necessary number of times, i.e. The processor and the peripheral control device are easily connected by the number of times that the vector can be read or by pseudo-generating the vector.
Equipped with a processor and a peripheral control unit that have a vector interrupt function and a bus cycle re-execution function, the processor can read a vector in one bus cycle, but the peripheral control '4' IA device has multiple hash cycles. In computer systems that require peripheral control device η
When the processor starts the hash cycle and issues an interrupt acknowledge signal in response to an interrupt signal from It is characterized by repeating only

〔Example〕

The details of the present invention will be explained below based on examples.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 5 is an operation timing chart thereof.

In FIG. 1, 1 is a processor, 3 is a peripheral control device,
10 represents an interrupt control circuit, 11 a vector address register, 12 an interrupt acknowledge flag, 13 a timer, and 14 a vector generation circuit. Also, ■ is an interrupt acknowledge signal, ■ is a vector, and ■ is a bus cycle re-execution command signal, and these signals ■, ■, ■
correspond to the signal waveforms ■, ■, and ■ in FIG. 5, respectively.

The interrupt control 0 circuit 10 in the processor 1 receives an interrupt signal from the peripheral control device 3 and sets the interrupt acknowledge signal When the flag 12 becomes L, the timer 13 is activated and after a predetermined time, the output is set to °L.The output of the timer 13 is controlled as a Hass cycle re-execution command signal ■ by interrupt. The circuit 10 is notified.

When the interrupt control circuit 10 identifies the hash cycle re-execution command signal ■, it sets the interrupt acknowledge signal to "1 bit" and immediately re-executes the hash cycle. As a result, the interrupt acknowledge signal ■ goes low again. becomes.

At this point, the vector generation circuit 14 is in a state where it can output the vector ■, and the output vector ■ is
It is read into the vector address register 11 of the processor 1 and used to address the corresponding interrupt processing program.

〔Effect of the invention〕

As described above, according to the present invention, even if there is an inconsistency in the interface between the processor IC and the peripheral control device IC using the hash-lid interrupt method or the vector read timing, the hash cycle re-execution function can be performed. The very simple means utilized allows for easy timing alignment and increased flexibility in system configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of a conventional example, FIG. 3 is an operation timing diagram of vector reading when the processor and peripheral control device are matched, and FIG. The figure is an operation timing diagram of vector reading when the peripheral control device requires a plurality of interrupt acknowledge cycles, and FIG. 5 is an operation timing diagram of the embodiment of FIG. 1. In the figure, 1 is a processor, 3 is a peripheral control device, 10 (j interrupt control circuit), 11 is a hector atreslensk, 1
2 is the interrupt acknowledge flag, 13 is the timer,
4B-Kuku generation circuit is shown. Patent Applicant Banafacom Co., Ltd. Representative Patent Attorney For Hase Car Seat (1 person outside) O 1 O 2 Diagram

Claims (1)

[Claims] Equipped with a processor and a peripheral control device that have a hash vector interrupt function and a bus cycle re-execution function, the processor can read vectors in one hash cycle, but the peripheral control device can read out vectors in multiple hash cycles. In the required computer system, when a processor starts a bus cycle and issues an interrupt acknowledge signal in response to an interrupt signal from a peripheral control device, the peripheral control device responds with a hash cycle re-execution command signal,
An interrupt processing method characterized in that the process of causing a processor to re-execute a bus cycle is repeated multiple times.