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JPS60249449A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60249449A
JPS60249449A JP59106046A JP10604684A JPS60249449A JP S60249449 A JPS60249449 A JP S60249449A JP 59106046 A JP59106046 A JP 59106046A JP 10604684 A JP10604684 A JP 10604684A JP S60249449 A JPS60249449 A JP S60249449A
Authority
JP
Japan
Prior art keywords
data
communication means
serial
bit
serial data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59106046A
Other languages
Japanese (ja)
Other versions
JPH0582096B2 (en
Inventor
Yuji Kakinuma
柿沼 雄二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP59106046A priority Critical patent/JPS60249449A/en
Publication of JPS60249449A publication Critical patent/JPS60249449A/en
Publication of JPH0582096B2 publication Critical patent/JPH0582096B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To transmit and receive data of two systems independently of each other and to transmit and receive data of a multibit length by providing two systems of communication means which can transmit and receive individual bits of data in serial, and connecting communication means in series on demand. CONSTITUTION:In the normal operation, serial data inputted to an input terminal 11 is converted to parallel data by the first communicating means 10 having transmission and reception functions and is sent to a processor 8. Data from the processor 8 is converted to serial data by the first communicating means 10 and is outputted from an output terminal 12. The second communicating means 13 is constituted similarly to the means 10 and transmits and receives data independently. When long bit data is transmitted and received, the output of the means 10 and the input of the means 13 are connected, and long bit serial data from the input terminal 11 is supplied to the processor as parallel data from means 10 and 13. Data from the processor 8 is converted to serial data by means 10 and 11 and is outputted from an output terminal 15.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は独立した2系統のディジタル信号のデータを、
ビット毎にシリアルに同時に送受信することができる半
導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides data of two independent digital signals.
The present invention relates to a semiconductor device that can serially transmit and receive bits at the same time.

従来例の構成とその問題点 近年、マイクロプロセッサなどの半導体装置は優れた制
御能力を持つため、電子機器への応用が進んでいる。制
御が複雑になるにつれ、ディジタル信号のデータを他の
電子機器との間でシリアルに送受信する必要が生じてき
た。データのシリアルな送受信は電子機器の省配線化に
役立つからである。従来のマイクロプロセッサなどの半
導体装置はこうしたデータをビット毎にシリアルに送受
信する通信手段を1系統だけ備えていた。
Conventional configurations and their problems In recent years, semiconductor devices such as microprocessors have been increasingly applied to electronic devices because they have excellent control capabilities. As control becomes more complex, it has become necessary to serially transmit and receive digital signal data to and from other electronic devices. This is because serial transmission and reception of data is useful for reducing wiring in electronic devices. Conventional semiconductor devices such as microprocessors have only one system of communication means for serially transmitting and receiving such data bit by bit.

第1図は、従来の半導体装置の一実施例を示すブロック
図である。1はマイクロプロセッサなどを一体に形成し
た半導体装置、2キマイクロプロセノサ本体、3けデー
タバス、4はデータをシリアル(で送受信する通信手段
、6げシリアルデータの入力端子、6はシリアルデータ
の出力端子でめるO 簡単に動作を説明すると、受信の場合は入力端子6より
シリアルデータを通信手段4に入力しデータバス3を介
してマイクロプロセッサ本体2がデータを受け処理する
。送信の場合はマイクロプロセッサ本体2のデータをデ
ータバス3を介して通信手段4にロードし出力端子6か
らシリアルデータとして送り出す。
FIG. 1 is a block diagram showing one embodiment of a conventional semiconductor device. 1 is a semiconductor device that integrates a microprocessor, etc.; 2 is a microprocessor body; 3 is a data bus; 4 is a communication means for transmitting and receiving data serially; 6 is a serial data input terminal; 6 is a serial data input terminal; To briefly explain the operation, in the case of reception, serial data is input to the communication means 4 from the input terminal 6, and the microprocessor body 2 receives and processes the data via the data bus 3.In the case of transmission loads the data of the microprocessor main body 2 into the communication means 4 via the data bus 3, and sends it out from the output terminal 6 as serial data.

しかしながら上記のような構成では、データを送受信す
る相手の電子機器が独立[2系統ある場合には同時送受
信が不可能であり、結果として全体の制御能力を低下孕
せるという問題点を有していた0 発明の目的 本発明は上記従来の問題点を解消するもので、データを
ビット毎にシリアルに送受信する通信手段を独立[2系
統備え、かつ両者をカスケード接続することも可能な半
導体装置を提供することを目的とする。
However, the above configuration has the problem that the electronic devices to which data is sent and received are independent (if there are two systems, simultaneous transmission and reception is impossible, and as a result, the overall control ability is reduced). OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides a semiconductor device having two independent systems of communication means for serially transmitting and receiving data bit by bit, and which can also be connected in cascade. The purpose is to provide.

発明の構成 本発明はディジタル信号のデータをビット毎にシリアル
に送信および受信可能な第1の通信手段と、前記第1の
通信手段とけ独立にディジタル信号のデータをビット毎
にシリアルに送信および受信可能な第2の通信手段と、
前記第1の通信手段の出力を前記第2の通信手段の入力
にカスケード接続する連結手段とを備えた半導体装置で
めシ、独立に2系統の通信手段を持つことにより、異な
る2系統の7リアルデータを同時に送受信したり、多ビ
ット長のシリアルデータを送受信したりすることのでき
るものである。
Structure of the Invention The present invention provides a first communication means capable of serially transmitting and receiving digital signal data bit by bit, and a first communication means capable of serially transmitting and receiving digital signal data bit by bit independently of the first communication means. a possible second means of communication;
A semiconductor device is provided with a connecting means for cascading the output of the first communication means to the input of the second communication means. It is capable of simultaneously transmitting and receiving real data and transmitting and receiving multi-bit serial data.

実施例の説明 第2図は本発明の一実施例を示すブ0.7り図である。Description of examples FIG. 2 is a block diagram showing one embodiment of the present invention.

第2図において、7はマイクロプロセッサなどを一体に
形成した半導体装置、8けマイクロプロセッサ本体、9
はデータバス、10ケテータをシリアルに送受信する第
1の通信手段、11けシリアルデータの入力端子、12
げシリアルデータの出力端子、13げデータをシリアル
に送受信する第2の通信手段、14けシリアルデータの
入力端子、15はシリアルデータの出力端子、16け通
信手段1oの出力、17げ通信手段1oと通信手段13
をカスケード接続する連結手段である。
In FIG. 2, numeral 7 denotes a semiconductor device integrally formed with a microprocessor, an 8-digit microprocessor body, 9
is a data bus, a first communication means for serially transmitting and receiving 10 digits, an input terminal for 11 digit serial data, 12
13 is a second communication means for serially transmitting and receiving data, 14 is an input terminal for serial data, 15 is an output terminal for serial data, 16 is an output of the communication means 1o, 17 is a communication means 1o and communication means 13
This is a connecting means for cascading.

以上のよって構成された本実施例の半導体装置について
、以下第2図のブロック図にもとづいてその動作を説明
する。
The operation of the semiconductor device of this embodiment constructed as described above will be explained below based on the block diagram of FIG. 2.

まず、独立VC,2系統のデータを処理する場合は連結
手段17は入力端子14からの信号を選ぶようにしてお
く。受信されるシリアルデータは入力端子11よ多通信
手段10vC入力され、データノくス9を介してマイク
ロプロセッサ本体8でデータ処理される。送信されるマ
イクロプロセッサ本体8のデータはデータバス9を介し
て通信手段1゜にロードされ、出力端子12からシリア
ルデータとして送り出される。
First, when processing data from two independent VC systems, the coupling means 17 selects the signal from the input terminal 14. The received serial data is inputted to the multi-communication means 10vC through the input terminal 11, and is processed by the microprocessor body 8 via the data node 9. The data to be transmitted from the microprocessor body 8 is loaded into the communication means 1° via the data bus 9, and sent out from the output terminal 12 as serial data.

同様にもう一方の受信されるシリアルデータは入力端子
14より連結手段17を経由して、通信手段13に入力
されデータバス9を介してマイクロプロセッサ本体8で
データ処理される。送信されるマイクロプロセッサ本体
8のデータはデータバス9を介して通信手段13にロー
ドされ、出力端子16からシリアルデータとして送り出
される。
Similarly, the other received serial data is input to the communication means 13 from the input terminal 14 via the connection means 17 and is processed by the microprocessor body 8 via the data bus 9. The data to be transmitted from the microprocessor body 8 is loaded into the communication means 13 via the data bus 9, and sent out from the output terminal 16 as serial data.

通信手段10と通信手段13のビット処理単位は通常8
ビツトであるが、何ビットであってもさしつかえない。
The bit processing unit of communication means 10 and communication means 13 is usually 8.
It is a bit, but any number of bits is acceptable.

多ビット長のデータを処理する場合は、連結手段17に
より第1の通信手段10と第2の通信手段13をカスケ
ード接続する。連結手段17は通信手段1oの出力16
を通信手段13の入力として選択するようにしておく。
When processing multi-bit data, the first communication means 10 and the second communication means 13 are connected in cascade by the connection means 17. The connecting means 17 connects the output 16 of the communication means 1o.
is selected as an input to the communication means 13.

これにより通信手段1oと通信手段13は一体となって
入力端子11からの多ビット長シリアルデータを受信し
、データバス9.を介してマイクロプロセッサ本体av
Cデータを渡すことができる。反対に、マイクロプロセ
ッサ本体8の多ビツトデータはデータバス9を介して通
信手段1oおよび通信手段13にロードされ、出力端子
15から多ビット長シリアルデータとして送信されるっ 以上のように本実施例によれば、独立に2系統の7リア
ルデータの送受信を同時処理したり多ビ、ト長のシリア
ルデータの送受信を処理できるので、従来てくらべて大
幅にシリアルデータ処理能力が向上している。従ってこ
の半導体装置は電子機器の制御においてディジタル信号
のデータ送受信に要する配線の削減に大きく寄与するも
のである0 発明の効果 本発明はシリアルデータを送受信する第1の通信子段と
第2の通信手段を独立に設けることにより、種類の異な
る2系統の電子機器との間で同時にシリアルデータの送
受信をすることができ、さらに第1の通信手段と第2の
通信手段を連結することにより多ビット長のシリアルデ
ータも送受信できるので、電子機器の制御においてディ
ジタル信号のデータ送受信に要する配線を大幅に削減で
きるという効果を得ることができる優れた半導体装置を
実現できるものである。
As a result, the communication means 1o and the communication means 13 together receive the multi-bit serial data from the input terminal 11, and the data bus 9. Microprocessor body through AV
C data can be passed. On the contrary, the multi-bit data of the microprocessor main body 8 is loaded into the communication means 1o and the communication means 13 via the data bus 9, and is transmitted from the output terminal 15 as multi-bit serial data. According to , it is possible to simultaneously process the transmission and reception of two systems of 7-real data and to process the transmission and reception of multi-bit and long serial data, so the serial data processing ability has been greatly improved compared to the past. Therefore, this semiconductor device greatly contributes to reducing the wiring required for data transmission and reception of digital signals in the control of electronic equipment. By providing independent means, it is possible to simultaneously transmit and receive serial data between two different types of electronic devices, and furthermore, by connecting the first communication means and the second communication means, multi-bit Since long serial data can also be transmitted and received, it is possible to realize an excellent semiconductor device that can significantly reduce the wiring required for data transmission and reception of digital signals in controlling electronic equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の一実施例を示すブロック図
、第2図は本発明の半導体装置の一実施例を示すブロッ
ク図である。 1・・・・・半導体装置、2・・・・マイクロプロセッ
サ本体、3・・・・・・データバス、4・・・・・・通
信手段、5・・・・・・入力端子、6・・・・出力端子
、7・・・半導体装置、8・・・・・・マイクロプロセ
ッサ本体、9・・・データバス、1o・・・・・・第1
の通信手段、11・・・・入力端子、12・・・・・・
出力端子、13・・・・・第2の通信手段、14・・ 
・入力端子、16・・・・・・出力端子、16・・・・
・・第2の通信手段の出力、17・・・・連結手段。
FIG. 1 is a block diagram showing an embodiment of a conventional semiconductor device, and FIG. 2 is a block diagram showing an embodiment of the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... Microprocessor body, 3... Data bus, 4... Communication means, 5... Input terminal, 6... ...Output terminal, 7...Semiconductor device, 8...Microprocessor body, 9...Data bus, 1o...First
communication means, 11...input terminal, 12...
Output terminal, 13...Second communication means, 14...
・Input terminal, 16... Output terminal, 16...
... Output of second communication means, 17... Connection means.

Claims (1)

【特許請求の範囲】[Claims] ディジタル信号のデータをビット毎にシリアルに送信お
よび受信−可能な第1の通信手段と、前記第1の通信手
段とは独立にディジタル信号のデータをビット毎にシリ
アルに送信および受信可能な第2の通信手段と、前記第
1の通信手段の出力を前記第2の通信手段の入力にカス
ケード接、読する連結手段とを備えたことを特徴とする
半導体装置。
a first communication means capable of serially transmitting and receiving data of a digital signal bit by bit, and a second communication means capable of serially transmitting and receiving data of a digital signal bit by bit independently of said first communication means; A semiconductor device comprising: communication means; and connection means for cascading and reading the output of the first communication means to the input of the second communication means.
JP59106046A 1984-05-25 1984-05-25 Semiconductor device Granted JPS60249449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59106046A JPS60249449A (en) 1984-05-25 1984-05-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59106046A JPS60249449A (en) 1984-05-25 1984-05-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60249449A true JPS60249449A (en) 1985-12-10
JPH0582096B2 JPH0582096B2 (en) 1993-11-17

Family

ID=14423687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59106046A Granted JPS60249449A (en) 1984-05-25 1984-05-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60249449A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58198986A (en) * 1982-05-17 1983-11-19 Tamura Electric Works Ltd Signal transmission system of key telephone device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58198986A (en) * 1982-05-17 1983-11-19 Tamura Electric Works Ltd Signal transmission system of key telephone device

Also Published As

Publication number Publication date
JPH0582096B2 (en) 1993-11-17

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