JPS60245313A - A/d-d/a converter - Google Patents

Abstract

PURPOSE:To obtain an A/D-D/A converter which has a small LSI chip and also can change a time division utilization ratio by a program, by switching as a time division and using one A/D converter for both A/D conversion and D/A conversion. CONSTITUTION:A D/A converter 27 is provided on an A/D converter for comparing successively an analog input 11 and a value of a D/A converting part 14, which becomes a comparison reference value. This converter is constituted so as to be brought to a switching control by an output pulse of a timing generating part 15 having an A/D enable flag 20 and a D/A enable flag 24, sof that the D/A converting part 14 is switched to an A/D converter and a D/A converter and operated by a multiplexer part 16. In this state, when sending out a signal of the A/D enable flag 20, a D/A output is outputted from an A/D register part 13, and when sending out a signal of the D/A enable flag 24, an analog converting output 17 to an input digital signal of a D/A register part 19 is outputted through the multiplexer part, and also the time sending out the signal of both the flags can be controlled variably.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an A/D-D/A converter.

Conventional configurations and their problems In recent years, A/D and D/A converters have been developed using microcomputers (
They are beginning to be integrated on-chip as a peripheral interface function for microcontrollers.

A conventional successive approximation type A/D converter will be explained below.

Figure 1 shows a block diagram of a conventional example, where 1 is an A/D input terminal, 2 is an analog comparator, and 3 is an A/D input terminal.
D register section, 4 is D/A conversion section using ladder resistance, 6
is a timing generator.

The operation of the conventional successive approximation type A/D converter configured as described above will be described below.

First, the timing generating section 5 resets the A/D register section 3. Next, the analog comparator 2
Compare the value of input terminal 1 and the output value of D/A converter 4,
The most significant bit of the A/D register section 3 is sent. As a result, the D/A converter 4 outputs a corresponding analog value,
Obtain the comparison reference voltage for the next bit. Similarly, the lower bits are set sequentially, and the final result is obtained from the A/D register section. Such a successive approximation type A/D converter is already well known, and detailed explanation will be omitted.

One of the conventional methods for integrating a D/A converter on a microcomputer is to provide a pulse width modulation (PWM) output and perform integration using a circuit external to the microcomputer.

However, in the above configuration, since the A/D and D/A are provided as separate circuits, there is a problem that the LSI chip area becomes large. Additionally, these specifications had the disadvantage of being hard-wired.

Purpose of the Invention The present invention solves the above conventional problems by providing one A/D converter and using it for both D/D conversion and D/A conversion in a time-sharing manner, thereby reducing the LSI chip size. 'l'
・In addition to increasing the A/D and D
/A converter.

Structure of the Invention The present invention includes an A/D register section, a D/A register section,
An A/D/D/D/D/D/D converter that includes a multiplexer section, a D/A conversion section, an analog comparator section, and a timing generation section having an A/D enable flag and a D/A enable flag.
It is an A converter that shares the D/A for D/D conversion and the D/A for D/A conversion in a time-sharing manner to reduce the circuit scale and LSI chip size, and also to reduce the A/D enable flag. .

The D/A enable flag allows optimization such that the time ratio for time division use can be changed depending on the purpose. For example, when only one channel of the A/D conversion unit and D/A conversion is used, timings allocated for other conversions can be skipped.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a block diagram of an A/D-D/A converter in an embodiment of the present invention.

11 is an A/D input terminal, 12 is an analog comparator,
13 is an A/D register section, 14 is a D/A conversion section, 16 is a timing generation section, and 27 is a D/A that outputs D/A conversion.
Channel. The timing generator 16 is further divided into the following elements.

20 is an A/D enable flag, 21 is a pre-centered binary counter, 22 is a start address designation unit that generates a preset value for the counter 21, 23 is a decoder, 24
25 is a D/A enable flag, 25 is an end designation unit that generates a count end value for the counter 21, and 26 is a comparator. The D/A channel 27 is further composed of the following elements. 17 is an output terminal for the D/A conversion result, 18 is a sample hold circuit, and 19 is a D/A register section for storing a value to be D/A converted.

The operation of the A/D-D/A converter of this embodiment configured as described above will be explained below.

The operation of this embodiment can be roughly divided into two parts. The D/A conversion operation uses normal successive approximation type A/D conversion and ladder resistance, and the D/A conversion has 8 channel outputs. The A/D-D/A converter of the embodiment is of the clock synchronous type and uses 8 clock pulses to perform 8-bit A/D conversion. D/A conversion requires a thick lock pulse per channel, and when all eight D/A channels are enabled, D/A conversion is completed in eight clock pulses.

A/D conversion and D/A conversion can be enabled or disabled separately.

Next, the detailed configuration and operation of each block of this embodiment will be explained.

FIG. 3 is a detailed circuit diagram of the timing generator. 28
is an A/D enable flag, which outputs 1°° when A/D conversion is enabled. Reference numeral 29 is a start address designation section which outputs "oooo" when A/D conversion is enabled, and outputs 1000 when disabled. 30 is a presettable binary counter, which operates in synchronization with the falling edge of the clock pulse. 31 is a D/A enable flag, which indicates how many of the eight D/A channels are enabled. 32 is an end address designation part, which is set when all D/A channels are disabled.
For example, when 4 channels are enabled, fi"1011" is output.

33 is a comparator, which outputs 1 from the A=B output side when the output value of the end specifying section 32 and the output of the counter 30 match.
Output. 34 is a D latch, which takes in the output value of the comparator 33 while the clock pulse is at a high level, and generates a load pulse for the counter 3o. 35
is a 4→16 line decoder. 36 is a square wave clock oscillation section.

FIG. 4 shows the operation timing of the timing generator.

As the clock pulse (CP) falls, the output of the counter 30 (BCO-BC4) in FIG. 3 changes, and the output of the decoder 36 (CPO to CP15) changes.

FIG. 5 is a detailed circuit diagram of the A/D register section.

37 is a D flip-flop, which operates in synchronization with the falling edge of the clock pulse. The output value (COMP) of the analog comparator 12 in Fig. 2 is latched, and the A/
Outputs the intermediate value (CMD) of the D conversion result. 38-45
is an AND gate and generates pulses for the second half of CPO, ~CP 15. 46 to 63 are 8-bit D latches that store A/D conversion results. D latch 46~
63 is the load pulse (LOAD) of the counter 30 in FIG.
) is reset when it occurs.

FIG. 6 is an operation timing chart of the A/D register section.

At the start of A/D conversion, the D latches 46 to 63 in FIG. 5 are cleared up to the first half of CPo. D latch 4 in the second half of CPO
6, and the D latch 47 is set in the second half of CP1. In the same manner, the D latch 53 is set in the second half of CP7 to obtain an 8-bit A/D conversion result.

64 to 61 are 8-bit 8-bit D-OR gates. The most significant bit (BC3) of the output of the counter 30 in FIG. 3 is r''
When it is 0'', the AD register section output (ADO to 7) in FIG. 2 is selected and output, and when it is 1, the D/A register section output (DAO to DAT) side in FIG. 2 is selected and output.

FIG. 8 is an operation timing chart of the multiplexer section.

The output (BC3) of the counter 30 in Fig. 3 is ' o '' o
At "1°", A/D conversion is performed, and when "1°", D/A conversion is performed.

FIG. 9 is a detailed circuit diagram of the D/A converter. 62 is a resistor array, and a total of 266 resistors are arranged in the X-Y direction. 63 is a decoder, and 64 is an analog multiplexer. The decoder 63 receives the multiplexer section output (MPX) shown in FIG.

~MPXy), and the input is determined by the resistor array 62
The D/A output signal (
DAOUT). 66 is a bar 11.66 for lowering the output impedance of the analog value. When the golf lug 20 and the D/A enable flag 24 are both disabled, the power to the buffer 66 is cut off.

FIG. 10 is a detailed circuit diagram of the sample and hold section.

66 is a transistor, 67 is an AND gate, 68 is a capacitor, 69 is a buffer, and 70 is a D/A output terminal. During sampling, the D/A converter output signal (DAOU
T) is transmitted to capacitor 68 by making transistor 66 conductive. The gate 67 of the transistor 66 opens and becomes conductive in the latter half of the clock pulse CP8. In Figure 10, D/A
Although only one channel is shown, in the embodiment there are eight channels, and sampling is performed in the same manner at CP9 to CP15. Buffer 7 of the D/A channel whose D/A enable flag 24 in FIG. 2 indicates a disabled state.
0 cuts off the power.

FIG. 11 shows an example of execution timing according to this embodiment.

A is an example of timing when A/D conversion and D/A conversion are performed in 4 channels. B is an example of timing when D/A conversion is reduced to 2 channels, and C is a timing example in which D/8 conversion is reduced to 1 channel. d and e are timing examples when only VA conversion is performed. When performing only D/A conversion, CPo~
CP7 does not occur. As for the A/D conversion result, an 8-bit result is obtained after the latter half of CF2. Note that in FIG. 11, the underline indicates the load pulse.

Note that although the means for cutting off the power supply to the analog buffer is not shown in the figure, it is controlled by inserting a transistor in series with the power supply.

Effects of the Invention The A/D and D/A converter of the present invention includes an A/D register section, a D/A register section, a multiplexer section, a D/A conversion section, an analog comparator section, and an A/D register section, a D/A register section, a multiplexer section, a D/A conversion section, an analog comparator section, and an A/D An A/D-D/A converter equipped with an enable flag and a timing generation unit having a D/A enable flag; reduction of LSI chip size by time-sharing use of the D/A converter;
By setting the A/D enable and D/A enable flags, the time-sharing utilization ratio of the D/A converter can be changed by a program, and the A/D and D/A conversion timing can be optimized.

The number of D/A converters used and A
There is no need to change the hardware (of the microcontroller) depending on whether a /D converter is required, so LSI design and
There is no need to create a new program for the SI tester, which saves design and manufacturing man-hours.

Furthermore, since the A/D-D/A usage ratio can be dynamically changed by a program, high-speed conversion can be performed only for a specific period. In addition, when A/D or D/A conversion is not required, the power to the analog section buffer amplifier, which consumes a large amount of power, can be cut off by disabling the A/D enable flag or D/A enable flag. can. Logic part is 0M
If it is configured with O3 or the like, the power consumption will be a little low, but since the analog part will be relatively thick, the power cutoff effect will be great.

In particular, switching the microcontroller clock to a lower speed

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional A/D converter, Fig. 2 is a block diagram showing an embodiment of the present invention, and Figs. 3 and 4 are circuit diagrams of the timing generator of the same embodiment. 6 and 6 are A/D register section circuit diagrams and their timing diagrams of the same embodiment; FIGS. 7 and 8 are multiplexer section circuit diagrams and their timing diagrams of the same embodiment;
FIG. 9 is a circuit diagram of the D/A converter section of the same embodiment, FIG. 10 is a circuit diagram of the sample hold section of the same embodiment, and FIG. 11 is an execution timing chart of the same embodiment. To 13.../D register section, 19...
D/A register section, 16... Multiplexer section, 14... D/A conversion section, 12... Analog comparator section, 18... Sample hold section , 20...A/D enable flag, 2
4...D/A enable flag, 16...
...Timing generation part, 29...Start specification part,
32... End specification section, 30... Presettable counter, 33... Comparator, 35
・・・・・・Decoder - Fig. 2 Fig. 3 Fig. 4 Fig. 5 Section 6 Fig. 8 Fig. 8C3A/A variation Fig. 10 Fig. 11 e'/11/C/l, /4?

Claims (1)

[Claims] (1) Selecting an A/D register section for storing A/D conversion results, a D/A register section for storing values to be D/A converted, and one of the two registers. A multiplexer section, a D/A converter section that converts the output value from the multiplexer section into an analog value, and a comparison result of the input value to be A/D converted and the output value from the D/A converter section. An analog comparator section that outputs to the register section, a sample hold section that outputs the output value of the D/A conversion section to the D/A conversion output terminal, and an A/D enable flag that indicates whether or not to perform A/D conversion. and D/
A: An A/D-D/A converter comprising a timing generator for setting the A/D register, switching a multiplexer, and generating a sample hole signal according to a D/A enable flag indicating whether or not to perform conversion. (2) The timing generation section includes a start specification section and an end specification section that are controlled by an A/D enable flag and a D/A enable flag, and a presettable counter section that uses the output from the start specification section as a preset input value. , the output value from the presettable counter and the output value from the end designation section are used as comparison inputs, and the preset (ij""i) of the presettable counter is determined based on the comparison result.
'l: A/D, D/ according to claim 1, which is constituted by a comparator section that outputs and a decoder section that decodes the output value from the presettable counter.
A converter. (3) The A/D converter according to claim 1, wherein the A/D converter includes an 8/D enable flag and a switch circuit that cuts off the current when the D/A enable flag is in a disabled state. , a D/A converter. (4) The sample and hold section includes an A/D enable flag and a switch circuit that cuts off current when the D/A enable flag is in a disabled state. A/D-D/A converter.