JPS60245172A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an OFF current and to respond ON or OFF at a high speed by implanting ions to a nonsingle crystal semiconductor to which hydrogen or halogen element is added in the prescribed amount, annealing it with strong light to grow crystal as an impurity region. CONSTITUTION:A nonsingle crystal semiconductor (Si) 2 which contains hydrogen of density higher than 1atom% is formed by silane PCVD on a quartz glass substrate 1, and a silicon nitride film 3 is laminated as a gate insulating film by a light CVD thereon. A region 5 for forming IGF is removed to remove it by plasma etching method. An N<+> type semiconductor film 4 is laminated thereon, with a resist 6 as a mask it is removed, with the gate electrode 4 and the resist 6 as masks P is implanted by ion implanting method to form a pair of impurity regions 7, 8. After the resist 6 is removed, annealed with strong light 10, the electrode 4 is polycrystallized, the regions 7, 8 are melted, recrystallized to grow the crystal. Electrodes 13, 13', leads 14, 14' are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an insulated gate field effect semiconductor device (hereinafter referred to as IGF) used in semiconductor integrated circuits, liquid crystal display panels, etc.

``Prior art j IGFs using single-crystal silicon are widely used in the semiconductor field.
-1986r Semiconductor device and method for manufacturing the same.”

However, an IGF in which the channel formation region is formed using a non-single-crystal semiconductor doped with hydrogen or a halogen element at a concentration of 1 atomic % or more, instead of using a single-crystal semiconductor, is proposed in the patent application filed by the present inventor in 1982- 124021r Semiconductor Device and Method for Manufacturing the Same'' (filed on October 7, 1978) is a typical example.

An IGF in which a semiconductor doped with hydrogen or a halogen element, particularly a silicon semiconductor, is used in the channel formation region,
The off-state current is 103 to 105 times smaller than that when a conventionally known single crystal semiconductor is used. Therefore, it is said that it is effective to use it as an IGF for controlling a liquid crystal display panel. As mentioned above, this IGF is a lateral channel type IGF in which a gate electrode is provided above the semiconductor in the channel formation region, and is also referred to in Japanese Patent Application No. 56-001767 r insulated gate type semiconductor device filed by the present inventor. and the so-called generally known thin film IGF transistor in which the gate electrode is provided under the semiconductor constituting the channel forming region. type is known. However, compared to the latter two, the former has the same structure as the previously known IGF using single-crystal silicon, so it has an extremely superior feature of being able to apply already developed technology. .

On the other hand, however, in such IGPs, the source and drain are not formed by thin film deposition using the CVD method (including plasma CVD method), but are added by ion implantation, etc., and the additives are hydrogenated at 400°C or less. Alternatively, the halogen element must be made into an active donor or acceptor by annealing at a temperature range in which it does not degas.

Regarding this point of view, the application of the present inventor mentioned above is not necessarily clear.

Means for Solving the Problem The present invention is intended to solve the above problem, and is a non-single crystal semiconductor (with no or very little added impurities).
A gate insulator and a gate electrode were selectively provided on the non-single-crystal semiconductor to which hydrogen or a halogen element was added (hereinafter simply referred to as a semiconductor or non-single-crystal semiconductor). Furthermore, using this gate electrode as a mask, impurities for the source and drain, such as phosphorus or arsenic for an N-channel type, and boron for a P-channel type, were doped into the inside of the non-single crystal semiconductor by ion implantation or the like. Thereafter, the region to which this inert impurity has been added is irradiated with strong light at a temperature of 400°C or less to perform strong light annealing (hereinafter simply referred to as photoannealing), so that the hydrogen or halogen element remains added and It is characterized by being transformed into a semiconductor whose crystallinity is more enhanced than that of the channel forming region, particularly into a semiconductor having a polycrystalline or single crystal structure.

That is, the present invention does not perform laser annealing after ion implantation on a conventionally known single crystal semiconductor to which no hydrogen or halogen element is added, but instead performs laser annealing after ion implantation. Crystal growth is included in the process by implanting ions into a non-single crystal semiconductor doped at a concentration of This is an impurity region that promotes crystallinity.

"Operation" As a result, in the structure of the IGF of the present invention, the gate electrode is provided above the non-single crystal semiconductor constituting the channel formation region on the substrate, and the optical Eg of this semiconductor (1. 1.6-1.8 eV for 7-1.8 eν)
It was possible to obtain an active impurity region having almost the same optical Eg. Since the throat and <Eg are the same or approximately the same as the channel forming region, the rONJ of IGF
, rOFF J. On the other hand, the on-current does not flow slowly when it rises, and on the other hand, the current does not flow lazily when it falls; the so-called off-current is small, and it can turn on and off with a high-speed response. Ta.

The present invention will be explained below with reference to Examples.

"Example 1" As shown in FIG. 1(A), the substrate (1) has a thickness of 1.
A 1 mm quartz glass substrate measuring 10 cm x 10 cm was used. On this upper surface, a plasma CV of silane (Silly) is applied.
D (High frequency 13.56MHz, substrate temperature 210℃)
A non-single crystal semiconductor (2) including an amorphous structure doped with hydrogen at a concentration of 1 atomic % or more was formed to have a thickness of 0.2 μm.

Furthermore, a silicon nitride film (3) was laminated as a gate insulating film on this upper surface by a photo-CVD method. That is, 5iJ4 was fabricated to a thickness of 1000 nm without using a mercury sensitization method by reaction of Si2H6 with ammonia or hydrazine (low pressure mercury lamp containing 2537 nm wavelength, substrate temperature 250° C.).

Thereafter, the remaining portions except for the region (5) where TGII is to be formed were removed by plasma etching. The reaction is CF.

The test was carried out at 13.56 MHz and room temperature with 10□ (5χ). On this gate insulating film, a microcrystalline or polycrystalline semiconductor of N+ conductivity type was laminated to a thickness of 0.3 μm. After removing this N+ semiconductor film by photoetching using a resist (6), using this resist and the gate electrode part (4) of the N'' semiconductor as a mask, the regions that will become the source and drain are implanted by ion implantation. Phosphorus was added to the concentration of IXIO''c+n-3 as shown in FIG. 1(B) to form a pair of impurity regions (7) and (8).

Furthermore, after removing the resist of the gate electrode, the entire substrate was subjected to photo-annealing using strong light (10). That is,
Ultra-high pressure mercury lamp (output 5KW, wavelength 250-600nm,
A parabolic reflector is used on the back side, and a quartz cylindrical lens (
Focal length 150cm, 2mm in the condensing part, length 180mm
), the irradiation area was constructed in a linear manner. The irradiation surface of the substrate was scanned with respect to this irradiation section at a speed of 5 to 50 cm/min, so that the entire surface of the substrate (10 cm x 10 cm) was irradiated with intense light.

In this way, since a large amount of phosphorus is added to the gate electrode side of the gate electrode portion, this electrode sufficiently absorbs light and becomes polycrystalline. Further, the impurity regions (7) and (8) were once melted and recrystallized, thereby causing the melting and recrystallization to shift (move) in the scanning direction, that is, the X direction. As a result, compared to simply uniformly heating or irradiating the entire surface with light, it was possible to increase the crystal grain size because a growth mechanism was added.

The region polycrystallized by this intense light annealing does not necessarily need to extend to the entire region below the impurity region. As shown by the broken line (11) (11 (11°)) in the drawing,
It is important that at least only the upper part crystallizes and the impurities become active. Furthermore, the end (15) (15
) are provided over the channel side with respect to the ends (16) and (16') of the gate electrodes, and N (7),
(8)-1(2) The junction interfaces (17) and (17') are provided inside the crystallized region, and the channel formation region is provided in a hybrid structure using a non-single crystal semiconductor of the ■-type semiconductor and a crystallized semiconductor. . The extent of the crystallized semiconductor region within this ■-type semiconductor can be determined by the scanning speed and intensity (illuminance) of optical annealing.

In the drawing, after the step in FIG. 1(B), PI [
1 to a thickness of 2μ over the entire surface, and then an electrode hole (13
) (13'), then aluminum ohmic contacts and their leads (14), (14')
is formed. When forming the second layers (14) and (14'), they may be connected to the gate electrode (4).

As a result of this light annealing, the sheet resistance is 4X1 compared to that before light irradiation.
0-3 (0cm>-'I XIO" (0cm) -
This could be revealed by the change in electrical conductivity characteristics after light irradiation annealing compared to '.

When the length of the channel forming region is 3 μ and 10 μ, the length in the channel is 1 mm, as shown in Fig. 2 (
21), As shown in (22), ■I-+2V
, V oo = 10V n I Xl0-5A, 2
Xl0-'II (7) current could be obtained.

Note that the off-state current is (VGG = OV) 10-” ~
10-'' (A), which was also smaller by 1 of 10-4 compared to 1048 of a single crystal semiconductor.

``Effect J'' Because the present invention adopts a manufacturing process in which a film is gradually formed and processed from the bottom, it has become possible to perform large-scale integration over a large area.
It was possible to fabricate 500 x 500 IGFs in a 0 cm panel, and it could be applied as an IGF for controlling a liquid crystal display element (9).

Since the photo-annealing process was performed at a low temperature of 400° C. or lower, it was possible to prevent the polycrystalline or single-crystalline semiconductor from releasing hydrogen or halogen elements therein.

Furthermore, instead of performing optical annealing on the entire surface of the substrate at the same time, it was scanned from one end to the other. For this purpose, a cylindrical ultra-high pressure mercury lamp is focused using a parabolic mirror and a quartz lens to form linear light, and the surface is optically annealed by scanning the substrate in a direction perpendicular to this light. was completed.

Since the subsequent annealing was performed using ultraviolet light, crystallization from the surface of the semiconductor toward the inside was promoted. Therefore, it has become possible to control the current flowing in the vicinity of the gate insulating film in the channel forming region to the sufficiently polycrystalline or single crystallized impurity region near the surface without any trouble.

No single crystal semiconductor is used as the substrate. Therefore, during the light irradiation annealing step, the hydrogen or halogen element (10) added to the channel forming region is not affected at all and can maintain the state of a non-single crystal semiconductor. Therefore, the off-state current is 1/1 that of a single crystal semiconductor.
It can be set to 0' to 1/105.

Since the source and drain are fabricated by photo-annealing after forming the gate, there is no dirt attached to the gate insulator interface, and the characteristics are stable.

Furthermore, compared to conventionally known methods, not only quartz glass but also any arbitrary substrate such as soda glass or heat-resistant organic film can be used as the substrate material.

The process of forming the semiconductor-gate insulator-gate electrode that constitutes the channel formation region, which is the interface between different materials, can be performed in the same reactor without exposing it to the atmosphere, so it has the advantage that fewer interface units occur. have

In the present invention, all of oxygen, carbon and nitrogen in the non-single crystal semiconductor in the channel forming region are 5XIO"c
The impurity concentration is preferably m-3 or less. That is, in the conventionally known IGP, these are 1 to 3 in the channel layer.
X 10"cn+-' concentration11) When using an amorphous silicon semiconductor, the lifetime of carriers, especially holes, is shortened, and the characteristics are 1/3 or less of the characteristics possessed by the present invention. In addition, a hysteresis characteristic was observed when adding a drain electric field of 2X106V/cm or more to the IDD vcc characteristic.On the other hand, when oxygen was
When set to -3 or less, no hysteresis was observed even at a voltage of 3XIO6V/cm.

[Brief explanation of the drawing]

FIG. 1 shows a longitudinal sectional view of the manufacturing process of an insulated gate field effect semiconductor device of the present invention. FIG. 2 shows the drain current-gate voltage characteristics. Patent applicant (12)

Claims (1)

[Claims] (1) The channel forming region of the insulated gate field effect transistor is made of a non-single crystal semiconductor doped with hydrogen or a halogen element, and a pair of impurity regions constituting the source and drain adjacent to the semiconductor are An insulated gate type semiconductor device characterized in that crystallization is promoted compared to the semiconductor of the channel forming region. 2. The insulated gate semiconductor device according to claim 1, wherein the pair of impurity regions is made of a polycrystalline semiconductor doped with hydrogen or a halogen element at a concentration of 1 atomic % or more.