JPS6024024A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6024024A JPS6024024A JP13107183A JP13107183A JPS6024024A JP S6024024 A JPS6024024 A JP S6024024A JP 13107183 A JP13107183 A JP 13107183A JP 13107183 A JP13107183 A JP 13107183A JP S6024024 A JPS6024024 A JP S6024024A
- Authority
- JP
- Japan
- Prior art keywords
- domain
- type
- gold
- heavy metal
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052737 gold Inorganic materials 0.000 claims abstract description 16
- 239000010931 gold Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000007787 solid Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 1
- 238000001556 precipitation Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分Ｗ１′〕
本発明はＭ金机が導入された領域を備えた半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Portion W1' of the Invention] The present invention relates to a semiconductor device including a region in which an M metal plate is introduced.
従来ダイオードやトランジスタ等のスイッチング速度を
速くするために金や白金等の重金属を所定領域に導入す
るという技術がよく用いられている。第１図を用いて重
金属をダイオードのアノードに導入した半導体装置を説
明する。Ｎ型の半導体基板１にＰ型領域２を形成する。Conventionally, in order to increase the switching speed of diodes, transistors, etc., a technique of introducing heavy metals such as gold or platinum into a predetermined region is often used. A semiconductor device in which heavy metals are introduced into the anode of a diode will be described with reference to FIG. A P type region 2 is formed in an N type semiconductor substrate 1.
半導体基板１゜Ｐ型領域２はそれぞれダイオードのカソ
ード、アノードとなる。半導体基板１の表面に酸化膜３
を形成した後Ｐ型領域２上の所定部分の酸化膜３を除去
する。重金属膜４を蒸着等の手段にょシ被着し、例えば
９００ ’Ｏの界囲気中にて１時間１１ど重金属属膜４
よりＰ型領域２へ重金属を拡散させる。The semiconductor substrate 1.degree. P-type region 2 becomes a cathode and an anode of a diode, respectively. Oxide film 3 on the surface of semiconductor substrate 1
After forming oxide film 3, a predetermined portion of oxide film 3 on P-type region 2 is removed. The heavy metal film 4 is deposited by means such as vapor deposition, for example, in an ambient atmosphere of 900'O for 1 hour.
The heavy metal is further diffused into the P-type region 2.
その後重金属膜４５Ｃ除去し、所定領域に電極を形成す
る。こうしてＰ型領域２内に重金属領域を形成すること
によシ、このダイオードの逆回復時間を小さくすること
ができる。Thereafter, the heavy metal film 45C is removed and electrodes are formed in predetermined areas. By thus forming a heavy metal region within the P-type region 2, the reverse recovery time of this diode can be reduced.
しかしこのようにして重金属領域を形成すると半導体基
板１表面に関して、垂直方向と同様に水永方向にも重金
属が拡散されてしまう。一方表面午
付近のＰ−Ｎ接合近傍に偏析した重金属はダイオードの
逆バイアス時のリーク′亀流を著しく増加させる場合が
ある。従って必要な垂直方向への拡散長と想定される水
平方向への拡散長とを十分考慮し、余裕を見込んだ設計
を行わなければならない。However, if the heavy metal region is formed in this way, the heavy metal will be diffused in the horizontal direction as well as in the vertical direction with respect to the surface of the semiconductor substrate 1. On the other hand, heavy metals segregated in the vicinity of the PN junction near the surface may significantly increase the leakage current when the diode is reverse biased. Therefore, the necessary vertical diffusion length and the expected horizontal diffusion length must be fully considered and a margin must be taken into account when designing.
また半；ｊｆｉ体呆枯回路装置においてその中の一つの
素子（のみｊ１１金鵬を拡散する場合には、その周辺の
素子への拡散を防ぐためその素子間距離を充分にとるこ
とが必要となり、半導体集積回路装置の高集積度化に支
障が生じる。In addition, in a semi-JFI circuit device, when diffusing the metal in only one element (J11), it is necessary to maintain a sufficient distance between the elements to prevent diffusion to the surrounding elements. This poses a problem in increasing the degree of integration of semiconductor integrated circuit devices.
本発明は上記の事情を、考慮してなされたもので、重金
属領域が所定領域に精度よく形成された半導体装１征を
提供することを目的とする。The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device in which heavy metal regions are precisely formed in predetermined regions.
５ｊ金属狽域を形成ずべきＰ属領域の周辺部にＮ型ｉＩ
目域をル、成し、仄に重金属の導入を行ってＰ型ｊ、ｕ
域内にｉｉ（金部領域を形成する。重金属の拡散速度は
Ｐ型憧域中よりもＮ型領域中の方が遅い。これはＮ型領
域中の重金属の固溶度がＰ型頭域中のそれよりも大きい
ためと考えられる。従って重金属はＮ型領域に達すると
拡散速度が遅くなり、Ｎ型領域を越えて拡散されること
がなく、所望の領域に重金属領域を形成することができ
る。5j N type iI in the periphery of the P region where the metal trap region should be formed.
P type j, u is formed by introducing heavy metals.
The diffusion rate of heavy metals is slower in the N-type region than in the P-type region. This is because the solid solubility of heavy metals in the N-type region is lower than that in the P-type head region. This is thought to be because the heavy metal is larger than that of the N-type region. Therefore, when the heavy metal reaches the N-type region, the diffusion rate slows down, and it is not diffused beyond the N-type region, making it possible to form a heavy metal region in the desired region. .
本発明の 実施例を第２図を用いて説明する。 An embodiment of the present invention will be described using FIG. 2.
Ｎ型の半導体基板１１にＰ型頭域１２を形成し。A P-type head region 12 is formed on an N-type semiconductor substrate 11.
ダイオードを構成する。Ｐ型頭域１２の周辺部にリング
状に不純物としてリンを導入したＮ型領域１５を形成す
る。半導体基板１１の表面に酸化膜１３を形成した後、
Ｎ型領域１５の内側の所定部分の酸化膜１３を除去し、
金膜１４を蒸着により被着する。次に９００℃の雰囲気
中にて１時間金膜１４よりｐ型領域１２中に金を拡散さ
せ金拡散領域を形成する。Configure the diode. An N-type region 15 into which phosphorus is introduced as an impurity is formed in a ring shape around the P-type head region 12 . After forming the oxide film 13 on the surface of the semiconductor substrate 11,
A predetermined portion of the oxide film 13 inside the N-type region 15 is removed,
A gold film 14 is deposited by vapor deposition. Next, gold is diffused from the gold film 14 into the p-type region 12 in an atmosphere of 900° C. for one hour to form a gold diffusion region.
リンが導入された領域にお・ける金の固溶度は非常に大
きい。これはリンと金が化合物を作るだめと思われる。The solid solubility of gold in the region where phosphorus is introduced is very large. This seems to be because phosphorus and gold cannot form a compound.
このため金の水平方向への拡散は防止され、所望の領域
のみへの拡散を行うことができる。そしてＰ型頭域１２
の端部付近に偏析する金の量が少なくなり、ダイオード
に逆バイアスを加えた際のリーク１１工流は大幅に減少
する。例えば３１バイアスとして４００ｖ加えた場合に
は従来１ｏ−３Ａ程度だったリーク電流は５Ｘ１０−５
Ａ程度棟で減少する。Therefore, horizontal diffusion of gold is prevented, and diffusion can be performed only in desired areas. and P type head area 12
The amount of gold segregated near the ends of the diode is reduced, and the leakage current when applying a reverse bias to the diode is significantly reduced. For example, if 400V is applied as a 31 bias, the leakage current, which was conventionally about 1o-3A, will be 5X10-5.
It decreases in A level buildings.
次に第３図を用いて本発明の他の実施例を説明する。第
：３図に示すのはモーターのスイッチングｉｔ’ｌｌ
ｆ１１１用として大′ｔａカトランジスタとダイオード
とを一体化した半導体装置である。まずＮ型の半導体基
板２１に互いに隣接して、Ｍｌ及び第２のＰ型頭域２２
．２３を設け、その中にさらにそれぞれ；イル１及び第
２のＮ型領域２４．２５を設ける。なお第１のＮ型領域
２４は第１のＰ型頭域２２内の第２のＰ型頭域２３１１
ＩＩＩにのみ形成されている。半導体基板２１、第１の
Ｐ型頭域２２がそれぞれダイオードのカソード、アノー
ドとなり、半導体基板２１、第２のＰ要領域２３、第２
のＮ型領域２５がそれぞれトランジスタのコレクタ、ベ
ース、エミツタとなる。次に半導体基板２１の表面に酸
化膜２６を形成し、第１のＰ型頭域２２の所定部分上に
開口部を設け、重金属膜２７を形成する。高温雰囲気中
にて重金属を第１のＰ型頭域２２内へ拡散させる。Next, another embodiment of the present invention will be described using FIG. Figure 3 shows the motor switching it'll
This is a semiconductor device for f111 that integrates a large transistor and a diode. First, an Ml and a second P-type head region 22 are arranged adjacent to each other on an N-type semiconductor substrate 21.
．． 23 are provided, within which are further provided an tile 1 and a second N-type region 24, 25, respectively. Note that the first N-type region 24 is a second P-type head region 2311 within the first P-type head region 22.
It is formed only in III. The semiconductor substrate 21 and the first P-type head region 22 serve as the cathode and anode of the diode, respectively.
The N-type regions 25 become the collector, base, and emitter of the transistor, respectively. Next, an oxide film 26 is formed on the surface of the semiconductor substrate 21, an opening is provided on a predetermined portion of the first P-type head region 22, and a heavy metal film 27 is formed. Heavy metals are diffused into the first P-shaped head region 22 in a high temperature atmosphere.
重金属は第１のＮ型領域２４が設けられているため第２
のＰ要領域２３へ拡散されない。重金属の拡散はさまざ
まな要因により支配されており、重金属の拡散状態はば
らつくことが多いため従来は隣接した素子の特性を調整
するのが困難だったが、本実施例によれば隣接した素子
は重金属の影響を受けることはなく、所望の特性を容易
に得ることができる。また第１のＮ型領域２４と第２の
Ｎ型領域２５とは同時に形成することができるため、工
程数が増大することはない。Since the first N-type region 24 is provided for heavy metals, the second
is not diffused to the P-required area 23. Diffusion of heavy metals is controlled by various factors, and the diffusion state of heavy metals often varies, so conventionally it was difficult to adjust the characteristics of adjacent elements, but according to this example, adjacent elements It is not affected by heavy metals, and desired properties can be easily obtained. Furthermore, since the first N-type region 24 and the second N-type region 25 can be formed simultaneously, the number of steps does not increase.
なお上記の実施例ではダイオードを例にして説明を行っ
たが、その他の半導体装置、例えばトランジスタにも本
発明を適用することができることは言うまでもない。Although the above embodiments have been described using diodes as an example, it goes without saying that the present invention can be applied to other semiconductor devices, such as transistors.
本発明によれば重金属領域を所定領域にＡ′ｎ度よく形
成することができるだめリーク電流の増大を防止するこ
とができ、特性の優れた半導体装置を得ることができる
。According to the present invention, since the heavy metal region can be formed in a predetermined region with a high degree of A'n, an increase in leakage current can be prevented, and a semiconductor device with excellent characteristics can be obtained.
２６１図は従来の■金属を導入した半導体装置を示すＭ
面図、第２図は本発明の一実施例を示す断面図 ｔｉ？
３図は本発明の他の実施例を示す断面図で；０）イ）
。
１１．２１・・・半導体基板、１２．２２・・・Ｐ型領
域、１５．２４・・Ｎ型１・μ域。
代理人 弁理士 則 近 憲 佑
（ほか１名）Figure 261 shows a conventional semiconductor device incorporating metal.
The top view and FIG. 2 are cross-sectional views showing one embodiment of the present invention.
Figure 3 is a sectional view showing another embodiment of the present invention;
. 11.21...Semiconductor substrate, 12.22...P type region, 15.24...N type 1.mu. region. Agent: Patent attorney Kensuke Chika (and 1 other person)
Claims (1)
頭域内に形成された重金属領域と、前記Ｐ型頭域内の周
辺部に形成され前記重金属の拡散を阻止するだめのＮ型
毎叢域とを具備する半導体装置。 （２１ｆｉｉＪ記Ｎ型記載型領域グ状に形成されている
ことを特徴とする特許請求の範囲第１項記載の半導体装
１？ｔ０ （３）前記重金属は金または白金のいずれかであること
を特徴とする特許請求の範囲第１項記載の半ぺ・Ｌ体装
置ｋ０ （４）前記Ｎ型領域は不純物としてリンが導入されてな
るものであることを特徴とする特許請求の範囲第１項ま
たは・刑３〕貝記載の半導体装置。[Scope of Claims] (A P-type region formed on an 11-half-29 body substrate, a heavy metal region formed within this P-type head region, and a heavy metal region formed in a peripheral portion of the P-type head region to prevent diffusion of the heavy metal. A semiconductor device comprising an N-type region for blocking. (3) The half-L body device k0 according to claim 1, wherein the heavy metal is either gold or platinum. (4) The N-type region is doped with phosphorus as an impurity. A semiconductor device according to claim 1 or claim 3, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13107183A JPS6024024A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13107183A JPS6024024A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6024024A true JPS6024024A (en) | 1985-02-06 |
Family
ID=15049312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13107183A Pending JPS6024024A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024024A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63291477A (en) * | 1987-05-23 | 1988-11-29 | Nippon Inter Electronics Corp | High speed rectifier element and manufacture thereof |
-
1983
- 1983-07-20 JP JP13107183A patent/JPS6024024A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63291477A (en) * | 1987-05-23 | 1988-11-29 | Nippon Inter Electronics Corp | High speed rectifier element and manufacture thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3909320A (en) | Method for forming MOS structure using double diffusion | |
| CA1082373A (en) | Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps | |
| US4441932A (en) | Process for preparing semiconductor device having active base region implanted therein using walled emitter opening and the edge of dielectric isolation zone | |
| JPH04127480A (en) | High breakdown strength low resistance semiconductor device | |
| US3338758A (en) | Surface gradient protected high breakdown junctions | |
| US3945857A (en) | Method for fabricating double-diffused, lateral transistors | |
| US4412238A (en) | Simplified BIFET structure | |
| EP0476571A2 (en) | Semiconductor device with vertical bipolar transistors | |
| US4035907A (en) | Integrated circuit having guard ring Schottky barrier diode and method | |
| US5841181A (en) | Semiconductor apparatus having field limiting rings | |
| US4512815A (en) | Simplified BIFET process | |
| EP0600596B1 (en) | Improved bipolar transistor | |
| US3825451A (en) | Method for fabricating polycrystalline structures for integrated circuits | |
| JPS6024024A (en) | Semiconductor device | |
| US5179030A (en) | Method of fabricating a buried zener diode simultaneously with other semiconductor devices | |
| JPH03201564A (en) | Lateral semiconductor device | |
| JPH07105485B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS5821866A (en) | Semiconductor device | |
| JPH02262372A (en) | Semiconductor device and manufacture thereof | |
| JPH0691097B2 (en) | Method for manufacturing semiconductor device | |
| JPS59104166A (en) | Control of injecting substrate in lateral bipolar transistor | |
| JPH01268169A (en) | Bipolar transistor | |
| JPS5910270A (en) | Semiconductor integrated circuit device | |
| JPS62298170A (en) | Manufacture of semiconductor device | |
| JPH05335329A (en) | Semiconductor device and its manufacture |