JPS60236210A - Junction of semiconductor wafers - Google Patents
Junction of semiconductor wafersInfo
- Publication number
- JPS60236210A JPS60236210A JP9318284A JP9318284A JPS60236210A JP S60236210 A JPS60236210 A JP S60236210A JP 9318284 A JP9318284 A JP 9318284A JP 9318284 A JP9318284 A JP 9318284A JP S60236210 A JPS60236210 A JP S60236210A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafers
- junction
- temperature
- reduced pressure
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、シリコンなどの半導体ウニノ・の接合方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for bonding semiconductors such as silicon.
半導体ウェーの面上に、同糧のまたは組成や不純物濃度
の異なる他の半導体層を形成する技術は、種々知られて
いる。例えば、化学蒸着法や物理蒸着法を応用した気相
成長法、液相エピタキシャル成長法、合金接合法、半田
などの接着層を利用した接着法、などである。しかしな
がら、従来の各種蒸着法では堆積速度が遅く、例えば数
100μmといった半導体層を形成しようとすると極め
て長い時間を要するという問題がある。また異種材料の
接着層で半導体ウェー・を接合する方法では、昇温する
と接着層材料が半導体中に拡散したし、化合物を生成し
たシして変質をおこすという不都合がある。更にまた、
半導体ウェハ同志を真空中で加熱加圧する、いわゆるホ
ウトゲレス法があるが、この方法では特殊装置を必要と
し、しかも融点に近い1300℃程度の高温を要するた
めクリーブなどの変形を生じる、という問題がある。Various techniques are known for forming other semiconductor layers of the same type or of different compositions and impurity concentrations on the surface of a semiconductor wafer. Examples include a vapor phase growth method applying a chemical vapor deposition method or a physical vapor deposition method, a liquid phase epitaxial growth method, an alloy bonding method, and an adhesion method using an adhesive layer such as solder. However, various conventional vapor deposition methods have a problem in that the deposition rate is slow and it takes an extremely long time to form a semiconductor layer of, for example, several hundred micrometers. Furthermore, in the method of bonding semiconductor wafers using an adhesive layer of different materials, there is a disadvantage that when the temperature rises, the adhesive layer material diffuses into the semiconductor, and compounds are generated, causing deterioration. Furthermore,
There is a so-called Houtgeres method in which semiconductor wafers are heated and pressurized together in a vacuum, but this method requires special equipment and also requires high temperatures of around 1300°C, which is close to the melting point, resulting in deformation such as cleavage. .
一方本発明者らは、鏡面研磨した半導体ウェハの研磨面
同志を清浄な雰囲気下で圧接することによシ極めて強固
に接合することを見出し、これを先に提案している(%
願昭58−159276号)。この方法によれば、事実
上異物の介在なしに簡単に半導体ウェー・の接合体が得
られる。On the other hand, the present inventors have discovered that by pressing the polished surfaces of mirror-polished semiconductor wafers together in a clean atmosphere, they can be bonded extremely firmly, and have previously proposed this (%
(Gan Sho 58-159276). According to this method, a bonded body of semiconductor wafers can be easily obtained with virtually no intervening foreign matter.
ところが、数インチという大きい径の半導体クエ・・の
接合にこの方法を用いた場合、ウニ・・の互いの影響で
全面接着が非常に難しいことがわかった。これは、接着
面の一部に残留ガスが介在することが主な要因と考えら
れる。However, when this method was used to bond semiconductor cubes with a diameter of several inches, it was found that it was extremely difficult to bond the entire surface due to the mutual influence of the sea urchins. This is considered to be mainly due to the presence of residual gas in a part of the adhesive surface.
本発明は、大面積の半導体ウェー・同志であってもこれ
を簡単かつ強固に接合することができる半導体ウェー・
の接合方法を提供することを目的とする。The present invention provides a semiconductor wafer that can easily and firmly bond even large-area semiconductor wafers together.
The purpose of this invention is to provide a method for joining.
本発明は、2枚の半導体ウニ・・の表面を鏡面研磨し、
その研磨面同志を減圧下で密着させ、次いで大気圧中に
戻して1300℃を越えない温度で熱処理することKよ
り、ウェー接合体を得る。The present invention mirror-polishes the surfaces of two semiconductor sea urchins,
The polished surfaces are brought into close contact with each other under reduced pressure, and then returned to atmospheric pressure and heat treated at a temperature not exceeding 1300° C. to obtain a wafer bonded body.
研磨面の表面粗さは500X以下とすることが好ましく
、また研磨面は十分洗浄した後、乾燥させてから減圧チ
ャン・寸内で密着させる。減圧チャンバ内圧力は10
rn Torr以下であれば、事実上空気などの残留ガ
スを無視できるので良好な密着が可能となる。The surface roughness of the polished surface is preferably 500X or less, and after the polished surface has been thoroughly cleaned and dried, it is brought into close contact in a vacuum chamber. The pressure inside the vacuum chamber is 10
If it is below rn Torr, residual gas such as air can be virtually ignored, and good adhesion is possible.
大気圧中での熱処理は、200℃以上であればウニ・・
の接合強度増大に効果が認められる。Heat treatment at atmospheric pressure can be applied to sea urchins at temperatures above 200°C.
The effect of increasing the bonding strength is recognized.
特に電気的特性を良好なものとするためには、i oo
o℃程度の熱処理が好凍し5い。1300℃程度以上に
昇温すると、従来のホットルス法におけると同様、クリ
ープなどのウェー・変形をもたらす。In particular, in order to improve the electrical characteristics, i oo
Heat treatment at around 0°C makes it a good freeze. When the temperature is increased to about 1300° C. or higher, wafer deformation such as creep occurs, as in the conventional Hotrus method.
なお本発明の方法は、デミなどの異物が接着面に介在す
れば良好な接合体を得ることはできない。従ってウェハ
の洗浄から密着までの工程では雰囲気の清浄性が重要で
ある。Note that the method of the present invention cannot obtain a good bonded body if foreign matter such as demi is present on the adhesive surface. Therefore, the cleanliness of the atmosphere is important in the process from wafer cleaning to adhesion.
本発明によれば、半導体ウェー・を減圧下で密着させる
ため、広い面積の半導体ウニ・・であっても接着面に残
留ガスがとシ残されることがなく、強固に接合すること
ができる。According to the present invention, since the semiconductor wafers are closely attached under reduced pressure, even if the semiconductor wafer has a large area, no residual gas is left on the bonding surface, and it is possible to firmly bond the semiconductor wafers.
本発明によシ得られる半導体ウニ・・接合体は、各種半
導体デバイスに広く応用できる。例えば、高不純物濃度
半導体ウェー・と低不純物濃度半導体を接合させること
により、従来メサ型トランソスタで必要であった深い、
かつ高濃度のコレクタ形成用拡散工程を省略することが
できる。The semiconductor urchin bonded body obtained by the present invention can be widely applied to various semiconductor devices. For example, by bonding a high impurity concentration semiconductor wafer with a low impurity concentration semiconductor, it is possible to
Moreover, a high-concentration collector-forming diffusion process can be omitted.
これによって、工程短縮や欠陥の導入防止などの大きな
効果が期待できる。またIC基板として従来エピタキシ
ャル成長によシ形成していた高抵抗活性層を本発明の方
法で実現すれば、やはり大幅なIC製造工程短縮が図れ
、高耐圧素子などの素子特性の改善にも寄与する。This can be expected to have significant effects such as shortening the process and preventing the introduction of defects. Furthermore, if a high-resistance active layer, which was conventionally formed by epitaxial growth, is realized as an IC substrate by the method of the present invention, the IC manufacturing process can be significantly shortened, and it will also contribute to improving the characteristics of devices such as high-voltage devices. .
固有抵抗0.050−備の3インチn型シリコンウニ・
・を2枚用意し、その表面を鏡面研J拮した。3-inch n-type silicon sea urchin with specific resistance of 0.050-
・I prepared two sheets and polished their surfaces to a mirror finish.
研磨面の表面粗さは100X以]、平面度は10μm8
度であった。これらのウェー・を、コ゛ミ源遊量20個
/−以下のクリーンルーム中で混酸を用いて洗浄した後
、乾燥させ、0.1 Torrの減圧チャンバに入t’
tて研磨面同志を密着させた。The surface roughness of the polished surface is 100X or more], the flatness is 10 μm8
It was degree. These wafers were cleaned using mixed acid in a clean room with a flow rate of 20 particles/- or less, dried, and placed in a vacuum chamber at 0.1 Torr.
The polished surfaces were brought into close contact.
次いでこのシリコンウエー・」−合体を大気中に戻し、
1150℃で2 n、y間熱処理した。This silicone wafer is then returned to the atmosphere,
Heat treatment was performed at 1150° C. for 2 n, y.
(()られたウェー・接合体を、フッ酸系エツチング液
により3咽口のメサ型にエツチング成型して接合面の端
面を露出させた。そし又このウニ・・接合体に金−アン
チモン電極を形成し、接合端面を清浄に保ったまま接合
部の導通特性を検査した。その結果ウェー・全域にわた
って良好なオーミック特性をカクシ、抵抗値も誤差範囲
内でウニ・・そのものの値に一致した。(()) The wafer bonded body was etched into a mesa shape with three orifices using a hydrofluoric acid-based etching solution to expose the end face of the bonded surface. The conductivity characteristics of the joint were inspected while keeping the joint end surface clean.The results showed that the ohmic characteristics were good over the entire wafer area, and the resistance value matched the value of the sea urchin itself within the error range. .
また赤外顕微鏡で観察した結果、接合面に気泡などの存
在が認められなかった。Further, as a result of observation using an infrared microscope, no air bubbles or the like were observed on the bonding surface.
Claims (1)
同志を減圧下で密着させ、次いで大気圧中で1300℃
を越えない温度で熱処理することを特徴とする半導体ウ
ェー・の接合方法。The surfaces of two semiconductor wafers are mirror-polished, the polished surfaces are brought into close contact under reduced pressure, and then heated at 1300°C under atmospheric pressure.
A method for joining semiconductor wafers characterized by heat treatment at a temperature not exceeding .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59093182A JPH0691006B2 (en) | 1984-05-10 | 1984-05-10 | Method for joining semiconductor wafers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59093182A JPH0691006B2 (en) | 1984-05-10 | 1984-05-10 | Method for joining semiconductor wafers |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60236210A true JPS60236210A (en) | 1985-11-25 |
JPH0691006B2 JPH0691006B2 (en) | 1994-11-14 |
Family
ID=14075431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59093182A Expired - Lifetime JPH0691006B2 (en) | 1984-05-10 | 1984-05-10 | Method for joining semiconductor wafers |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0691006B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62282933A (en) * | 1986-06-02 | 1987-12-08 | 日本電信電話株式会社 | Manufacture of precision part |
JPH01238113A (en) * | 1988-03-18 | 1989-09-22 | Nec Corp | Manufacture of semiconductor substrate |
US5129827A (en) * | 1989-08-28 | 1992-07-14 | Kabushiki Kaisha Toshiba | Method for bonding semiconductor substrates |
US5273553A (en) * | 1989-08-28 | 1993-12-28 | Kabushiki Kaisha Toshiba | Apparatus for bonding semiconductor substrates |
US5451547A (en) * | 1991-08-26 | 1995-09-19 | Nippondenso Co., Ltd. | Method of manufacturing semiconductor substrate |
US5843832A (en) * | 1995-03-01 | 1998-12-01 | Virginia Semiconductor, Inc. | Method of formation of thin bonded ultra-thin wafers |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5613773A (en) * | 1979-07-03 | 1981-02-10 | Licentia Gmbh | Fet and method of manufacturing same |
-
1984
- 1984-05-10 JP JP59093182A patent/JPH0691006B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5613773A (en) * | 1979-07-03 | 1981-02-10 | Licentia Gmbh | Fet and method of manufacturing same |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62282933A (en) * | 1986-06-02 | 1987-12-08 | 日本電信電話株式会社 | Manufacture of precision part |
JPH01238113A (en) * | 1988-03-18 | 1989-09-22 | Nec Corp | Manufacture of semiconductor substrate |
US5129827A (en) * | 1989-08-28 | 1992-07-14 | Kabushiki Kaisha Toshiba | Method for bonding semiconductor substrates |
US5273553A (en) * | 1989-08-28 | 1993-12-28 | Kabushiki Kaisha Toshiba | Apparatus for bonding semiconductor substrates |
US5451547A (en) * | 1991-08-26 | 1995-09-19 | Nippondenso Co., Ltd. | Method of manufacturing semiconductor substrate |
US5843832A (en) * | 1995-03-01 | 1998-12-01 | Virginia Semiconductor, Inc. | Method of formation of thin bonded ultra-thin wafers |
Also Published As
Publication number | Publication date |
---|---|
JPH0691006B2 (en) | 1994-11-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |