JPS60235266A - data search circuit - Google Patents

Abstract

PURPOSE:To shorten the data retrieval time by providing data latch circuits whose number is larger than the number of address busses, and retrieving data from a memory having a capacity larger than the memory capacity which can be accessed directly by address busses. CONSTITUTION:A data latch circuit 25 having bits whose number is larger than the number of bits of an address bus 22 is provided on a data bus 23. A preset counter part 26 which has the same number of bits as the latch circuit 25 and can be preset and is counted up for every read request of a CPU21 is provided on the data bus 23 also. Before retrieval is started, the last address is set to the latch circuit 25, and the start address is set to the preset counter part 26. Thus, the address of a ROM31 is incremented automatically only by issue of a read request signal from the CPU21, and data in addresses are outputted to the data bus, and an end interruption signal is transmitted from a comparator 27 to the CPU2 when data in the last address is read.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data retrieval circuit for a computer system, particularly a microcomputer system. The present invention relates to a circuit suitable for searching.

- [Background of the Invention] In a microcomputer system, there are limits to the area that can be directly accessed by the address bus of a central processing unit (hereinafter abbreviated as CPU).

For example, in the case of an 8-bit CPU, the address bus is generally 1
Since there are six, only 54K bytes of memory space can be directly accessed. Of course, if you use a CPU with 16 or more address buses, for example a 16-bit CPU, you can access directly, but this will result in an expensive system. For this reason, an example of a conventional circuit used when an 8-bit CPU has a memory capacity of 64 bytes or more is shown in FIG. FIG. 1 shows an 8-bit CPU that searches data in a 96-byte read-only memory (hereinafter abbreviated as ROM). In Figure 1, 1 is the CPU
, 2 is the CPU address bus, 3 is the CP tJ data bus, 4 is the address decoder, 5 is the latch circuit, 6 is the decoder, 8.9.10 is the byte ROM in 32, 11.1
2.13 is an AND circuit. The address decoder 4 is
When the data on the address bus reaches the address assigned to the latch circuit 5, the state of the data bus is latched into the latch circuit 4. The decoder 6 is a decoding circuit for validating only one of the ROMs 3 to 10 from the data latched in the latch circuit 5, and the output signal of the decoder 6 and the CP
The read request signal from U is ANDed by AND circuits 11-13, and only one of the ROMs 8-10 is selected. The ROMs 8 to 10 are respectively connected to a data bus and an address bus, and only the ROM selected by the selection signals output from the AND circuits 11 to 13 outputs data to the data bus in accordance with the request of the address bus. .

FIG. 2 shows a flowchart of the process when necessary data is retrieved from 96 bytes in a configuration like the following. In FIG. 2, it is assumed that a specific 1-byte of data starting from byte 96 is retrieved in order from the first address of the memory. First, data is set in the latch circuit 5 in order to designate the ROM to be made valid among the ROMs 8.9 and '10. Next, initial address setting is performed. Next, the address is updated by one (hereinafter referred to as address increment) and data is read from the ROM corresponding to that address.

It is determined whether the read data is the data being searched for, and if it is the data being searched for, it is processed as search data rf and the search ends. However, if it is not search data, RO
It is determined whether switching of M is necessary, and if it is not necessary, the process returns to address increment processing. If it is necessary to switch ROMs, it is determined whether the data search has ended, and if the data search has ended, it is treated as no search data, and if it is not, the first ROM,
Repeat from the li fixed process.

As mentioned above, conventionally, the circuit 11'N shown in FIG.
Since the processing shown in Fig. 2 was performed, data judgment, RO
Two processes, ie, determining whether or not M switching is necessary, and address increment processing are required for each 1-byte search. For this reason, when searching for one piece of data among the big mouse data, the search time becomes long.

In addition, when using many registers in the CPU for data search, before starting the data search, save the contents in the CPU registers immediately before starting the data search, and then After that, it was necessary to restore the saved contents. For this reason, the data search time becomes even longer.

In this embodiment, the ROM capacity is 96 bytes, but when handling a larger ROM capacity, the number of digits that can be processed by the latch circuit 5 and the decoder 6 is increased, and the decoder 6
The number of outputs was increased. For example, when handling 384-byte ROM, add 32-byte ROM for a total of 12
1, the output of the decoder 6 is set to 12, and R in Fig. 1 is used.
Similar to OM8-10, one of the 12 ROMs is logically ANDed from the output signal of the decoder 6 and the read request signal from the CPU.
I was connected to select one.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed data retrieval circuit that reduces data retrieval time in a circuit for retrieving data from a memory with a memory capacity larger than that which can be directly accessed by a CPU address bus in a microcomputer system. .

[Summary of the invention]

In the present invention, there is provided a latch section consisting of at least more latch circuits than the number of address buses, a preset counter section that can be preset with the same number of digits as the latch section and counts up every time a CP TJ read request is made, and a fii of the preset counter. ``ROM accessed by f;
It consists of a comparator that outputs an output when the value of the latch section and the value of the preset counter section match. In this case, if you set the final address in the latch section and the first address in the preset counter section before starting the search, then the
ROM automatically by just issuing a read request signal from the PU
The address is incremented, the data at the address is output to the data bus, and when the designated final address is read, the comparator notifies the CPU that the final address has been searched.

[Embodiments of the invention]

A specific embodiment of the present invention is shown in FIG. In this example, 8
A 384-byte ROM is accessed by a 384-bit CPU.

In FIG. 3, 21 is a CPU, 22 is an address bus,
23 is a data bus, 24 is an address decoder, 25 is 1
19-bit latch circuit consisting of a 9-bit data latch circuit, 26 is a 19-bit preset counter, 27
is a bit comparator, 28 is a decoder, 29.30.31 is each 128 by 1-ROM, 32.33.34.35
is an AND circuit. In FIG. 3, the address decoder 24 outputs the lower 8 bits, middle 8 bits, and upper 3 bits of the 19-bit latch circuit 25 according to the state of the address bus 22.
It outputs a signal for selecting a bit, a signal for selecting the lower 8 bits, middle 8 bits, and lower three bits of the 19-bit preset counter 26, and a signal for selecting the ROM 29, 30, and 31. The 19-bit latch circuit 25 and the 19-bit preset counter 26 are adapted to take in data from the data bus when selected by the selection signal from the address decoder. A N I) circuit 32 outputs the AND of the ROM selection signal from the address decoder and the read request signal from the CPU. This output is 1
It is input to the clock input section of a 9-bit preset counter, and the 19-bit preset counter is incremented every time a ROM read request is made. Decoder 28 decodes the 19-bit preset counter.
The bit is decoded and logically multiplied with the output of the AND circuit 32 to select one of the ROMs 30, 31, and 32. Note that the lower 17 bits of the 19-bit preset counter 26 are directly connected to the address input section of the ROM 29.30.31.

ROM29.30.31 is AND circuit 33.34.3
5 selects a valid one, and 1: outputs the contents of the specified address to the data bus in the lower 17 bits of the 19-bit preset counter. Further, when the value of the 19-bit latch circuit 25 and the value of the 19-bit preset counter become the same, the bit comparator 27 requests an interrupt to the CPU.

FIGS. 4 and 5 show flowcharts of the process when necessary data is searched from 384 bytes using a circuit having a "U" structure. In FIG. 4, it is assumed that a specific 1-byte of data is sequentially searched from among the bytes at 384 from the beginning of the ROM. First, the lower 8 bits, middle 8 bits, and upper 3 bits of the 19-bit latch circuit 25 are sequentially addressed to write data, and the address of the final data in the ROM is set. Next, the lower 8 bits, middle 8 bits, and upper 3 bits of the 19-bit preset counter are sequentially addressed, data is written, and the start address of the ROM is set.

After that, the allocated address of the ROM is designated and data is read. It is determined whether the data is the requested data or not, and if it is not the requested data, the data is read again. At this time, data at the next address can be automatically read in response to a read request from the CPU 21, so there is no need for address update processing. If the read data is the requested data, it is processed as search data exists.

If the requested data does not reach the address specified by the latch circuit 25, an interrupt request will be sent to the CPU, so it will be processed as if there is no search data in the interrupt processing shown in FIG.

In this embodiment, since the configuration and processing are performed as described below, the number of determinations in the data search routine is reduced to one, which is less than the conventional example shown in FIG. Further, address increment processing and ROM switching processing are also unnecessary.

As described above, in the present invention, the processing content in the data search routine is reduced compared to the conventional method, so that the data search time when searching for data in the same memory capacity can be shortened. In the conventional example shown in FIG. 2, the data retrieval routine from address increment processing to determination of the necessity of R0M switching takes about 21 machine cycles; however, in the present invention shown in FIG. Since the match determination is repeated, it only takes about 12 machine cycles. Furthermore, since there is no need for a ROM switching determination section, the present invention can reduce the comparative data search time to 1/2 of that of the prior art.

Furthermore, in the present invention, only the registers for fetching data among the registers of the CPU are used for data retrieval. Therefore, the time for saving and restoring registers can be shortened, and the search time can be further shortened.

In this embodiment, we have described the case of a 384 byte ROM, but if there are fewer than 384 bytes, the number of digits handled by the latch circuit, preset counter, and bit comparator should be reduced, and if there are more than 384 bytes, This can be handled by increasing the number of digits handled.

Although this embodiment has been described with respect to an 8-bit CPU, the present invention can be similarly applied to other classes of CPUs. Further, although only the reading of the memory IJROM has been described, the present invention can be similarly applied to reading and writing of a readable/writable memory.

〔Effect of the invention〕

As described above, according to the present invention, when the CPU has a memory that has a memory capacity that is larger than the memory capacity that can be directly accessed, and when searching for data in the memory, the conventional 1/! You can search for the required data in a short time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional data search circuit, FIG. 2 is a flowchart of processing when the circuit of FIG. 1 is used, and FIG. 3 is a circuit diagram of a data search circuit implementing the present invention. FIG. 4 is a flowchart of processing in the circuit of FIG. 3, and FIG. 5 is a flowchart of interrupt processing in the circuit of FIG. 3. 1.21...CPU, 2.22...Address bus,
3.23...Data bus, 4.24...Address decoder, 25...19-bit latch circuit, 26...
19-bit preset counter, 8.9.10.29.
30.31...ROM0 Agent Patent Attorney Akio Takahashi 1st Figure ¥, 2I! I ¥-3 Figure Y 4 Figure f 5 Closed

Claims (1)

[Claims] A latch section consisting of a number of latch circuits equal to or greater than the number of address buses of the central processing unit, and a latch section having the same number of digits as the number of said latch circuits, which can be preset, and is added every time the central processing unit reads. a counter section, a memory section connected to the counter section and outputting data at an address designated by the output of the counter section to the data bus, and a comparison section that outputs a match signal when the values of the latch section and the counter section match. A data retrieval circuit characterized in that it consists of parts.