JPS60229599A - Video signal encoding/decodig system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention encodes video signals, and more particularly video signals for use in compatible high-definition TV systems and other applications with existing receivers. and a decoding device and method.

BACKGROUND OF THE INVENTION It is well recognized that it is desirable for viewers to have high quality images on TV. Society of Film and Television Engineers (SMPTE)
) convened a research group to study various aspects of high definition TV systems, including systems for home use. SMP
The conclusion drawn by the TE research group is that any new service that provides higher-definition TV than is traditionally broadcast will require, among other things (i.e. - more pixels in the line image, Because it is desirable to provide existing home TV receivers with essentially every image attribute and quality that a receiver is capable of (more lines per frame, and therefore more bandwidth required for transmission), be. (S
MPTE Academic Journal Vol. 89, No. 3, pp. 153-161.

(See March 1980 issue). - As an example, the research group cited when NTSC compatible color services were first introduced. The black-and-white receivers then available to the public effectively reproduced the black-and-white versions of color broadcasts without compromising the receiver's electronic performance or the quality of the reproduction. The SMPTE research group has also found that receivers designed for new (high-definition) services should be able to use existing transmission methods and derive results from them that are no worse than those provided by existing receivers. I cautioned that it must be done.

The report of SMPTE Research Gruzo shall be accepted (1)
3) It shows the difficulty in discerning a means to obtain a compatible system capable of receiving images with existing receivers. To the knowledge of the patent applicant, no such system has yet been developed. Indicating a high-definition TV system that is believed to meet practical requirements for performance and compatibility, and that has parameters of operation that are sufficiently flexible to meet the standards ultimately adopted by the TV industry. This is the object of the present invention.

Another object of the present invention is to provide a technique for encoding or decoding that is useful for transmitting or storing video information in a manner that may require reduced bandwidth channels or reduced storage capacity. be.

Yet another object of the present invention is to provide a technique that utilizes the characteristics of human vision to encode transmitted color TV signals in a new way. For example, a receiver with a decoder with frame memory (but not necessarily full high-resolution capability) is able to recover fully separated color and (14) luminance details.

SUMMARY OF THE INVENTION The present invention is directed to an apparatus and method for encoding and/or decoding video signals for use in existing compatible high definition TV systems or other applications. The present invention takes advantage of certain characteristics of human vision, among other things. In particular, it has been discovered that two different types of neurons are used for vision. One neuron detects low-resolution images, is relatively sensitive to temporal transients, and has a time constant for information formation and decay, approximately 40 to 80 milliseconds. It is believed that The second type of neuron is apparently used to transmit relatively high resolution information from the orbit. Neurons of this type are thought to have a time constant of about 200-350 milliseconds. Also, if you temporarily stimulate the first type of neuron, it will be 150 to 300 mi! Preventing the reception of information from the second type of neuron for J seconds. These characteristics of human visual perception enable the development of image transmission systems in which the transmission bandwidth can be effectively reduced without degrading the image perceived by the viewer. As explained above, rapidly changing information is perceived at low resolution;
It is only necessary to transmit this information with the bandwidth required to transmit a relatively low (eg, conventional TV) resolution image at, for example, 30 frames per second. Since relatively high resolution information is only perceptible in about 115 to 173 seconds, the bandwidth required to send relatively high resolution information can be effectively reduced. That is because a suitably low effective frame update rate is all that is required for its transmission. Still, the fact that the eye takes longer to represent a high-resolution image (e.g. 115 to 1/2 seconds), since the relatively high-resolution image is suppressed after a transient event,
3) is not considered to be able to be detected.

A video transmission system may comprise a frame storage at its transmitting end as well as at its receiving end, so that a certain portion of the video information is transmitted and stored less frequently at the receiver, and then used for generation of the video signal at the receiver. It is generally known that it can be reproduced between The present invention improves such systems by taking full advantage of human visual perception characteristics, and has the advantage of providing alternative forms of video, both high and low definition, if desired. It also has the advantage of making the video conform to existing TV standards.

According to one form of the invention, means are provided for storing an input frame as an array of pixel values (preferably, but not necessarily, digital pixel values), and interrogating the stored array to form at least a sum signal. An encoder is provided that includes means for generating a difference signal. The sum signal represents the sum of pixel values in a certain group of pixels, and the difference signal represents the difference between the sum of some pixel values of the pixels in that group and the sum of the pixel values of other pixels in the same group. represent Sum and difference signals are created for multiple bluefs 0 spanning video frames. The sum signal is generated at a relatively high information update rate (e.g., once per each conventional TV frame), and the difference signal is generated at a relatively low information update rate (e.g., once per three or more TV frames) (17). be done. In the illustrated embodiment of this formation of the invention, a sum signal is generated for each frame of a series of frames, and an individual difference signal is generated for each frame of the series.

The encoded sum signal and encoded difference signal can be converted to analog signals and modulated or otherwise transmitted onto separate carrier waves for transmission. At the receiver, the sum and difference signals can be recovered from the carrier wave and dinotated prior to their decoding. According to a feature of this type of invention, the decoder includes means for storing the sum signal and each difference signal, and means for combining the sum and difference signals to obtain an output pixel value for each pixel of the output video frame. be. The number of pixels in each output video frame of the decoder is in fact the same as the number of pixels in the binary high-definition digitized video frame array, and the pixel values of the pixels in the output video frame correspond to the input video frame array. corresponds to the pixel value of the pixel. In the proposed embodiment, the decoder means (18) for storing the sum and difference signals record the input time at a relatively slow clock speed and record the output time for the combination means at a relatively fast clock speed. Consists of digital memory for recording. The pixels output from the combining means can be converted into an output analog video signal for display.

In the disclosed embodiment of this type of invention, each group of pixels of the stored array covers approximately the same area as an individual pixel of conventional TV resolution pixels as a group. Therefore, the sum signal produced during each frame of a conventional TV could be adapted for use by a conventional TV receiver and would be viewed at the same resolution as existing TVs. For receivers equipped with means for reproducing and decoding the difference signal, improved image resolution (such as twice in each dimension for one of the exemplary embodiments herein) can be achieved. However, it will be appreciated that different image group configurations can be employed to achieve different levels of visual clarity improvement compared to the lower resolution sum signal when taken alone. . The present invention also has the video signal transmitted and stored at the same perceptual resolution as in existing systems, but
It will also be appreciated that there are applications for systems that require less bandwidth due to the lower overall information rate required to transmit high quality information.

In the motion picture or film application of the present invention, the mixing of encoded high and low resolution frames 1 records video information on a relatively smaller portion of film than was previously required to record information with the same effective resolution. It can be used to. In such applications, it would again be desirable to have information available in both relatively low resolution and relatively high resolution formats, as the present invention provides.

In the format of the invention we are dealing with here, prior to storing the frames in dinotal format, electronic processing is performed to obtain low and high spatial frequency representations of the images.

In particular, an apparatus and method for encoding and decoding a video signal is provided, the encoder leading to a representation of low spatial frequency components of an image represented by the video signal.
It includes means responsive to the video signal. Another derivation is a display containing high spatial frequency components of an image represented by a video signal. Means is provided for producing output frames consisting of a representation of low spatial frequency components at a fast screen update rate, such as the standard NTSC frame rate of 30 frames per second.

Also, a slow frame update rate, preferably 3 to 3 per second.
Means are also provided for producing an output frame consisting of a representation of high spatial frequency components over a range of 15 frames. about 5 per second
We believe that the frame rate is adequate to maximize bandwidth savings while maintaining virtually high resolution integrity. The decoder is provided with means for combining the display of low spatial frequency components and the display of high spatial frequency components to obtain a decoded video signal.

In one form of the invention, means are provided (21) for delaying the output frame of the low spatial frequency component representation with respect to the output frame of the high spatial frequency component representation. The fact that rapidly changing low-quality image parts tend to mask the effects on high-resolution parts even when transient phenomena caused by motion occur is due to the mental physics of human vision. It is based on scientific measurements.

By delaying the output frame of the low spatial frequency component display with respect to the output frame of the high spatial frequency component display (which is thought to have a similar effect to accelerating the high spatial frequency component display), the slow presentation of long-term detailed information Masking effects can be used to cover up.

In some embodiments of the invention, the derivation of the representation of low spatial frequency components of the image represented by the video signal involves passing the video signal through a low-pass filter to continuously This is done by forming a weighted sum of corresponding pixels of the three scan lines. However, in this embodiment, the means for deriving a display containing high spatial frequency components of an image represented by a video signal is comprised of two other high frequency signal components per each scan line and a high spatial frequency component between each other scan line. This is carried out by alternately selecting (22) the low frequency and high frequency signal components of the scan lines. In this way, averaging in the vertical direction is achieved while reducing artifacts that result from using an unweighted sum of scan lines. Also, the savings in bandwidth of the signals representing the other high frequency components for each scan line is achieved by not including these signal components in the high resolution channel.

Also, in accordance with a feature of some embodiments, the chrominance and luminance information may not be sufficiently separated by conventional color TV processing.
．． Improvements have been shown to encode and process the portion of the standard-definition video spectrum that exceeds 5 Ml (z.
R-Y, B-Y, and Y signals above z (red-yellow, blue-
This information is typically repeated for two successive frames with phase-inverted color carriers. At the receiver, frame storage is used to add or subtract these same two frames. The sum gives a Y signal of 2.5 WfHy or more even without a color signal.

(The color signal is assumed to be the same in these two frames, but the carrier waves are out of phase.) The difference between the two frames gives the color without color mixing. Since the brightness is the same for the two frames, the difference is zero in this frequency range. With this adjustment, the frame rate for color and brightness above 25MH3 is half the conventional frame rate, or 5 frames per second. However, according to the applicant's psychophysical research, this is sufficient.

The system of this embodiment is compatible with standard receivers;
``Augmentation'' (i.e., beyond the standard
It will be appreciated that it is also compatible with receivers that are not fully high resolution.

In either case, slow frame rates for color information as well as detail luminance information do not result in any noticeable degradation in perceived image quality due to the previously described characteristics of human vision. However, in an "enhanced" receiver, improved color and detail separation would be a distinct advantage. This advantage exists even in the most capable high resolution receivers, which include even higher resolution luminance and chroma component signals.

Embodiment Referring to FIG. 1, a block diagram of a high definition TV system according to a first embodiment of the present invention is shown. High resolution TV camera 10, assumed to be a black and white camera for ease of explanation, generates a TV video signal that is coupled to encoding circuit 20. The encoding circuit, according to the principles to be explained, digitalizes the video frame into an array of pixels and generates an "intensity" signal, i.e., a sum signal I, and an x, y, z
and three difference signals represented by a difference signal of . ■ The signal contains information in a frequency bandwidth that is virtually equivalent to the luminance bandwidth of a conventional TV. The encoding circuit also generates multiple auxiliary signals called ``difference signals''. This difference signal, when taken in conjunction with the sum signal, can later be used to obtain the virtually high-resolution information contained in the dinotalized frame of the original video. The sum signal and the multi(25) difference signal are converted to analog form and sent to the transmitter circuit 30.
is combined with The transmitting circuit 30 may include means for modulating a carrier wave with the sum signal and the difference signal and transmitting the modulated symbols.

On the receiver side, a receiving circuit 40 reproduces the sum signal and the difference signal, and these signals are sequentially coupled to a decoding circuit 50. The decoding circuit 50 dinotals the sum signal and the difference signal, and combines them to give a pixel value for each pixel of the output video frame that is equivalent to the pixel value of the corresponding pixel of the original high-resolution frame dinotalized by encoding. get.

The high resolution digital video signal is converted to analog format and displayed on the display device 60. A feature of the present invention is that the sum signal I is compatible with conventional broadcast TV, and can be used even in home-use television receivers that are not equipped with the decoder circuit necessary to obtain high-resolution images.

FIG. 2 is helpful in understanding how sum (or intensity) and difference signals can be generated for an array of pixels. In FIG. 2, pixels are represented by small dots, l-26), and in this example there are 1152 pixels on one scan line, and 964 visible scan lines in one frame. The pixels in FIG. 2 can be considered "high resolution" pixels, with approximately twice as many horizontal and vertical pixels per frame compared to conventional broadcast TV. The pixels in this embodiment are divided into groups of four pixels each as shown. Therefore, in the horizontal direction, the groups range from group 1 to group f57.
6i, and for group 0 scan lines, group scan lines 1 to 482 can be numbered. Therefore, the number of pixel groups approximately corresponds to the number of resolution pixels in conventional broadcast TV. In this embodiment, the sum signal or intensity signal I consists of four pixels of each group, and this sum signal (if properly scaled) is the average intensity (or brightness) level. The pixels of group n are in adjacent pairs of scan lines, labeled scan lines A and B.
, A XB , and Bln, on +n
on, the intensity or sum signal I is expressed as follows, as shown in FIG.

In+Aon10A, n0Bon0B1n (1) The difference signal of this embodiment is X. , Yn and Z. By subtracting the column sum, row sum, and diagonal sum, the difference signal is as follows.

Xo=(Aoo×B.n)-(A1n+81n)-AO
n-Ain 10BOn Jn (2) Yn-(Aon10A1n)-(Bon10B1o)-A. o1A1n-Bo
o-B,. (3) Zn-(AOn+B1n) (AIn
10BOn)-A. n-Aln-Boo+B1o (4) Of course, the sign can also be inverted for all difference signals. The independent equations (1) to (4) are A on
+ B on + A 1n When solving for + and Bln, the following solution is obtained.

The relationships from equations (5) to (8) are used in the decoding circuit on the receiver side in order to reproduce the pixel values originally stored in the encoder.

In the presently described embodiment of the invention, a "low resolution" intensity signal I (hereinafter to be understood as effectively conventional broadcast TV resolution) is produced at a conventional TV video frame rate and a difference signal The perfect complement of is generated at 1/3 of the conventional TV video frame rate. However, it will be appreciated that a variety of speeds may be employed, as will be explained in more detail below. In this embodiment N, the difference signals X, Y, and (
29) and Z are formed in sequence, and one frame of a single difference signal is formed during a conventional TV video frame period.

With respect to FIG. 3, the encoding circuit 20 of the first embodiment
A simplified block diagram of is shown. Camera 10 (Figure 1
) is coupled to an analog/diphthalmic (A, /I') converter 2]0 which operates in a conventional manner to convert the TV-multiplied signal into dinotal format. In this embodiment, each video pixel of a frame is represented by an 8-bit binary signal determined by the instantaneous brightness level of the video signal at a particular pixel location. The Aρ converter 210 operates to digitize each pixel at the encoder clock speed and couple the 8-bit pixel value to the encoder storage subsystem 300. For details, refer to FIGS. 4 and 5. In particular, the output of A/D converter 210 is coupled to the input of a 24-stage serial-in parallel-out buffer register 3100, which is also clocked at the encoder clock speed. The buffer register 310 is
, 4) act to receive 24 8-bit pixel values from the converter (30) and, when full, the contents of the buffer child register are strobed into the input hoard of random access memory (RAM) 320. In this embodiment, the memory 320 stores one of the high-resolution videos.
8-bit pixels for one frame are stored. Memory 320 has a set of output ports labeled A port and B port. The A port is used to output the pixel value of the odd numbered scan line, and the B port is used to output the pixel value of the adjacent even numbered scan line. In this way, the pixels of the group of FIG. 2 are conveniently accessed to produce the desired sum and difference signals. For high-speed processing, and as will be explained further below, the sum and difference signals are generated using a sum and difference signal generation digital circuit 600 that simultaneously processes the pixel values from the AytE'-) and B ports. It is formed.

[Independent pair of 2 marked A/port, B' port
- can be used to form a difference signal, as described above. ] The output of the circuit 600 is connected to a D/A converter 301, which converts the sum and difference signals into analog signals that are connected to the transmitting circuit 30 (FIG. 1).

FIG. 4 illustrates the encoder storage subsystem 3000A force control and addressing method. As previously mentioned, the pixels are clocked into the Guffaleno Star 310 at the input clock rate of the encoder. Modulo 24 pixel counter 3
30 is arranged to count clock pulses and generate one output when the input buffer register 310 is loaded with the latest 24 8-pit pixel values. The output of counter 330 is applied to strobe 24 pixel values into memory 320 via the input port. The output of counter 330 is connected to a modulo 48 counter 340, and this counter 340
It keeps track of the number of 24 pixel sequences it reads per scan line. Therefore, the sequence counter 340
The count is a [sequence address], a number from 0 to 47, that specifies the part of the address at which the most recent 24-pixel sequence is to be stored in memory. The output of sequence counter 340 is therefore also converted into a modulo 964 scan line counter that steps at the end of each scan line, thereby producing a portion of the address specifying the scan line of pixels being read. connected. It will be appreciated that in this manner, a composite address is created for each sequence of 24 high resolution pixels so that the entire frame's high resolution pixels can be stored in an easily retrievable location in memory 320. think.

FIG. 5 illustrates the output control and addressing method of the encoder storage subsystem. As noted above, memory is y
T? -t A, y]? -) It has an output port marked B. When the output of port A is active to read the pixel value of a particular scan line, port B is used to read the pixel value of the corresponding pixel of the next scan line. This facilitates generation of sum and difference signals. The output taken from each port in parallel is the value of 12 consecutive pixels of one scan line, i.e., 240 pixels per sequence (33), as described with respect to encoder memory addressing and control. It is a dedication. Port A output buffer register 360 and port B output buffer register 365 each operate under the control of the encoder output clock.
It is a stage parallel input series output renoster.

The counter 370 of the Mosoyuro 12 counts the encoder output clock/clock and thereby clocks the respective port A
And f? - Parallel-in-serial-output output buffer registers 360 and 365 for gate B produce outputs that are used to strobe a sequence of 12 pixels in each of two consecutive scan lines. The output of counter 370 is connected to a modulo 2 subsequence counter 375 that keeps track of which half of the originally stored 24 pixel sequence is addressed. Therefore, the single bit output of counter 375 is part of the address input to the encoder memory output port. The output of counter 375 is connected to a modulo 48 sequence counter 380 whose output count determines the other part of the address, i.e. the sequence of the particular 24 pixels being addressed at both ports (34). It shows. The output of counter 380 is connected to a modulo 241 scan line counter 385 which outputs counter 3
The output of 85 is coupled to a quadruple circuit 386. The output of multiplier 386 is connected to one input of adder 387. The other input to adder 387 is the output of gate 388.

Key) 388 has an input representing the number 2 and is enabled throughout the generation of the odd TV field. The output of adder 387 is the scan line number portion of the baud)A address and is also connected to another adder 389 which adds one. The output of adder 389 is yl? - This is the scan line number part of the B address. In operation, the scan line address circuit just described operates such that the scan line address of A) indicates an odd scan line and 1? - Operate so that the scanning line address of the gate B indicates an even numbered line. For two ports, between even fields there are scan line sets 0, 1 then 4, 5 then 8 degrees 9...
・During odd fields,
Scan lines 2 and 3 are addressed, then 6 and 7, then 10°11, and so on. In this way, an interlaced output is obtained by alternately aligning sets of scan lines in a high resolution array. Therefore, a complete address at baud)A(!:H) successively provides pixels from successive scan line pairs of the stored video frame, and the pixel values are addressed 12 bits at a time to the output 360. It can be seen that it is strobed with 365.

FIG. 6 shows the sum and difference signals used to generate the intensity signal from ports A and baud 1-B when these outputs are clocked in series from the PA and FARENOSTA 360 and 365, respectively. ' A part of the JiJ generation circuit 600 is explained. This circuit consists of arithmetic unit 6]0
and 625, as well as storage registers 615, 620 . and 6
It has 30.

The arithmetic unit 610 receives the outputs of baud A and B.

The output of the arithmetic unit 610 is stored in storage registers 615 and 62.
0, and the outputs of these registers are sequentially connected to an arithmetic unit 625.

The output of the arithmetic unit 625 is in turn stored in the storage register 63.
0, and the output of this register 630 is the above (1).
The desired sum signal ■ is obtained according to the relationship in the equation.

The arithmetic units and storage registers described herein receive the vertical and horizontal synchronization signals and the encoder output clock signal, and perform the control sequence described in the flowchart of FIG. 7 to obtain the sum shown in relation (1). It is under the control of a ROM sequencer 6050, which generates.

In particular, the first set of pixels from port A and port B are
As represented by block 721, arithmetic unit 61
It is input to 0. Arithmetic unit 610 is controlled to sum this initial set of pixels. That is, (Ao + Bo) is created as described in the group of FIG. 2, and as represented by block 722. The output of the arithmetic unit 610 is stored in register 6]5 (block 72
3). The second set of pixels of the group is then input to computational unit 610 (block 724).
, again controlled to form an addition function (block 7
25). The result is registered in register 621 (block 725
). The outputs of registers 615 and 620 (37) are output to arithmetic unit 625 (processor 727), which is controlled to create a sum (block 728) in accordance with the relational expression (1). Arithmetic unit, l-
The output of 625 is stored in register 630 (block 7
29) and output from register 630 (block 73).
0) Works as a sum signal output I, and the signal engineer outputs the transmitting circuit 30 (
For example, it is connected to Fig. 1).

In FIG. 8, the outputs of baud)A and baud)H are each 360
A sum and difference signal generation circuit 600 (Fig. 3
) explains some of the This circuit is a calculation unit)66
0 and 675 and storage registers 665, 6701 and 6
Contains 80. Computing unit 660 receives the pixel streams of port A and port B. Arithmetic unit 660 is connected to storage registers 665 and 670, the outputs of which are in turn connected to arithmetic unit 675. The output of the arithmetic unit 675 (38) is then connected to the storage register 680, and the output of this register is converted into the above (2), (3) P (
According to the relational expression 4), x, y, and 2 become Z difference signals. The arithmetic unit and storage registers described here are 'I ROM'.
Although it is under the control of sequencer 655, this sequencer 6
55 receives the vertical and horizontal synchronization signals as well as the encoder output clock signal and creates the control sequence described in the flowchart of FIG. 9 to obtain the desired difference signal. Modulo 3 counter 690 responds to an alternating vertical synchronization signal to provide three outputs that act as codes to determine which of the X, Y, and Z difference signals should be generated for a particular frame. Create one of the counts. This output code is 1, which is connected to the transmitter circuit 30, so that it is transmitted and used by the receiver's decoder circuit to distinguish between the difference signals at the decoder.

In FIG. 9, the determining diamond 905 indicates the difference signal code X,
It represents the decision as to whether Y or Z is alive.

If the X code is valid, it is entered in block 911. What about this block? - Compute the first set of pixels from A and B.

This indicates input to the trolley 60. Arithmetic Uni, Toro 60
is controlled to sum this set of pixels, as represented by block 912.

The output of arithmetic unit 660 is stored in register 665 (block 913). The second set of pixels in the group is then computed (block 914).
is input and controlled to again form an addition function (block 915). The result is stored in register 670 (block 916). The outputs of registers 665 and 670 are coupled to arithmetic unit 675 (block 9
]7), which is controlled to make a difference (block 9
18).

The output of the arithmetic unit 675 is stored in a register 680 (block 921) and from the register 680 (block 9
22), which is output as a difference signal X which is connected to the transmitting circuit 30. This process is repeated for the next group of two sets of pixels, and the procedure continues for each set of scan lines of the frame. In this way, it can be seen that the X difference signal is created by the relational expression (2) above.

During the next frame, when the Y code is alive, the shunt starting at block 931 becomes active. In particular, the first set of pixels is
1), which is the difference between this pair of pixels, i.e. (Ao
-Bo) as represented by block 932. The output of arithmetic unit 660 is stored in register 665 (block 934). The second set of pixels of the group is then input to arithmetic unit 660 (block 934), which is again controlled to perform the subtraction (block 935). The result is stored in register 670 (block 936).

The outputs of registers 665 and 670 are output to arithmetic unit 675 which is controlled to form a sum (block 938). Blocks 921 and 922, as before, serve to control the storage in register 680 and the output from register 680 of the Y difference signal, which is inconsistent with the relationship previously shown in equation (3). .

(41) During the next frame, when the Z code is alive, the shunt starting at block 941 is active. A first set of pixels is input to an arithmetic unit 660 (block 941) which calculates the difference of this set of pixels, i.e. block 941.
It is controlled to create (Ao-Bo) as represented by 42.

The output of arithmetic unit 660 is stored in register 665 (block 943). The second set of pixels of the group is then input to arithmetic unit 660 (block 944).
, which is controlled to perform the subtraction again (block 9
45). The result is stored in register 670 (block 946).

The outputs of registers 665 and 670 are sent to arithmetic unit 675.
and is controlled to perform subtraction (Pro 948). Blocks 921 and 922, as before, store the difference signal Z in register 680, consistent with the storage in register 680 and the relationship shown in equation (4) above.
It works to control the output from 0.

Referring to FIG. 10, decoding circuit 50 (FIG. 1) (42
) is shown. Receiver circuit 4
The sum and difference signals reproduced by 0 (Fig. 1) are:
'l, //]: is connected to a converter 1010 which operates to convert these signals into disortal form.

The digitized signal is stored in the decoder storage subsystem 1
100, and this subsystem is connected to the present embodiment in such a way that it simultaneously produces the latest digital information, i.e., a sum signal (I) and three difference signals (x, y, z) at four output ports. Now it works. These signals are combined by the pixel value generation circuit 1300 according to relations (5), (6), (7), and (8) to reproduce the high resolution pixel values originally stored in the encoder. The output of circuit 1300 is coupled to D/A converter 1015, which converts the dinotal signal output from circuit 1300 to an analog format suitable for display on high resolution monitor 1018.

FIG. 11 illustrates the input control and addressing of the decoder storage subsystem 1100. The storage is organized in this embodiment as four two-bit memory blocks of RAM, each with 482 scan lines.
Each pixel can store 576 (12×48) 8-bit pixel values.

The four parts of the decoder memory are intensity memo 1/121°, difference signal x memory 1122. They are called a difference signal Y memory 1123° and a difference signal Z memory 1124. These memory portions are connected via their respective input ports to 'I I,
It operates to store signals labeled X, Y, and Z, respectively. These signals are then read out at the respective outputs of the memory portions and combined as will now be described.

The intensity channel signal I is received by an A/I) converter 1010a, which converts the analog signal to 8-bit di-notional pixel values at a decoder intensity channel clock rate, which is typically the same as the encode output clock rate. The input buffer recorder 1130 is connected to the memory 1121 in parallel.
A serial-in parallel-out register that receives twelve 8-bit pixel values that are strobed. modulo 12
The counter 1135 counts the clock pulses and stores the 12 pixel information from the buffer 1130 in the memory 11.
Create a strobe signal that operates to strobe 21. The output of modulo 12 counter 1135 is counted by modulo 48 counter 1140, the count consisting of the sequence address portion of the address coupled to memory 1121. The output of the modulo 48 counter 1140 is connected to the modulo 482 counter 1141,
The count of counter 1141 constitutes a line address input to memory 1121. Therefore, each group of twelve 8-bit pixels is strobed to the appropriate sequence address and line address in decoder strength memory 1121.

The difference channel signal is connected to an A/l) converter 1010b, which converts the difference channel signal into an 8-bit Convert to pixel value. The difference channel signal is also connected to a decoder 1155 which detects the difference process code (x, y or 2) and outputs the
Determine which of the Y and Z difference signals is present during the current frame (45). Decoder 115
The output of 5 outputs a usable signal to one of three dates: X-key 1156, Y-key 1-1157, or 2-key
) 1158. The decoded signals also include X, Y as an address selection indication.

It is also connected to each memory of Z. A/D converter 101
The 8-bit pixel value output from 0b is the date 1156, 1157 . or through 1158, serial input parallel output pufferenostar 1172°1173,
or connected to the input of 1174.

The input address generation for the x, y, z portion of the decoder memory 1122, 1.123.1] 24 is similar to the address generation for the intensity memory section 1121. (If the input clocks are selected as the same, the input address generation for the X, Y, and Z memory sections is common to the input address generation for the intensity memory section.) The clock signal is connected to a modulo 12 counter 1181. , the output of the counter]181 is sent to the buffer 11.72.

This is a strobe signal used to strobe the contents of 1173 or 1174 into their respective memories.

However, only one memory whose selected address line of the memory section is active can identify the address to which the pixel value is strobed. The output of modulo 12 counter 1181 is connected to modulo 48 counter 1182, whose count constitutes the sequence address for the sequence of 12 pixels being strobed, as described above. The output of modulo 48 counter 1182 is also modulo 48
It is also connected to the counter 1183 of counter 1.
The output of 183 again serves as a line address. Strobe and address signals are sent to memories 1121.1122.
and 1123, along with a memory portion selection address. Therefore, the decoder memory sequentially stores the intensity channel signals in the decoder memory section 121 and in turn the X-difference signal.

The Y difference signal and the Z difference signal are stored in memory units 1122, 1123 and 1124. At this time, each of the difference signal memories is
The slow information rate, i.e. in current typical implementations,
It is updated once every three video frames.

Referring to FIG. 12, the receiver memory output ports and output addressing scheme are shown. memory part 112 ],
, 11.22, 1123, and 1124 are each 2
It has parallel outputs of four pixels, and these outputs are parallel input serial output buffer renostars 1221 and 12, respectively.
22,1223. and 1224, and the serial outputs of these registers are connected to the intensity channel signal ■ and the three difference channels (N.

This is an 8-bit dinotal signal representing y and zl, respectively.

The counter J231 of modulo 24 counts the decoder memory output clock/master pulse, and this clock pulse has a higher speed than the decoder memory output clock (for example,
In this embodiment, the speed is twice as fast). The output of the modulo 24 counter 1231 is the memory 1121, 1122,
1,123.1124 to 24 pixels in parallel, each output panfare sensor 1221.1222. ]2
23. and 1224 as a loop signal. The output of the counter J231 of the modulo 24 is also connected to the input of the counter 1232 of the modulo mouth 24, and the count number of this counter 1232(7) is used as a sequence address to the four memories 1121, 1122, 1123, and 1124. Ru. modulo 24
The output of the counter 1232 is coupled to a modulo 482 counter 1233, and the count number of this counter 1233 is stored in the memory l I 2 ], ], ] 22 , 1
123, 1.124. Therefore, during the elapsed time of each frame, the memo IJ
], 12].

1122.1123.1124 output the latest stored frame of I, X, Y, Z information from their respective buffers. As already mentioned, information is "updated" every frame, and x, y, z difference signal information is "updated" every three frames.
will be updated. Therefore, the X, Y, and Z outputs are each "new"
The information is redundantly read three times before being read.

Referring to FIG. 13, the pixel value generation circuit 1.3 of the decoder
00 (FIG. 10), which operates on the output of the decoder storage subsystem to
The original pixel value is reproduced according to the relational expression of ) to 4). There are four operating units under the control of the ROM soaker [305]]310.13].

13]2. and 1313 are used. Arithmetic unit 131], 3]0 receives the sum signal ■ and one of the difference signals X, and the arithmetic unit 131] receives the difference signals Y and Z. The output of the arithmetic unit 1310 is the arithmetic unit)13]
Connected to each input of 2 and 1313, operation unino) 131
The output of 1 is connected to one more input of arithmetic units 1312 and 1313. The outputs of operations UNINO+-1312 and 1313 are each coupled to two inputs of a state switch 1320, and the output of 1320 is coupled to the input of a D/A converter 1350.

The output of converter 1350 is connected to a summing circuit 1375 which also creates a locally created composite synchronization and blanking (as previously noted) for the received TV signal. ), producing a composite output high definition TV signal. Switch 1320 and D/A converter 1350 operate at the decoder video output clock rate, which is typically the same as the encoder clock rate used for the original clock in high resolution pixel information. A ROM sequencer 1305, which receives a synchronization signal and a video output clock, controls the state of the arithmetic unit.

FIG. 14 explains the routine of ROM sequencer 1305. Decision diamond 1405 represents a question as to which field of the frame is currently being created. The field information is obtained from the receiver's synchronization and blanking circuit to the ROM sequencer. If it is the field of the first frame (odd field), an odd number of output lines should be created, and the pixels of each pixel group.

It will be understood that and A1 will be created (
(see Figure 2). Pixel A. is created according to relational expression (5). block]411 is the arithmetic unit 13]0,131
1.1312 indicates that these units are controlled so that they each perform addition. As a result, calculation unit 1
．． The output of 312 is A according to relational expression (5). Show all (
4] 2).

Solid Stay 1-Switch 13201. , which is clocked at the same speed as the ROM sequencer by the decoder video output clock, samples the output of the arithmetic unit [3]2 for the pixels Ao of each group, and also samples the output of the arithmetic unit Ao for the pixels A of each group. 1313 output. When the next clock pulse occurs, in order to process the next pixel, arithmetic units 1: 310 and 1311 are controlled to perform a subtraction and arithmetic unit 1313 is controlled to perform an addition (block 1413). As a result, the output of the arithmetic unit 13]3 (block]4]4) corresponds to the formula for the desired A1 according to relational expression (6). This signal is transmitted from the arithmetic unit 13 ] 3 to the solid state switch 1320
is the same unit l-] 313 II) When sampling the output 1, the set of adjacent pixels of each odd-numbered scan line is processed in this way. When the feel of the second frame)'' (even number) is being generated, the outputs of the arithmetic units 1312 and 1313 are synchronized with the operation of the solid-state switch 1320, and the relational expressions (7) and (8) are generated. ) are used to create signals for Bo and B, respectively.

In particular, for pixel B0, the arithmetic unit 13]0 and 1
311 is controlled to perform addition, arithmetic unit) 13
1.2 is controlled to perform the subtraction (block 1421
). As a result, the output B from operation unino) 13]2. The pixels will be based on equation (7). As mentioned above,
This pixel value is output to a solid-state switch 1320 that samples the output of the arithmetic unit 1312 in synchronization with the switch. This solid state
When the switch is receiving the output of the arithmetic unino) 1312, the arithmetic unino) 1310, 1311゜1313
are all controlled to perform subtraction (block 1423) corresponding to relational expression (8), and as a result, an appropriate value for the pixel B of the group can be output (block 1
424).

In typical embodiments described herein, the encoder produces the perfect complement of the difference signal at one-third the rate at which the low-resolution intensity signal (sum signal) is generated.

Since each different individual difference signal is produced simultaneously with the intensity signal, the output, t? - The signals from ports A and B (FIG. 5) can be used to create both sum and difference signals (using the combinational circuits of FIGS. 6 and 8). but,
As will be described later, by further slowing down the generation speed of the difference signal to the fullest extent permitted by considering the visual recognition ability,
It may be desirable to further conserve bandwidth. Figure 5
In , the ports labeled A' and B' and their associated clocks may be independently capable of generating the difference signal at any desired rate.

In the first embodiment already described, the decoder also includes a memory IJ for storing the incoming intensity (sum) signal and the difference signal.
'(r) and then read out the stored signals (with redundancy, at least in the case of difference signals) to a combinational circuit that produces high-resolution pixel values.

However, it should be noted that the decoder could alternatively be implemented as described above by combining previously stored high-resolution pixel values (i.e. from previous frames) with the sum and difference signals when they are received. It is important to pay attention to.

Although the first exemplary embodiment has been described in terms of a black and white system, the principles of the invention apply equally to color systems, as further disclosed below. For TV broadcast applications, colors can typically be encoded on 525 carrier waves. For high quality reception, even higher resolution chroma signals are used. For example, a 90 degree chromaticity coordinate can be transmitted with a resolution of 525 scan lines in both the horizontal and vertical directions. 30 pieces of information per second
does not need to be created (sent) at frame rate;
Lower chroma frame rates are preferred to conserve bandwidth, as explained below. A difference signal containing high resolution chromaticity information is employed and frames can be sent sequentially.

As noted above, various pixel blueprints can be square, rectangular, straight, or irregularly shaped.
Configurations may be used consistent with the principles of the invention. The number of difference signals required in each case is a function of the number of pixels in one gruno. Let us review the psychophysical measurements carried out by the applicant at 111, which describes another embodiment of the invention. . Certain aspects of the invention are based on that measurement. Contrast sensitivity thresholds for monochromatic luminance gratings and isoluminant chromaticity gratings were measured at a number of temporal frequencies, over a spatial frequency range that is important in TVs at common viewing distances. As a result, a series of ocular modulation transfer functions were obtained at these spatial and temporal frequencies. Measurements have shown that some of the information necessary to determine the ocular time constants for both luminance and chrominance can be obtained and the desired ratio of reproduction can be obtained at the resolution required for the luminance and primary color difference signals. It can also be used for evaluation.

A simplified steady state contrast sensitivity curve of the eye is shown in FIG. This figure shows the brightness and brightness C of white and NTS
The eye's response f1 is fully shown for silk of equal luminance complementary colors on the line on the CIE diagram for examining the three primary colors. Since the color curves are normalized, all four curves are equal in their maximum sensitivity. This normalization equates the minimum perceptible color difference as opposed to the minimum perceivable luminance contrast for all three primary colors at low spatial frequencies. These curves end at spatial frequencies where color is no longer perceivable. Gratings above this spatial frequency are still visible, but appear monochromatic at all color contrasts. From these curves and the endpoints, it becomes clear that the color difference signal should be approximately half the luminance resolution for R-Y and one-fourth the resolution for B-Y, so considering both the horizontal and vertical directions, this are 1/4 and 1/16, respectively, in terms of luminance bandwidth.
corresponds to

A second series of measurements was performed to determine the perception of spatial frequency as a function of duration. The duration is 1.2
．． 4.8.16.32.64.128 fields were used (17 m5 per field). Figure 16 plots the eye's relative sensitivity to the photometric grating as a function of the grating presentation time. This is shown both in luminance and chrominance,
The eye fits into the grid and becomes more invisible. In a short presentation time such as 0.01 seconds,
These spatial frequencies are greatly enhanced in visibility compared to the steady-state visibility of the grating; for very short presentations, all spatial frequencies are suppressed.

FIG. 17 shows the corresponding curve k1.2° of the equiluminant chromaticity grid,
9. and 27 cycles/degree as a function of duration.

The presence of motion generally results in low spatial frequency brightness changes that suppress reception for some time. The suppression of the grating (target) actually precedes the mask for a short time. The target object was presented both behind the mask (front masking) and in front of the mask (back masking). The degree of suppression by the 01 second mask was 611 constant (~611) using TV that was not broadcast as a signal during masking. Spatial frequencies (target grids) were presented for various intervals immediately before or after masking.

FIG. 18 plots the relative responses of the eye to these stimuli when the grating duration is varied just before or after the mask. This experiment was conducted for the duration (Figures 16 and 17).
) and the effects of masking. In scenes that are not exactly covered by moving objects in the video,
The detailed information shows what happens to the sensitivity of the eye.

FIG. 19 shows a family of curves corresponding to FIG. 18 for an isoluminant chromaticity grid. - As can be seen, the suppression is noticeable above 4 cycles/degree for luminance and 09 cycles/degree for chrominance beyond 200 m5. Masking is both luminance and chrominance, primarily pre-masking. Suppression of low spatial frequency luminance in 1° targets occurs only for about 50 ms before or after the mask. From this it may be concluded that a frame rate of approximately 20 frames per second is necessary to depict motion at low spatial frequencies, as is known in cinematography.

In another form of the invention, electronic processing is performed to obtain a representation of the low and high spatial frequency components of an image prior to storing the frame in digital form.

Low spatial frequency representations can be used for standard resolution transmission that is compatible with existing equipment.

Referring to FIG. 20, a block diagram of the luminance processing portion of encoding circuit 20 is shown in another embodiment of the present invention. The high-resolution video signal from camera 10 is passed through a low-pass filter 2010, the output of which is used to obtain a standard M-resolution image, and is connected to a three-wire vertical-to-sautian average circuit 2020. circuit 202
0 has two series-line delay giant circuits 2021 and 2022.
, weighting amplifiers 2026, 2027, 2028° and a summing amplifier 2029. The corresponding vertical elements of three successive scan lines are weighted by amplifiers 2026°2027.2
028, these amplifiers weight the elements from the scan lines]/4 and 1/2, respectively.

1/4 is added, and these are added by an adder 2029. Applicant notes that spatial frequency aliasing artifacts may occur in standard-definition receivers when alternative high-resolution scan lines are used to create the standard-definition signal, due to the long-sword-shaped nature of the sampling window used. We discovered that this can occur. By adding together the proportionally weighted values of the elements from at least three successive scan lines,
This artifact can be virtually eliminated.

The output of the circuit 2020 is connected to a solid-state switch circuit 2030 that passes the output signal only during the occurrence of odd scan lines of the high resolution video signal in response to an odd/even scan line indicator 2040. . Before connecting the output of switch circuit 2030 to leopard converter 2045,
Optionally, a time-paced correction circuit 203 is provided to reduce the sizing rate requirements of the quality changer 2045 and the amount of memory in which standard resolution luminance must be stored.
5 (since there are only every other output).

In order to finally reconstruct the high resolution image brightness, not only the high frequency components of the odd scan line signals but also the even scan line signals are used to obtain the high band brightness signal.

In the illustrated embodiment, the high resolution video from camera 10 is also coupled to a separate delay equalizer 2050 whose output is connected to the positive input terminal of a differential amplifier 2060.

Differential amplifier 2060 subtracts the low band component from the high band component of the odd scan line signal. Selecting an odd scan line from the differential amplifier output is performed by an odd/even scan line indicator 204.
This is achieved with another switch circuit 2070 under the control of 0. Another input to switch circuit 2070 is the high band even scan line luminance signal. Therefore, the output of the switch circuit 2070 connected to the leopard converter 2080 includes the luminance component of the high resolution video signal. but used to generate a standard definition signal (as in the embodiments described above, to avoid redundancy of this information and save bandwidth).
Remove low-resolution components associated with odd-numbered scan lines.

In the presently described embodiment, color handling is described, and FIG. 21 shows a block diagram of the chrominance processing portion of the encoder circuit.

In this embodiment, the color difference signals indicated by B-Y and R-Y are described as being output from the high-resolution camera 10. In reality, these signals are selected at specific orthogonal reference points of the color vectorscope that do not necessarily correspond to B-Y and R-Y. The chrominance processing of this embodiment is as described in connection with FIG. It has many aspects similar to brightness processing. Vertical spatial waves are again provided using two one-line delay circuits for each of the color component signals. However, in this case, the vertical spatial frequency characteristics of standard NTSC chrominance are sufficient for high-resolution color, so to obtain both standard-resolution and high-resolution color component signals,
Only odd numbered scan line information is processed. R-Y and B-Y
The signals are each applied to the vertical Gaussian averaging circuit 202 of FIG.
Circuits 2110 and 2120 operate in a similar manner to 0.
It is connected to the. In particular, each of these circuits includes a set of -line delay circuits 2111 and 2112, three weighted amplifiers 2116, 2117, 2118 . and summing amplifier 2
It has a built-in 119. The outputs of the circuits 2110 and 2120 are connected to switch circuits 2]15 and 2]25, respectively, which switch circuits respond to the output of the odd/even scan line indicator 2040 to select the odd scan line of the high resolution video signal. The output signal is passed only during the generation of . The output of the switch circuit 2]15 is connected to the positive input of a differential amplifier 2132 and a low-pass filter 2130 via a delay equalizer 213]. A negative input of differential amplifier 2132 receives the output of low pass filter 2130. Low pass filter 2
The output of 130 and the output of differential amplifier 2132 are connected to optional time base correction circuits 2134 and 213, respectively.
5, and as above, these correction circuits can be used to reduce the sampling rate requirements of the downstream transducer as well as of the memory in which the chrominance component signal is to be stored.

The output of the time base corrector circuit 2134 and 2]35 is
are connected to transducers 2144 and 2145, respectively.

In the B-Y channel, the output of switch circuit 2125 is coupled to a circuit that has substantially the same functionality as shown for the R-Y channel. However, a prime sign (') is used to indicate the circuit reference number. In this channel, the low pass filter 2130'stop converter 2
144' can operate at a lower frequency (eg, half the frequency, half the scan line rate) than its R-Y channel counterpart. This is due to the low bandwidth requirements of standard resolution B-Y signals.

Referring to FIG. 22, a block diagram of a memory and output implementation of an encoding circuit (20) of a further form of the present invention is shown. The six outputs of the circuit of FIG.
11 to 2216, and as already mentioned, these memories are provided with independent input and output ports, e.g. Input and/or output speeds are adjustable. In this example embodiment, the input to the memory is at a nominal rate of 30 frames per second, and the output of the memory holding the standard resolution signal is also at 30 frames per second. (Of course, it will be appreciated that other speeds can be used anywhere.) The high resolution luminance output of memory 2214 is set at an output frame rate of 3 to
It is desirable to have 15 frames/second. To maximize bandwidth savings while retaining virtually high resolution, approximately 5
A rate of frames per second is considered suitable. In this embodiment, the high-resolution RY frame rate is the same as the high-resolution luminance frame rate, and the high-resolution B-Y frame rate is 3.
It is desirable that the speed be in the range of ~30 frames/second. (B
-Y signal is R-Y, consistent with NTSC standard TV.
Since it can be transmitted with only ]/4 of the bandwidth, it can be done at a nominal rate of 30 frames per second without significant bandwidth compromise. ) Note! The outputs of J2211-2216 are D/
It is connected to A converters 2221 to 2225.

The standard resolution color difference signal is 90° to the color subcarrier signal.
It may be modulated (block 2230) and the resulting chrominance signal (chrominance signal) may be combined with the luminance signal using a summer 2240 to obtain a chrominance video signal at virtually standard resolution.

The video signal is delayed by delay circuit 2250 and then transmitted and/or recorded. The high resolution signal may be transmitted and/or recorded by, for example, transmitter circuit 30 (FIG. 1). The purpose of the delay (individual delays in separate channels may be used instead) is to effectively accelerate the high-resolution portion of the image with respect to the low-resolution portion of the image, ultimately resulting in The goal is to maximize the masking of the slow build-up of high-resolution information in the displayed image. Preferably, the delay is in the range 30-200m5. If the delay is too long, details will appear before they are expected to become visible.

Referring to FIG. 23, a block diagram of an embodiment of a decoder according to a previous form of the invention is shown.

It will be appreciated that the standard definition video signal may be utilized by a standard definition receiver (eg, as shown in FIG. 1) after being received by receiver circuitry (40). Figure 2
In the high resolution decoder of No. 3, the standard resolution channel is connected to a low pass filter 2305 to remove chrominance and also operates in conjunction with low pass filters 2307 and 2308 to recover the color difference signals R-Y and B-Y'i. 90 to do
Also connected to the ° detector 2306. The reproduced standard resolution signal components are each input to an A/D converter 23 ] ].

Connected to 2312.2213. The high-resolution luminance and color difference signals obtained by
315. and 2316. The outputs of the transducers are each connected to six memories 2321-2326, which, as shown in the figure, reconstruct high-definition frames in connection with the first embodiment, as described above. can be provided with independent input and output ports to allow the generation of the necessary video information. In this embodiment, inter alia, the memory produces odd numbered scan lines for the luminance and color difference signals respectively, and the standard resolution odd numbered scan lines are as described above in order to obtain an average of the vertical elements as well as a reduction of artifacts. , contains weighted portions of adjacent even-numbered scan lines. Low frequency signals from standard resolution odd field scan lines are averaged vertically.
It is reproduced using the circuit 2340'i in a manner similar to "reversely returning".

One odd-numbered scanning line from the standard resolution luminance memo 'J 2321 and both adjacent even-numbered scanning lines from the high-resolution luminance memo IJ 2324 are connected to their respective D/A converters 233.
1.2332.2333, the weightings are connected to amplifiers 2341, 4.342 and 2343, respectively. Each weighting amplifier has a weighting factor of 2. -1. -1. For weighting, the outputs of the amplifiers are summed in an adder 2344, and the outputs of the adder are sequentially low-pass filtered in a filter 2345. High resolution brightness memo IJ 23
The odd scan line output from 24 is connected to a D/A converter 2334, the output of which is high pass filtered by filter 2346 and then connected to one input of adder 2347. Another input to the adder is low pass filter 2
Therefore, the output of the adder 2347 becomes the information of the reproduced high-resolution odd-numbered scanning line. [It will be appreciated that odd and even scanlines can be obtained using appropriate scanline delays with respect to the output of the memory, i.e. by accessing the appropriate output ports for different scanline information.] Dew. ] The output of the D/A converter 2333 is high-resolution even-numbered scanning line information, but the solid stay 1... switch 2350
Another input to the switch is the high-resolution odd scan file information of the adder 2347. The switch 2350 is under the control of the odd/even scan line indicator 2351 and selects high resolution odd scan line information or high resolution even scan line information depending on the current scan line state.

High resolution color difference signals are reproduced in a similar manner. In this case, the low resolution and high resolution R-Y signals from memories 2325 and 2323 are sent to D/A converter 233, respectively.
5 and 2336, and their analog outputs undergo high and low pass filtering by filters 2356 and 2357, respectively. The outputs of filters 2356 and 2357 are input to adder 2358, the output of which thus constitutes the odd scan line RY signal (remembering that color difference signals are obtained only from odd scan lines). The output of the adder 2358 is the − line delay circuit 23
61 and its output is connected to another adder 2362
This is one input to the . Another input of adder 2362 is the output of adder 2358. Adder 2362 has an inherent weighting factor of ]/2 so that its output is the average of successive odd numbered scan lines. Solid state switch 2363 is then used to alternate between the odd scan line output of adder 2358 and the even scan line output of adder 2362, which is derived from averaging the odd scan lines. The output of the solid state switch includes a high resolution RY signal.

The high resolution B-Y signal is reproduced in the same manner as the R-Y signal. In particular, high resolution B-Y memory and standard resolution B-Y
The output of the memory is connected to D/A converters 2337 and 2338, and then to filters 2371 and 2372, respectively.
The output of the filter is connected to an adder 2358'. Adder 2358', -line delay circuit 2361
', adder 2362', and switch 2363' are B
-Y operates in the same way as its counterpart in the R-Y circuit to obtain high resolution resolution. The high resolution luminance and color difference signals are then decoded in well known manner and applied to the high resolution display 6o.

The goals for reasonable image quality for high-definition TV broadcasting systems are 3.
It has been said that it should be of good quality, equal to or better than 5++lll1 movie film. According to some analysis (Ll
, by Pourciau [High Resolution T
VI, SMPTE Conference, October 1983), a scanning system of about 1000 scan line resolution [as mentioned at the outset] with comparable horizontal resolution and reasonable compensation is 3
It is said that it should closely match the t1 capacity of 5m+n movie film. As seen from FIG. 15, R-Y and B-Y
The high frequency cutoffs of the signals are approximately a factor of 2 and 4, respectively, which are lower than the high frequency cutoff of the Y signal. 3～
A system based on these values, using an aspect ratio of 5, would have approximately the following bandwidth requirements:

Y-21, OOMHz RY -5,25Ml (z B -Y -1,31MHz Total 27.56 MHz This bandwidth can be reduced by exploiting the "oblique effect" in vision.Human visual system It is known that the resolution is worse in the diagonal than in the cardinal (horizontal and vertical) directions. (Appelle
, S, J. Perception and discrimination as a function of stimulus direction. Oblique effects in humans and animals, Journal of Psychology, Vol. 78, 266.
~278 pages, 1972) and Timney, B.
N., Muir, D.W., [Directional Anisotropy, Incidence and Magnitude in Caucasians and Chinese People,'' Science, vol. 193, pp. 699-701, 1976, etc.). FIG. 24 compares the average (eight subjects) normalized contrast sensitivities for YXR-Y and BY signals for gratings oriented in the cardinal direction (solid line) and oblique direction (dashed line). As can be seen, at high spatial frequencies, the human visual system has approximately a times lower resolution for all three signals in the diagonal direction.

Figure 25 AVi human visual system at maximum sensitivity of 30 cm,
The polar coordinate distribution of the limit resolution response is Zoron I□Lfc,
It can be seen that the highest sensitivity of about 20 cycles/degree is in the cardinal direction. Figure 258 shows the polar coordinates of the spatial frequency obtained from a 35mm film viewed at 35 times the screen height, and Figure 25C shows, for example, the already mentioned 100mm
0 scan lines (vertical and equivalent horizontal) resolution high quality T
From the V system, it shows the polar coordinates of the spatial frequency. Clearly, the sampling method by which TV signals are generally obtained does not suit the characteristics of the human visual system very well. A TV Zanzo ring system that is much more “effectively” matched to the human visual system of FIG. 25A is shown in FIG.
The slight loss in perceived resolution on the 9-diagonal that can be obtained from a 0-line scan high-definition TV system is compensated for by a slightly better "Kell factor" obtained by oversampling the image and pre- and post-filtering. be done. Utilizing these techniques for Y, R-Y, and B-Y signals has approximately the following bandwidth: Still images can be obtained with resolution limits very close to the perceived resolution limits of human vision.

Y I O, 50M) Tz R'-Y -2,63MH7゜B -Y -, 66MHz Total 13.79 MHz As already mentioned, the technique of drawing moving images deals with high-resolution information in human vision. It is developed using Neuron's slow temporal response.

And this makes it possible to create high-definition TVs that can be compatible with existing TV receivers.
Further reducing the overall required bandwidth in the system. According to a feature of the present embodiment, portions of the vector are encoded onto standard definition video frames above 2.5 MHz, where the color and luminance information is not well separated by conventional color TV processing methods. Improvements have also been shown in processing. .

Simply put, conventional NTSC transmission is 25MH
It is modified by adding together the R-Y, , B-Y and Y signals over z. The information is then typically repeated for two successive frames, with the color carrier phase reversed. On the receiver side, frame storage can be used to add or subtract these two identical frames. The sum signal provides a Y signal of 2.5 MHz or higher without a color signal. (The color signal is created identically for the two frames, but the carrier waves are in opposite phase.) The difference between the two frames gives the color without color mixing. Since the brightness is the same for the two frames, the difference is zero in this frequency range. Depending on this arrangement, 2.5
The frame rate for color and luminance above MHz is half the conventional frame rate, or 15 frames/second. However, based on the applicant's psychophysical studies, this is sufficient.

The system of the present embodiment is compatible with standard receivers, and which we will now describe as an "upgraded" system that includes frame storage and circuitry for decoding the same frame of successive color and detail brightness information. In other words, it is compatible with television receivers (which are more advanced than the standard but not completely high-resolution). In either case, the lower frame rate for color information and detail luminance information does not result in any noticeable degradation in perceived image quality due to the aforementioned characteristics of human vision. However, in advanced receivers, improved color and detail brightness separation is clearly an advantage. This advantage also exists in high resolution complete receivers that further include high resolution luminance and color component signals.

With the aforementioned modifications to the standard NTSC transmission, the Y signal at 4.2 MHz 'i, without color or brightness mixing,
It is possible to transmit I and Q signals up to a normal bandwidth. High resolution luminance as well as chrominance detail information can be transmitted at a rather low frame rate. One example is to use 75 frames per second and diagonal sillage (to take advantage of the diagonal effect).

A modified standard NTSC transmission at 4.2 FilfHz will carry lower resolution information that is changing more rapidly. Another low bandwidth channel is used to carry the remaining high resolution detail and color information at a rate of 75 frames per second. FIG. 26 shows the video coverage of the system. 2.5 without changing the interlaced scanning speed of 30 frames/sec.
A conventional low frequency channel is used to transmit the luminance signal at MHz 1 (band 2601). 2
．． 5 MHz to 4.2 MHz? , the detail luminance and chrominance signals are repeated to provide a 15 frames/second display (band 2602). Other frequency bands are 75
Used to transmit higher detail luminance and detail chrominance in frames per second (band 2603). This additional channel requires a scoop of bandwidth to transmit these detail signals.

Y 1.30 MHz RY-, 60 MHz B-Y-, 15 MHz Total 2.05 MHz Referring to FIGS. 27 and 28, block diagrams of encoders according to embodiments of the present invention are illustrated.

This encoder, like the spectrum of FIG. 26, can be used to obtain signals for transmission and/or storage of the type just described. A high resolution color camera and related circuit 2711 are provided, Y, R-Y, B
It has as output a high resolution signal marked -Y. In the illustrated embodiment, a diagonal index of elements is used to provide the benefit of off-centing the base clock 2712 by one element on successive scan lines (i.e., alternating for interlaced signals), as described above. in the field). The camera circuit receives synchronization and drive signals from subsystem 2713 which is connected to clock 2712 . In alternating fields the clock is offset. The high resolution luminance signal Y is subjected to low pass filtering, as shown at block 2721, to obtain a standard resolution low frequency luminance signal, represented by band 260 in FIG.

Block 2721 may incorporate a circuit (e.g., circuit 20]0 and 2020) f, as shown in FIG. horizontal as well as vertical low-pass filtering, such as by combining The standard resolution low frequency luminance signal is sent to the delay circuit 276.
0 becomes one input to the adder circuit 2750.

A differential circuit 2722 is used to subtract the standard resolution low frequency brightness from the high frequency brightness, and the result is low-frequency waveformed to obtain a brightness signal in the frequency range represented by frequency band 2602 in FIG. [For ease of explanation, the equalization delay circuit is omitted as described in some of the current embodiments. According to a feature of this embodiment, a circuit is provided to repeat this part of the luminance information for two successive frames. In particular, a nature converter 2724 di-notes the signals, which are connected to a frame delay circuit 2728 and a summing circuit 2729 that receives the outputs of both the nature converter and the frame delay circuit. Therefore, the output of adder circuit 2729 is the average of two successive frames. This signal is then connected to frame storage circuit 2725 and one input of switch 2726. switch 27
Another input of 26 is the direct output of adder circuit 2729. The paired two frame count count (which may also be transmitted as described below) is coupled to frame storage circuit 2725 and switch 2726 so that the first of the pair of frames is output from summation circuit 2729. This frame is stored in the frame storage circuit 2725 and output from the switch 2726. During the second frame of the successive pair of frames, the frame storage circuit 2725 is operated to read the frame just stored (i.e., the first frame of the pair) and the switch passes the output of the frame storage circuit. It works like this. Stated another way, during the first frame of a pair of successive frames, frame storage circuit 2725 is in a read mode;
Switch 2726 is operative to pass the output directly received from circuit 2729, while the received sequence of frames (within the frequency band described above) is
．． 2, 3, 4, 5.6..., the output of the switch 2726 is frame 1, 1, 3° 3.5, 5
．． It becomes... The output of switch 2726 is D/A
It is connected to converter 2727 , the output of which is in turn connected to another input of summing circuit 2750 .

The R-Y high-resolution signal is converted into a low-frequency P wave (block 2731
) can be applied to undergo both horizontal and vertical filtering as described above. The r-wave signal is coupled to an A/D converter 2734 and the averaged R-
a frame delay circuit 2738 arranged and operative like the corresponding circuits 2728, 2729, 2725, 2726 of the luminance processing to convey successive frames of Y information;
, an adder circuit 2739, a frame storage circuit 2735, and a switch 2736. The output of switch 2736 is connected to D/A converter 2737, whose output is 9
This is one input to the 00 modulator 2755. Another input to the 90° modulator 2755 is the modified standard resolution B
-Y is the output of the processing channel. This channel is modified R
- operates in a similar manner to its counterpart in the Y processing channel;
Low-pass filter 2741, converter 2744, frame delay circuit 2748, addition circuit 2749, frame storage circuit 2745, switch 2746, and D/A converter 274
Contains 7. However, in the case of B2Y signals, lower resolution is required, as mentioned earlier.

This signal is then waved to a much lower frequency (again, both horizontally and vertically). After the modified standard resolution color difference signal is 90° modulated onto the 3.58 MH7 color subcarrier, the result is another input to the summing circuit 2750. It will be understood that in order to convey successive frames, alternative means can be provided before and after combining information components. The output of summing circuit 2750 can be stored and/or transmitted. Standard resolution memory (as in FIG. 22) can be used if desired.

FIG. 28 shows a block diagram of the high resolution processing portion of the encoder of this embodiment. This encoder is used to obtain the signal represented by frequency band 2603 in FIG. The high resolution luminance signal is connected to a high pass filter 28J1 to remove low frequency components that would be redundant for the portion of information transmitted on the standard resolution channel (eg, in the embodiments described above). Again, for both luminance as well as color difference signals, filtering can be performed not only horizontally but also vertically. The P-wave signal is sent to an A/D converter 28] 3, and then to a circuit 2 that operates to average the high-resolution video information of four consecutive frames.
814. This means that in this embodiment this information is stored at conventional frame rates (i.e. 75 frames/
The averaging of the video information at each pixel over four consecutive frames can be successfully used to obtain the signal to be stored and transmitted. . The circuit 2814 includes three frame delay circuits 2815, 2816 and 2817, and not only the outputs of the three frame delay circuits but also
The input to the first frame delay circuit is also connected to a summing circuit 2818 to average each pixel over four consecutive frames.

The output of circuit 2814 is a high resolution luminance memory 2819;
It is then connected to an associated D/A converter 2819A, which operates in a manner similar to the memory described in previous embodiments to produce encoded high resolution information for transmission at a lower frame update rate.

The high resolution color difference signal R-Y is sent to the filter circuit 2821
This is due to the same reasons mentioned regarding brightness filtering. In this case, however, since high-definition color information cannot be perceived with as high a resolution as luminance, the circuit 2822 is configured to operate in both the horizontal and vertical directions to obtain a frame having, for example, a total of 525 scan lines. Low pass filtered. Thus, filters 2821 and 2822 taken together provide bandpass filter operation. The resulting signal is sent to the leopard converter 28
23 and then connected to circuit 2824. circuit 2824
operates in a manner similar to its above-described counterpart (2814), and includes a high resolution R-Y memory 2829 and associated D/
The four frames are averaged before connecting to A converter 2829A.

The high resolution B-Y signal processing channel is similar to the R-Y signal processing just described and includes blocks 2831-2839A that operate in a similar manner to their counterparts 2821-2829A. However, in the case of B-Y signal processing, as mentioned above, the required maximum resolution is smaller for R-Y signal information. Therefore, the high-frequency F wave in this case should be performed at a lower frequency and scanning linear velocity.

A memory that clocks in and clocks out at the desired rate can be provided as described in the previous embodiments. Instead of continuously transmitting each component of the lower rate high resolution information, each such component may vary in time base and be transmitted only during a portion of a cycle.

Delay circuit 2760 (along with equalization delay circuit - not shown) in the low resolution luminance channel operates like delay circuit 2250 (FIG. 22) to control color and detail luminance with respect to low resolution luminance (FIG. 27). By effectively accelerating the high resolution portion of the image in the channel, the slow build-up of high resolution information in the final displayed image is maximally masked. A subsequent delay circuit 2790 operates after addition of the modified standard definition signals and also delays these signals with respect to the high resolution channels for the same purpose. This delay, which in this case is preferably every frame period, serves to center the temporal transients of the low resolution information with respect to the frame averaged high resolution information.

Referring to FIG. 29, a block diagram of an implementation of a decoder for reproducing encoded color and luminance detail components is shown. These signal components are, for example,
Represented by a signal in frequency band 2602 in FIG.
This is encoded using the circuit shown in FIG. "
Not only sophisticated standard-definition receivers, but also high-resolution receivers can have such decoders. The received (-?) modified standard resolution signal is subjected to low frequency F waves by a filter 2911 and high frequency waves by a filter 29]2 to separate upper and lower components of -1z (2.5 M) in this embodiment. The output of the high-pass filter 2912 is a one-frame delay circuit 29]3 and a differential ][ ]1 path 292
1 positive input terminal, is added to one input terminal of adder circuit 2922. The output of the one-frame delay circuit 2913 is connected to another input terminal of the adder circuit 2922 and the negative input terminal of the differential amplifier 292. The output of summing circuit 2922 becomes one input of another summing circuit 2924, which receives as its other input the output of low-pass filter 29]. The output of differential circuit 2921 is connected to a 90° modulator 2923 which also receives a conventionally generated color subcarrier.

Operation 2. Successive identical frames of color and detail luminance video information in frequency band 2602 are reproduced by adding and subtracting successive frames to separate the color difference signal from the standard resolution detail signal. In particular, since the phase of the color subcarrier is reversed between successive pairs of identical frames, the addition of successive frames involves adding the color signal out of phase with itself;
This leaves behind the standard resolution luminance detail signal.

This latter signal can be added to the low frequency luminance by a summing circuit 2924 to obtain standard resolution luminance.

Also, by subtracting consecutive identical frames, standard resolution luminance details are canceled and out-of-phase color signals are added, resulting in a clean reproduction of the color signal. Transmitted frame count (1 or 2) H1
It can be used to identify each successive pair of the same U-frame.

Alternatively, consecutive identical frames can also be detected by other means at the receiver using the color subcarrier phase for synchronization.1 For high resolution receivers, the low and high resolution signals are Techniques similar to those described in connection with FIG. 23 can be used and combined to reproduce high resolution information for display on a display.

If diagonal sampling were used, a 7j corresponding alternating scan line offset would be used in the receiver display.

Further variations are within the scope and spirit of the invention.
Those familiar with this type of technology will recognize that this is possible. For example, if required by broadcast standards, a "high resolution signal canceler" could be available in high definition receivers when low resolution broadcasts are received. 1. While the double interlaced scanning method has been explained, it should be understood that alternative methods such as triple interlaced scanning can be used. Additionally, regarding -, the standard frame rate is the NTS used in the United States.
It is possible to use speeds other than the C method speed of 30 frames/second,
The invention is applicable to any type of video system. Finally, it should be noted that integrated circuit technology can be employed to implement some or all of the encoders and decoders, as is the case with home receivers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a compatible high-definition TV system according to one embodiment of the present invention that is compatible with existing systems and can be used to implement the method of the present invention. FIG. 2 is a diagram of scan lines and pixel groups of a high resolution desotalized frame of the described implementation. FIG. 3 is a block diagram of the encoding circuit of FIG. 1. FIG. 4 is a block diagram of a portion of the encoder storage subsystem showing the input controls and their addressing. FIG. 5 is a block diagram of a portion of the encoder storage subsystem showing the output control and its addressing. FIG. 6 is a block diagram of a sum signal generating section of a part of the sum signal and difference signal generating circuit of the encoder. FIG. 7 is a system diagram for controlling the ROM sequencer of the sum signal generating circuit of the encoder. FIG. 8 is a block diagram of a difference signal generating section in the sum signal and difference signal generating circuit of the encoder. FIG. 9 is a system diagram for controlling the ROM sequencer of the encoder difference signal generating circuit. FIG. 10 is a block diagram of the decoding circuit of FIG. 1. FIG. 11 is a block diagram of a portion of the decoder storage subsystem showing the input controls and their addressing. FIG. 12 is a block diagram of a portion of the decoder storage subsystem showing the output control and its addressing. FIG. 13 is a block diagram of the pixel value generation circuit of the decoder. FIG. 14 is a system diagram for controlling the ROM sequencer of the pixel value generation circuit of the decoder. FIG. 15 shows the eye's steady state contrast sensitivity curve. FIG. 16 is a diagram of the relative sensitivity of the eye to the visibility grid as a function of the duration of grid presentation. FIG. 17 shows the curves of an isoluminant chromaticity grid as a function of duration. FIG. 18 shows a diagram of the relative eye response to masking. FIG. 19 is a diagram illustrating the relative response to masking regarding a chromaticity grid of equal luminance. FIG. 20 is a block diagram of the luminance processing portion of the encoding circuit, in accordance with another embodiment of the invention. FIG. 21 shows a block diagram of the chrominance processing portion of the encoding circuit according to another embodiment of the same type. FIG. 22 shows a block diagram of the storage and output circuitry of one embodiment of the above type of the invention. FIG. 23 is a block diagram of a decoding circuit according to the above type of the present invention. FIG. 24 shows Y oriented in cardinal and diagonal directions.
, R-Y, and B-Y gratings. FIG. 25 is a polar diagram of the limited resolution response of various systems, including 25A, 25B, 25C, and 25D. FIG. 26 illustrates the frequency vector of the proposed system. 27 and 28 show, according to another embodiment of the invention,
FIG. 2 is a block diagram of an encoder. FIG. 29 is a block diagram of a decoder regarding decoded signals encoded by the encoders of FIGS. 27 and 28. Patent Applicant: New York Institute of Technology, Patent Application Agent, Patent Attorney, Megumi Yamamoto - v4 Actually 4 No 0 People 1 pKJ - Tsuyabe 5 Iguchi - 1 - ~ -0 effect"affected 8v"I-\ UIN Beni Shichimikyo Procedural Amendment (Spontaneous) May 9, 1985 Commissioner of the Patent Office Shiga Gakudon 1 Display of Case 1985 Patent Application No. 71281 2 Title of Invention Video signal encoding/decoding system 3. Relationship with the case of the person making the amendment Name of the patent applicant: New York Institute of Technology 4, Agent 5, Column for the representative of the patent applicant in the application subject to the amendment, power of attorney and drawings 6, Contents of the amendment (1) Submit the application for correction as attached. (2) Submit the power of attorney and translation as attached.

Claims (1)

[Claims] (1) An apparatus characterized in that it encodes and decodes a video signal representing an image, comprising: A) An encoder comprising: said video signal leading to a low frequency luminance signal; means responsive to said video signal to derive a combined chrominance and detail luminance signal; means for producing an output frame of said low frequency luminance signal at a fast frame update rate; said combined chrominance and detail luminance signal at a slow frame update rate. A means of producing an output frame. and B) a decoder comprising: a combined chrominance and detail luminance signal at the slow frame update rate for separating the combined signal and producing separated chrominance and detail luminance signals at the fast frame update rate; means responsive to said frame of signals;
and means responsive to the low frequency luminance signal and the separate detail luminance signal for producing a composite luminance signal. (2) said means for producing output frames of said combined chrominance and detail luminance signals at a slow frame update rate; 2. A device according to claim 1, comprising means for producing a frame of chrominance signals carried out on an inverted carrier wave. 3. The apparatus of claim 1, wherein the fast frame update rate is 30 frames per second and the slow frame update rate is 15 frames per second. (4) The apparatus according to claim 2, wherein the fast frame update rate is 30 frames/second and the slow frame update rate is 15 frames/second. (5) the means for producing an output frame of said combined chrominance and detail luminance signal at a slow frame update rate further averages successive frames of said chrominance signal and said detail luminance signal before each repetition thereof; Device according to claim 2, characterized in that it consists of means. (6) The low frequency luminance signal has a bandwidth of about 2.5 Ml-1z, and the combined chrominance and detail luminance signal has a bandwidth of about 0.7Iz. Apparatus according to paragraph 1. (7) The low frequency luminance signal has a bandwidth of about 2.5 MHz, and the combined chrominance and detail luminance signal has a bandwidth of about 0.7 MHz. The device according to item 4. (8) The means in the decoder for separating the combined signal includes means for adding or subtracting repeated frames of the combined signal. Device. (9) The means in the decoder for separating the combined signal includes means for adding or subtracting the combined signal (3 repeated frames). 00 further comprising means in said encoder responsive to said video signal for guiding a high resolution luminance signal and a chrominance signal; 1. The apparatus according to claim 1, characterized in that the apparatus comprises means in said encoder for producing a frame at a frame update rate of: 01) encoding a video signal representing an image, comprising: 2. Deriving a low frequency luminance signal from the video signal; deriving a combined signal of chrominance and detail luminance from the video signal; creating an output frame of the low frequency luminance signal at a high frame update rate. Step: producing an output frame of the chrominance and detail luminance signals at a slow frame update rate. 0. The method of claim 11, further comprising the step of transmitting an output frame. θ1 The step of producing an output frame of the chrominance and detail luminance combination signal at a slow frame update rate,
Claims characterized in that it consists of creating frames of a detail luminance signal that repeats each once, and a chrominance signal that repeats each once, but with carrier waves that are inverted in phase between repeated frames. The method according to paragraph 11. 04. At a slow frame update rate, the step of producing an output frame of the combined chrominance and detail luminance signal comprises repeating once each frame of the detail luminance signal and repeating once each but with a phase-inverted carrier between each repeated frame. 13. A method as claimed in claim 12, characterized in that it consists of creating a frame of chrominance signals to be performed. Claim (5), wherein the high frame update rate is 30 frames/second and the low frame update rate is 15 frames/second. Method. (111G) The method of claim 14, wherein the fast frame update rate is 30 frames/second and the slow frame update rate is 15 frames/second. said step of producing an output frame of said combined chrominance and detail luminance signal at a slow frame update rate;
15. The method of claim 14, further comprising averaging successive frames of said chrominance signal and said detail luminance signal before each repetition. The patent characterized in that the low frequency luminance signal has a bandwidth of about 2.5 h/H-tz, and the combined chrominance and detail luminance signal has a bandwidth of about 0.7 MHz. The method according to claim 14. 0. The method of claim 1 further comprising the steps of deriving high resolution luminance and chrominance signals, and producing output frames of each of the resolution luminance and chrominance signals at the lowest frame update rate.
The method described in Section 1. (6) (a) further comprising two steps of deriving both high-resolution luminance and chrominance signals and producing output frames of both signals at the lowest frame update rate. The method described in. 01) Deriving a low frequency luminance signal from the video signal, deriving a combined signal of chrominance and detail brightness from the video signal, creating an output frame of the low frequency brightness signal at a high frame update rate, and outputting the combined signal of the chrominance and detail brightness. A decoder for use in decoding a video signal representing an image encoded by producing frames at said slow frame update rate, characterized in that it comprises means for: separating said combined signal; means for producing separated chrominance signals and detail luminance at said fast frame update rate in response to two frames of said combined chrominance and detail luminance signal at said slow frame update rate; for producing a composite luminance signal; , means responsive to the low frequency luminance signal and the separated detail luminance signal. (a) The decoder according to claim 21, wherein the high-speed frame update rate is 30 frames/second, and the low-speed frame update rate is 15 frames/second. (c) The output frame of the combined signal of chrominance and detail brightness at a slow frame update rate is carried by a frame of the detail brightness signal which is repeated once each, and a carrier wave which is repeated once each but whose phase is inverted between the repeated frames. 22. A decoder as claimed in claim 21, characterized in that the decoder includes means for adding and subtracting repeated frames of said combined signal. ←→ The output frames of the combined chrominance and detail luminance signal at a slow frame update rate include a frame of the detail luminance signal that repeats once each, and a chrominance signal that repeats each one time but is carried on a carrier wave whose phase is inverted between the repeated frames. and the decoder adds repeated frames of the combined signal;
23. The decoder according to claim 22, further comprising means for subtracting. (c) The decoder according to claim 21, further comprising means for displaying the reproduced chrominance signal and composite luminance signal. (c) The decoder according to claim 23, further comprising means for displaying the reproduced chrominance signal and composite luminance signal. 25. A decoder as claimed in claim 24, further comprising means for displaying the reproduced chrominance signal and the composite luminance signal. (c) A method characterized by encoding, transmitting, receiving, and decoding a video signal representing an image, comprising the following steps; a step of deriving a low frequency luminance signal from the video signal; from the video signal, Deriving a combined signal of chrominance and detail brightness; Creating an output frame of the low frequency brightness signal at a high frame update rate; (9) Creating an output frame of the combined chrominance and detail brightness signal at a slow frame update rate; transmitting the output frames; receiving the output frames; separating the combined signal and producing separated chrominance and detail luminance signals at the fast frame update rate; and low frequency luminance. generating a composite luminance signal from the signal and the separated detail luminance signal; The above step of producing output frames of the combined chrominance and detail luminance signal at a slow frame update rate includes repeating each frame of the detail luminance signal once, and repeating each frame of the detail luminance signal once, but with the phase reversed between the repeated frames. 29. A method according to claim 28, characterized in that it consists of creating a frame of chrominance signals transmitted on a carrier wave. 29. The method of claim 28, wherein: (1) the fast frame update rate is 30 frames/second and the slow frame update rate is 15 frames/second. (10) 0p The method of claim 29, wherein the fast frame update rate is 30 frames/second and the slow frame update rate is 15 frames/second. 02 The step of producing an output frame of the combined chrominance and detail luminance signal at a slow frame update rate further comprises averaging successive frames of the chrominance signal and the detail luminance signal before each repetition. 30. A method according to claim 29, characterized in that: 0'3 The low frequency luminance signal has a bandwidth of about 2.5 MHz, and the combined chrominance and detail luminance signal has a bandwidth of about 0.7 MJ (z). 29. The method of claim 29. (b) The step of separating the combined signal includes adding or subtracting repeated frames of the combined signal. The method according to claim 09, further comprising: deriving high resolution luminance and chrominance signals; producing output frames of the high resolution luminance and chrominance signals at a minimum frame update rate; and generating output frames of the high resolution luminance and chrominance signals. Claim 1, comprising the steps of producing at a minimum frame update rate; transmitting frames of high-resolution luminance and chrominance signals; and receiving frames of high-resolution luminance and chrominance signals. The method described in Section 29.