JPS6022778B2 - Response synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a response synchronization method in a data processing device.

Conventionally, a data response sending operation between a data requesting device and an acceptance processing device is generally performed as follows.

This is carried out by sending data to the data requesting device on a unilateral condition of the receiving processing device, or by sending a advance notice signal from the receiving processing device to the data requesting device indicating that preparations for sending data are completed. .

Therefore, if the data requesting device is not independently provided with a request unit including a request control circuit and a data sending buffer, and a receiving unit including an acceptance control circuit and a data receiving buffer, request sending and response processing are required. can't do it. As a result, the request sending operation from the requesting device in response to the data response sending signal notice signal sent from the receiving processing device to the data requesting device is prohibited, and the response processing to the receiving processing device is processed with priority. There is. As a result, the request cycle time of the data requesting device is extended, which has the disadvantage of affecting the data transfer rate. SUMMARY OF THE INVENTION It is an object of the present invention to provide a response synchronization method which solves the above-mentioned drawbacks and achieves a desired data transfer rate without delaying the request cycle time with a simple configuration.

The system of the present invention includes a data requesting device that operates in synchronization with a first clock signal, and a second data requesting device that operates in synchronization with the first clock signal and has a period twice that of the first clock signal.
In the response synchronization method, the data request device sends the request in synchronization with the first clock signal, and the data request device sends the request in synchronization with the first clock signal. and a storage means for storing the logical value of the second clock signal at the time of receiving the request from the data requesting device, arithmetic means for performing a predetermined operation on the logical value of the clock signal and the logical value of the second clock signal at the time of data response processing; and a determination for determining the data response timing to the data requesting device based on the arithmetic result of the arithmetic means. It is characterized by having means.

Next, the present invention will be explained in detail with reference to the drawings.

A first embodiment of the present invention shown in FIG.
and a data request device 2. The reception processing device 1 includes an admission control circuit 3, a memory circuit 4, a timing management circuit 5, and a response control circuit 6. The data requesting device 2 also includes a request sending control circuit 7. Next, the operation of the embodiment of the present invention will be explained in detail.

A first timing signal and a second timing signal described below refer to a first clock signal and a second clock signal.

The request sending control circuit 7 of the data requesting device 2 receives the first timing signal 14 from the timing management circuit 5, and sends the request signal 8 to the processing device 1 at the first timing 14 if the request sending condition is satisfied. The request sending control circuit 7
It is determined whether the request has been accepted based on the output signal 1 from the reception control circuit 3 when the request signal 8 is sent. The reception control circuit 3 receives the request signal 8 and sends out the request signal 9 when the conditions are met. Furthermore, when the request permission signal is given in the request permission state, the reception control circuit determines that the request signal 9 has been accepted, and sets the reception success signal 18 to a logical value of "1". A first timing signal 1 as shown in FIG.
The value of the second timing signal 19 having a period twice 4 and the signal 17 indicating receipt of a request from the data requesting device are held in the memory circuit 4 in response to the success signal 18. The response control circuit 6 is activated by the response signal 13 from the memory control device 100. The response control circuit 6 receives and synchronizes with the response signal 13, and outputs an output signal 20 consisting of the second timing signal 19 read out from the storage circuit 4 and the request acceptance signal 17, and the current value of the second clock signal. Make a comparison.
When the comparison results match and coincide with the first timing 14, a response signal 16 is generated to the data requesting device 2. In this way, by using the response method of the present invention, it becomes necessary to provide separate buffers for requests/acceptance control circuit requests/acceptance data on the data requesting device side, and it is also necessary to provide an interface such as a data sending notice signal. Don't say,
This method is effective in satisfying a desired data transfer rate with simple hardware without delaying the requested cycle time.

Next, an embodiment of the response control circuit 6 that controls the reception processing apparatus, particularly in a response synchronization method, will be described in detail with reference to FIG.

The response control circuit 6 shown in FIG. 2 includes a synchronization circuit 23 that receives the response signal 13 from the memory control device 100 shown in FIG.
, the response signal 68 of the response control circuit 6 and the synchronization circuit 2
3 to write address 5 in response to data confirmation signal 49.
Address control circuit 24 outputs 0 and read address 56, request acceptance valid which is set when the write address 50 from this address control circuit 24 is logic "0" and the synchronization signal 48 and request acceptance display signal 46 are given. Similarly, when the write address 60 of the flip-flop 25 is logic "1", the synchronization signal 48 and the request acceptance indication signal 46 are output.
A flip-flop 26 that holds the second timing signal 52 when the flip-flop 25 is set; a second timing signal 52 when the flip-flop 27 is set; A flip flop holding signal 54.

28, these flip-flop groups 26 and 28
An exclusive OR circuit 41 of the delayed second timing signal 66 generated in response to the output of the fixed logical value "1" and the second timing signal 19, and the outputs of the flip-flop groups 25 and 27. The response valid signal 65 generated based on the output 67 of the exclusive OR circuit 41 and the first
an AND circuit 42 that performs logical product with the timing signal 14 of The circuit is comprised of NAND circuit groups 37 and 38 which generate reset signals 69 and 70 in response to the input address 56 of the flip-flops 25-28. Memory circuit 4
is composed of a memory circuit 400, an output address register 22, and a write address register 21.

Next, the operation of the response control circuit 6 will be explained in detail with reference to FIG.

The reception success signal 18 of the reception control circuit 3 puts the storage circuit 400 into a writable state and counts up the address in the write address register 21 for the storage circuit 400'.

Output signal 44 is used as a write address for storage circuit 400. Request acceptance display signal 46 of storage circuit 400 is applied to AND circuits 29 and 31, and second timing signal 47 is applied to AND circuits 30 and 32.
The response signal 13 is synchronized by a synchronization circuit 23 to generate a synchronization signal 48 and a data confirmation signal 49. Synchronization signal 48 is supplied to AND circuits 29 and 31, and data confirmation signal 49 is coupled to write initiation address control circuit 24 and supplied to read address register 22 of storage circuit 400 as an update signal. The write address 5 from address control circuit 24 is applied to AND circuits 29 and 31. The output signals 51 and 53 of the AND circuits 29 and 31 are the set signals of the request acceptance valid flip-flops 25 and 27, and the AND circuits 30 and 3.
2 input signals. The second timing signal 52 from the AND circuit 30 is synchronized with the second timing signal 47 from the memory circuit 4 and the flip-flop 26
The second timing signal 54 from the AND circuit 32 is supplied to the second timing signal 47 from the storage circuit 4.
The signal is synchronized and supplied to the flip-flop 28. Output signals 57, 58, 59 of flip-flops 25, 26, 27 and 28 and six-channel NAND circuits 33, 34,
V is supplied to 35 and 36 along with the proposed address 56 from the address control circuit 24, and the output signals 61, 62,
63 and 64 are generated. Output signals 61 and 63 are supplied to NAND circuit 39 to generate response valid signal 65. The output signals 62 and 64 are also input to four NAND circuits to generate a delayed second timing signal 66. This signal 66 and the current second timing signal 19 are supplied to the exclusive OR circuit 41, and when the values match, an output signal 67 with a logical value of "1" is generated. The AND circuit 42 is supplied with the output signal 65 of the NAND circuit 39 and the first timing signal 14, and generates an output signal 68 with a logical value of "1" when the AND condition is satisfied. Output signal 6
8 is sent to an AND circuit 43, which generates a response signal 16 to the data requesting device 2. Here, the operation of the response synchronization method will be similarly explained using FIGS. 1 and 2. The reception control circuit 3 is activated by the request signal 8 from the data request device 2 synchronized with the first timing signal 14 created by the timing management circuit 5, and if the request permission signal 11 is valid, it is determined that the request has been accepted. As a result, an acceptance success signal 18 with a logical value of "1" is generated.

This signal 18 indicates the value of the second timing signal 19 generated by the timing management circuit 5 and the signal 17 indicating that a request from the data requesting device has been accepted at the location indicated by the write address 44 of the output of the write address register 21. The address in the write address register 21 is counted up. Furthermore, when the response signal 13 is supplied to the reception processing device 1, the synchronization circuit 23 shown in FIG. Ru. The synchronization signal 48 is sent to the AND circuit 29 together with the output signal 46 of the memory circuit 4 and the write address 50 from the address control circuit 24.
and 31, and output signals 21 and 53 of logical value "1" are generated. When the write address 50 has a logic value of "0", the condition of the AND circuit 29 is satisfied and an output signal 51 of a logic value of "1" is generated. The output signal 51 sets the request acceptance enable flip-flop 25, and the condition is taken from the second timing signal 47 maintained by the storage circuit 400' and the AND circuit 3, and the stored second timing signal is output. A value of 52 is set in the flip-flop 26. Here, the value of the second timing signal 52 is set to the logical value "1". On the other hand, the data confirmation signal 49 becomes a logical value "1", and the read address register 22 of the memory circuit 4 counts up. Also, the write address 50 of the address control circuit 24 is counted up. The logical address 56 from the address control circuit 24 also becomes a logical value "0". The NAND circuit 33 generates an output signal 61 with a logic value of "0" based on the NAND of the output address 56 and the output signal 57 of the flip-flop 25, and this signal 61 is responded with a logic value of "1" by the NAND circuit 39. A valid signal 65 is generated. Further, the second timing signal 58 stored in the flip-flop 26 and the NAND circuit 34 generate an output signal 62 having a logic value of "0". The output signal 62 with the logic value "0" and the output signal 64 of the AND circuit 36 are NANDed by the NAND circuit 40 and the stored second timing signal 66 with the logic value "1" is obtained.
occurs. This signal 66 is checked to match the current value of the second timing signal 19 by the exclusive OR circuit 41, and when they match, an output signal 67 with a logic value of "1" is generated. This output signal 67 is a signal 6 with a logical value of “1”.
5 and the first timing signal 14 and the AND circuit 42, an output signal 68 having a logic value of "1" is generated. The output signal of logical value “1” is output from the address control circuit 24.
At the same time, the NAND circuit 37 generates a reset signal 69 having a logic value of "0", and as a result, the flip-flops 25 and 26 are reset. Further, a response signal 16 synchronized with the request signal is sent to the data requesting device 2 via an AND circuit 43. The present invention includes a data requesting device that provides a first timing and a second timing, makes a request using the first timing signal, and a processing device that stores the second timing at the time, and has a data requesting device that stores the second timing at the first timing signal. By calculating the value of the current second timing and the current second timing and returning a response signal to the requesting device, the desired data transfer rate can be achieved without delaying the request cycle time. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a response control circuit configuration of the reception processing device shown in FIG. 1, and FIG. FIG. In FIGS. 1 to 3, 1..., reception processing device,
2...Data request device, 3...Reception control circuit, 4...
...Memory circuit, 5...Timing management circuit, 6...
・Response control circuit, 7...Request sending control circuit, 2
1...Write address register, 22...
Issue address register, 23...Synchronization circuit,
24...Write/read address control circuit, 25, 26
, 27, 28...flip flop, 29, 30, 31
, 32, 42, 43...AND circuit, 33, 34, 35
, 36, 37, 38, 39, 40... NAND circuit, 41... Exclusive OR circuit, 100...
-Memory control device. Figure 3: Rarely illustrated younger brother 2

Claims (1)

[Claims] 1 A data requesting device that operates in synchronization with a first clock signal, and a second clock signal that operates in synchronization with the first clock signal and has a period twice that of the first clock signal. In the response synchronization method in which a data response is performed between a device that receives and processes a request from the data request device, the data request device has a request sending means that sends the request in synchronization with a first clock signal. death,
The processing device includes storage means for storing the logical value of the second clock signal at the time of receiving a request from the data requesting device, and processing of the logical value of the second clock signal and data response stored in the storage means. The present invention is characterized by comprising: arithmetic means for performing a predetermined arithmetic operation on the logical value of the second clock signal at a time; and a determining means for determining a data response timing to the data requesting device based on the arithmetic result of the arithmetic grenade. response synchronization method.