JPS6022755B2 - Digital electronic clock display drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display drive circuit for a digital electronic watch, and the present invention relates to a display drive circuit for a digital electronic watch, in which the rate of change in luminance of the shading of the colon during normal operation is the same as the rate of change in the brightness of the shading of the colon during dimming. It is an object of the present invention to provide a display drive circuit that can display the colon in an easy-to-see manner.

Some conventional digital electronic watches are provided with a colon between an hour display element and a minute display element, and are flashed at a cycle of, for example, one second to indicate the operation of the clock.

The colon display method of this watch is to supply a maximum voltage of 0.9 degrees to the terminal of the colon, then reduce the voltage to zero for the next 0.9 seconds, and repeat this alternately to make the terminal blink with a large brightness difference. For this reason, the contrast of blinking is strong and the observer's eyes are easily fatigued.Particularly when used in a car watch, there are disadvantages such as disturbing the driver's attention and causing an accident. Therefore, in order to eliminate the above-mentioned drawbacks, the present applicant
-39902 ``Display drive circuit'' was proposed.

For example, as shown in Figure 2, a resistor R is connected between the colon display signal output terminal 2 of the IHZ provided in the drive circuit 1 and the power supply terminal 3, and the signal input shown in Figure 2A is connected. As shown in the figure, the voltage Voo' lowered by the resistor R and the voltage Voo are alternately applied to the colon 4 in intervals of 0.9 mm, so that the colon 4 is displayed in shading instead of flashing, thereby reducing changes in brightness. was. Now, considering the brightness of the time display element 5 or the colon 4 during daytime and nighttime, when used at night, the same brightness as during the daytime feels dazzling, so it is easier to see if the applied voltage is lowered overall. However, in the case of a crab light display tube digital clock, if the applied pressure is lowered,
The brightness of the time display element 5 at the right end becomes significantly lower than the brightness of the time display element 5 at the left end, or the brightness of each segment of the time display element 5 becomes uneven, which is undesirable. Therefore, at night, for example, if the light display tube is driven intermittently with a relatively high frequency signal of about HZ with a duty ratio of 1'4, and the signal is applied to the colon 4 and the time display element 5, The afterimage effect gives the impression of a substantially darker image, resulting in uniform brightness across the entire display. However, when this method is applied to the circuit shown in FIG. 1, a signal port as shown in FIG. 2 is applied to the colon 4 during dimming. As a result, the luminance during the dark display and the light display appear to be substantially the same, and there is a problem in that the operation of the night time clock cannot be confirmed. The present invention solves the above-mentioned problems, and each embodiment thereof will be described with reference to FIG. 3 and subsequent figures.

The embodiment shown in FIG. 3 is applied to an automobile clock, and the S
is a switch that opens and closes in conjunction with the light switch, and is connected between the input terminal 7 of the drive circuit 6 and the power supply 1B, and is opened when headlights, etc. are not required, such as during the day. . First, when headlights, etc. are not required, and the switch S is open, the signal applied to the colon display signal output terminal 8 of the drive circuit 6 is at a predetermined H level as shown in FIG. This is the IH2 signal A, in which a zero bell and a zero bell are repeated alternately. On the other hand, the signals taken out from the AM display signal output terminal 9 and the PM display signal output terminal 10 of the drive circuit 6 are at the H level in the morning and at the signal terminal which becomes a bell in the afternoon, as shown in the opening and c of the figure. and a signal C that goes to zero in the morning and goes to H level in the afternoon, and these are the segments f and e of the display element of 1 field life digit as shown in FIG. 5 (AM display element f and PM display element e). These are supplied to each of the morning and afternoon and are displayed corresponding to the morning and afternoon, respectively. This signal port and C are diodes D,,
Voltage V at resistor R2 applied via D2. . ', which is added to the signal from the colon display signal output terminal 8, and as shown in FIG.
The next 0.9 sand voltage VDo becomes the alternately repeated first pulse signal D. This signal 2 is supplied to the colon 4, and causes the colon 4 to display shading at a cycle of 1 second. Due to this shading display of the colon 4, as with the digital clock shown in FIG. 1, the viewer's eyes do not get tired compared to the conventional flashing display, and the viewer can drive the car safely. Here, when the switch S is closed at the same time as the headlights are turned on at night, the voltage power supply +B is applied to the input terminal 7 of the drive circuit 6.

As a result, the next 8 kHz rectangular wave pulse with a 0.9-segment duty ratio of 1/4 is alternately repeated at the colon display signal output terminal 8 with a zero bell for 0.5 seconds as shown in Figure 4 A'. Signal A' is taken out. Similarly, the output terminal 9 also has a signal port ', which produces a class HZ rectangular wave pulse in the morning and a zero bell in the afternoon, as shown in the figure's opening. A signal C' is taken out which becomes a rectangular wave pulse of pink HZ with a duty ratio of 1'4 in the afternoon with a zero bell in the morning as shown in C'. The drive circuit 6 is configured such that when a voltage of 10 B is applied to its input terminal 7, an internal logic circuit is operated, and each of the terminals 8 to 10' outputs the signals as described above. . The signal ports ' and c' are supplied to the AM display element f and the PM display element e, respectively.
These display elements f and e are displayed in an intermittent manner using the frequency of the box HZ corresponding to morning and afternoon, respectively. During this time, due to the afterimage effect of the song display, it appears to the eye that the brightness has become substantially lower than in the case of Figure 4 (a) and (c). On the other hand, the signal ports ' and C' are applied together and become a voltage Voo' at the resistor R2, and the colon display signal output terminal 8
is added to the signal I' of 0, as shown in FIG.
．． A rectangular wave pulse of departure Z with a peak value Voo' for 9 seconds,
The next rectangular wave pulse of the Tsumugi HZ having the sand wave height value Voo of 0.9 becomes the second wave pulse signal 2' which is alternately repeated.

This signal 2' is supplied to the colon 4, and causes the colon 4 to display shading at a cycle of 1 second. At this time, the colon 4 is actually displayed blinking intermittently at the frequency of the lizard HZ, but as in the case of the AM display element f and the PM display element e, it is essentially perceived as a gray scale display due to the afterimage effect of the eye. The image appears darker than the case shown in FIG. 4, 2. Moreover, instead of lowering the voltage and lowering the brightness, the normal time is 1'
4. Since this is a dimming display that utilizes the residual effect of the ocular eye, the rate of change in the brightness of the shading in Colon 4 is the same as the rate of change in brightness of the shading in normal times, as shown in Figure 4. You can check the operation of the clock with the same feeling. In addition, the third
In the embodiment shown in the figure, when it is not necessary to use the AM display element f and the PM display element e, the diodes D, , D2
is not necessary, and terminals 9 and 10 may be directly connected.

In another embodiment shown in FIG. 6, the same components as those in FIG. 3 are given the same reference numerals, and their explanations will be omitted.

First, when the switch S is open, the signal A shown in FIG. An H level signal is always applied to either one of the output terminals 11 and 12 of the FET of the drive circuit 6. Signals from terminals 11 and 12 are connected to diodes D3 and D
4 becomes a signal E shown in the tree of FIG. 4, and becomes a voltage Voo' signal at the resistor R3. This signal is added to signal A from terminal 8, and as in the case of the embodiment shown in FIG. 3, becomes signal 2 shown in FIG. Displays shading in cycles. Note that the drive circuit 6 is actually provided with a number of FETs corresponding to the segments of the time display element 5.
The configuration is such that each segment is displayed over time using the output signal of the ET. This embodiment uses FETs to display segments a and b of the 1 o'clock digit of the time display element 5. Further, the diodes D3 and D4 are provided so that one segment display signal does not cause the other segment to be displayed incorrectly. When the nighttime switch S is closed, a voltage of 1 B is applied to the input terminal 7 of the drive circuit 6, and a signal A' as shown in FIG. 4A' is applied to the terminal 8.
A rectangular wave pulse of HZ similar to the signal ports ' and c' is taken out from either terminal 11 or 12, and a signal as shown in Fig. 4 (not shown) is taken out at the connection point between diodes D3 and D4. Ho' is taken out.

As a result, the colon 4 is supplied with a signal 2' as shown in Fig. 4 2' in the same way as in the embodiment shown in Fig. 3, and gradation is displayed with the same luminance change rate as the normal gradation luminance change rate. . It should be noted that each segment of the display element 5 is displayed in a dimmed state by the rectangular wave pulse of the square HZ from the FET of the drive circuit 6. Note that in the embodiment shown in FIG.
In order to obtain , the first or tenth digit of the element 5 may be used, and the segments may be b and c, c and d, etc.

As described above, the display drive circuit of the digital electronic timepiece according to the present invention obtains the first pulse signal, which has a frequency corresponding to the display period of the colon and has a DC component superimposed thereon, from the display output signal of the time drive circuit, and calculates the time. When the brightness of the display element and the brightness of the colon are reduced, level values corresponding to the H level period and the L level period of the first pulse signal are determined from the display output signal. obtaining a second pulse signal corresponding to the period and having a duty ratio smaller than the duty ratio of the first pulse signal and a frequency larger than the frequency of the first pulse signal;
Since the pulse signal is selectively applied to the colon and the display is displayed with different gradations and luminances according to the first and second pulse signals, the luminance is lower than the gradation display of the subordinate colon. As a result, the viewer's eyes will not get tired, and if the surroundings are dark, the brightness will be lowered (attenuated) so that it will not be perceived as dazzling. Since the rate of change in brightness is the same as the rate of change in brightness in normal conditions, it is easier to determine.
Furthermore, when dimming the light, the applied voltage is not lowered overall, but the afterimage effect is used to display the signal with a small duty ratio, so especially when used in a crab light display tube digital clock, the right edge It has the advantage that there is no difference in brightness between a certain time display element and the one on the left end, there is no brightness unevenness in the segment, and there is no deterioration in the image quality of the colon in particular.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a display driving circuit previously proposed by the present applicant, Fig. 2 A is a display signal waveform diagram obtained by the circuit shown in Fig. 1, and Fig. 3 is a digital electronic circuit according to the present invention. Circuit diagram of the first embodiment of the clock display drive circuit, Fig. 4 A to Thu,
A' to H' are display signal waveform diagrams obtained by the circuit shown in FIG. 3 and the circuit shown in FIG. 6, FIG. 5 is a plan view of a time display element, and FIG. FIG. 3 is a circuit diagram of a second embodiment. Tortoise: Colon, 5: Time display element,
6...Drive circuit, 7...Input terminal, 8-12.
...Display signal output terminal, S...Switch, D, ~
D4...Diode, R2, R3...Resistance, a~g...
segment. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 4

Claims (1)

[Claims] 1. A first pulse signal having a frequency corresponding to the display period of the colon and on which a DC component is superimposed is obtained from the display output signal of the time drive circuit, and the luminance of the time display element and the luminance of the colon are determined. At the time of dimming, level values corresponding to the H level period and the L level period of the first pulse signal are set from the display output signal in correspondence to the H level period and the L level period. obtaining a second pulse signal having a duty ratio smaller than the duty ratio of the first pulse signal and a frequency larger than the frequency of the first pulse signal;
1. A display drive circuit for a digital electronic timepiece, characterized in that the display driving circuit for a digital electronic timepiece is configured to selectively apply a pulse signal of 1 to the colon to display a display with mutually different gradation and brightness according to each of the first and second pulse signals. 2 Obtain a first pulse signal with a frequency corresponding to the colon display period and a DC component superimposed from the colon display output signal and the AM/PM display output signal of the time drive circuit, and calculate the luminance of the time display element and the colon. When the brightness is dimmed, level values corresponding to the levels of the H level period and the L level period of the first pulse signal are calculated from the colon display output signal and the AM/PM display output signal, respectively. obtaining a second pulse signal corresponding to the L level period and having a duty ratio smaller than the duty ratio of the first pulse signal and a frequency larger than the frequency of the first pulse signal;
A digital electronic timepiece characterized in that the first or second pulse signal is selectively applied to the colon so that the colon is displayed with different gradations and brightness depending on the first or second pulse signal, respectively. display drive circuit. 3 Obtain a first pulse signal with a frequency corresponding to the display period of the colon and a DC component superimposed thereon from the colon display output signal of the time drive circuit and the time display element segment display output signal, and obtain the first pulse signal with a DC component superimposed thereon, and determine the luminance of the time display element and the colon. When the brightness of
From the colon display output signal and the segment display output signal, level values corresponding to the level of the H level period and the level of the L level period of the first pulse signal are assigned to the H level period and the L level period. Obtain a second pulse signal with a duty ratio smaller than the duty ratio of the first pulse signal and a frequency larger than the frequency of the first pulse signal, and pass the first or second pulse signal to the colon. selectively applying the segment display output signal to the segment of the time display element to display the segment display output signal in different shades of luminance depending on the first or second pulse signal, respectively, and applying the segment display output signal to the segment of the time display element to display the segment display output signal in accordance with the segment display output signal. A display drive circuit for a digital electronic watch, characterized in that it is configured to display a display.