JPS60224275A - Manufacture of insulating-substrate-mis type field effect transistor - Google Patents

Abstract

PURPOSE:To prevent short circuits between a gate electrode and source and drain electrodes, by implanting non-dopant ions, mixing the interface between a high-melting-point metal and silicon, silicifying the silicon at a part, where the high-melting-point metal is contacted, by hot annealing, and the like. CONSTITUTION:On an insulating transparent substrate 1, an island shaped silicon transistor region 2, a gate electrode 4 and a source and drain diffused layer are formed. Then a negative type photoresist 41 is attached on the entire surface. The back surface is exposed to light and developed. A high-melting-point metal 21 is attached on the upper surface of the device. The resist 41 is exfoliated. Then, non-dopant ions are implanted, and the interface between the high-melting point metal 21 and the silicon parts 2 and 4 is mixed. The silicon at the part, where the high-melting-point metal 21 and the silicon parts 2 and 4 are contacted, and made to be silicides 32 and 31 by hot annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to MI 8 (Metal-Insulate
Regarding the manufacturing method of (r-Be-miconductor) type field effect transistor (hereinafter referred to as MI8 FET), in particular, we have developed a method to reduce resistance by forming silicide on the source, drain, and gate electrodes of MI8' PET using an insulating transparent substrate. Regarding how to.

(Prior art and its problems) Conventional high-performance MI8 FETs generally use polysilicon as the gate electrode material because the gate electrode and source/drain electrodes can be formed in a self-aligned manner. In this structure, the resistance of the source, drain, and gate electrodes poses a problem for the dynamics and characteristics of the device. In general process steps, the sheet resistance of the source and drain electrodes is 10-odd Ω/hole for n+ and 1000 for p-10.
/ before and after the mouth, polysilicon is added with n+ ~ (9) Ω / mouth, p
+ is about 200-300Ω/mouth. One way to lower this resistance is to silicide each electrode to lower the resistance. Regarding silicidation, in order to perform this uniformly, after depositing the high melting point metal,
The ITM method (1
ion implantation through m
Et alf i 1m method) is good. I'I'M
For example, B, Nagasawa et al, @A 8
elf-Aligred Mo-8i1icido
Formation JJAP Vol 22. AI
, Jan, 1983 PPL57-L59.

In this method, for example, titanium (T) is used on silicon (8i).
i) was deposited to a thickness of approximately 400 mm, and 8i ions were deposited at F3MeV.
5X10 CIIl iono-injection at approximately 550°C for 20
Heat treatment for about 10 minutes to form a silicide.
A sheet resistance of about 0.070°C is obtained, which is then reduced to about 3Ω/hole by etching away the remaining titanium and performing heat treatment at about 800°C.

In this ITM method, if the sidewall of the gate polysilicon is rubbed with a nearly vertical pot, there will be no interfacial mixing due to implanted ions even if there is metal, and it is difficult to turn into silicide with low-temperature heat treatment, so the gate electrode and source/drain electrode are self-aligned. It is characterized by its ability to be silicided.

However, when interfacial mixing is performed with relatively light ions such as 8i ions and Ar ions, sufficient mixing cannot be achieved and heat treatment at a somewhat high temperature is required. Therefore, silicidation also occurs on the side walls of the gate polygon 8i, causing a short circuit between the gate electrode, source, and drain. To prevent this, an insulator such as an oxide film or a nitride film is formed on the gate sidewalls.

The MI8 FET, which uses a semiconductor on an insulating substrate, has characteristics such as low junction capacitance, low wiring capacitance, and complete isolation between each element, and is attracting attention from the perspective of application to high-speed, high-density integrated circuits. has been done.

Applying the above-mentioned silicidation technology to this element is important in forming a higher performance device.

The examples in FIGS. 1(a) to (e) are 808 (Silic
MI8 using on 0n8apph ire)
FIG. 6 is a schematic cross-sectional view showing a process when applying the above-mentioned silicidation to F'B'l' using a technique similar to the conventional technique. Figure (a) shows a cross section of a transistor in which a gate electrode and source/drain diffusion layers are formed using the normal 80S process, and Figure Φ) shows a cross section of a transistor in which a silicon nitride film is applied over the entire surface by the OVD method. (C) shows the sample of Φ) which was dry-etched from the top surface, leaving the nitride film only on the side wall of the gate polysilicon pole 4. Single crystal silicon is island-like ζ
During this processing, anisotropic processing and etching are performed using hydrazine, etc., so the edges are tapered at approximately 54 degrees and no nitride film remains. Figure (d) shows a Ti film deposited on the top surface and an 8i
5×10 ions with an acceleration energy of 80 K e V
The process of c1rL ion implantation is shown. FIG. 5(e) shows a cross section after ion implantation, additional annealing at 550° C., and unreacted Ti was then etched away. Ions enter the tapered portion of the island-shaped silicon end compared to the flat portion, and interfacial mixing is not performed sufficiently, so that silicidation due to thermal reaction progresses abnormally and extends onto the sapphire substrate. This situation will be explained in detail using the partial cross-sectional perspective view of FIG. In the figure, 1 is a sapphire substrate, 2 is an island-shaped silicon (constituting a transistor), 3 is a gate insulating film, 4 is a gate polysilicon electrode, 11 is an insulating film formed on the gate sidewall, and 31 and 32 are formed by the ITM method. A silicide layer is formed on the gate electrode and the source/drain diffusion layer, respectively, a silicide layer is grown abnormally on a tapered part of island-like silicon due to a thermal reaction, and a silicide layer is formed on the gate sidewall. The parts shown are those that go under the insulating film 11 and sink into the sapphire-gate polysilicon interface. This silicide layer cracking causes a short circuit between the gate electrode and the source/drain electrode.

(Object of the Invention) The present invention provides a highly reliable and high-performance insulating substrate MI8F that prevents short circuits between the gate electrode and source/drain electrodes described above.
It is an object of the present invention to provide a method for forming and attaching an ET.

(Structure of the Invention) According to the present invention, in a method for manufacturing an MI8fi field effect transistor formed using silicon crystal on an insulating transparent substrate, an island-like silicon transistor region, a gate electrode, and a source/drain diffusion layer are formed. After that, a negative photoresist is attached to the entire surface, exposed and developed from the back side, a high melting point metal is attached to the entire upper surface, and then the nuclear resist is peeled off, and non-dopant ions are ion-implanted to form the high melting point metal. A method for manufacturing an insulating substrate MIS type field effect transistor is obtained, which includes the steps of: mixing the interface between the high melting point metal and the silicon, and then thermally annealing the silicon at a portion where the high melting point metal and the silicon are in contact with each other to silicide. .

(Example) Next, the present invention will be described in detail based on the example shown in FIG. In this example, the substrate is SO8 and single-crystal Si with a thickness of 0.4 μm, as shown in Figures (a) to (f).
FIG. 3 is a schematic cross-sectional view for explaining the steps of the example.

Figure 3(a) shows a cross section of an FBT in which a gate electrode 4 and source/drain diffusion layers 2 are formed in the same process as in the conventional method.
Reference numeral 11 indicates a gate oxide film, 1 indicates a sapphire substrate, and 11 indicates a silicon oxide film formed on the side walls of the gate electrode. Next, as shown in FIG. Φ), a negative type photoresist 41 is deposited to a thickness of about 1 μm. After that, it is exposed to light from the back side and developed. At this time, by setting the exposure amount to about three times the appropriate amount when exposing from the surface, it is possible to overprint the island-shaped silicon and leave a resist as shown in FIG.

In this state, Ti-t-thickness of about 400A was formed by vacuum evaporation method.
Vapor deposition (same figure @)). After that, by peeling off the resist, T
i remains. After this, the 8i ion is 5×1015 at Sono KeV.
a' ion implantation process is heated at 550°C in Hx to form a silicide, and the remaining Ti is removed by etching (see Fig.
f)).

The above explanation uses an SO8 substrate with a thickness of 0.4 μm, but other thicknesses are also possible, and the metal may also be other high melting point metals, such as MOLW, Pt, etc. SOI (5ilico) instead of 808 board
For example, it is also applicable when using an 8i crystal grown on a quartz substrate.

(Effects of the Invention) The above steps can prevent abnormal growth of silicide in the tapered portion of the silicon island, and can prevent short circuits between the gate electrode and the source/drain diffusion layer. Silicidation lowers the resistance of the gate electrode, source and drain,
High performance MI8 FET can be obtained with high reliability.

[Brief explanation of drawings]

Figures 1 (a) to (e) show MI8 F using an SO8 substrate.
FIG. 3 is a schematic cross-sectional view showing a process when B'I is silicided by the ITM method using a conventional method. Figure 2 shows a MISFET formed by the process shown in Figure 1.
FIG. 2 is a partial cross-sectional perspective view showing a state of short circuit between the gate electrode and the source/drain electrodes. FIGS. 3(a) to 3(f) are schematic cross-sectional views showing the process of forming a MIS type FET on an 808 substrate by applying ITM silicidation according to the present invention. In the figure, 1 is an 8apphire substrate, 2 is an island-like silicon that constitutes a transistor, 3 is a gate oxide film, 4 is a gate polysilicon electrode, 11 is SiO2 by OVD method,
21 is titanium, 31 is a silicide layer on the gate electrode, 3
2 is a silicide layer on the source/drain diffusion node, 33 is a part of the island-like silicon end taper, ζ is a silicide layer that has grown abnormally due to a thermal reaction, and A is a part of the silicide layer that is buried at the interface between the gate polysilicon electrode and the sapphire substrate. , 4
1 indicates a negative photoresist, respectively.

Claims (1)

[Claims] MI formed using silicon crystal on an insulating transparent substrate
In a method for manufacturing an A-type field effect transistor, after forming a transistor region, a gate electrode, and a source/drain electrode of island-like silicon, a negative photoresist is deposited on the entire surface, exposed and developed from the back side, and the upper surface is coated with a high melting point. The process of attaching metal to the entire surface and then peeling off the resist, implanting non-dopant ions to mix the interface between the high melting point metal and silicon, and then thermally annealing the silicon in the area where the high melting point metal and silicon are in contact is removed. 1. A method for manufacturing an insulated substrate MIS field effect transistor, the method comprising the step of siliciding the insulated substrate MIS field effect transistor.