JPS60224218A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60224218A JPS60224218A JP7939384A JP7939384A JPS60224218A JP S60224218 A JPS60224218 A JP S60224218A JP 7939384 A JP7939384 A JP 7939384A JP 7939384 A JP7939384 A JP 7939384A JP S60224218 A JPS60224218 A JP S60224218A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- etching
- coating
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000001020 plasma etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- -1 15= -CVD Sin Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特にコンタクト
ホールの形成に改良を加えた半導体装置の製造方法に係
わる。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which the formation of contact holes is improved.
従来、半導体基板上例えば第1図(&)、(b)に示す
ように製造されていた。まず、例えばPfiのシリコン
基板10表面に周知の技術によ1r型の拡散層2を形成
した後、全面に絶縁膜3を形成する。つづいて、この絶
縁膜3上に、前記拡散層2の一部に対応する部分に開孔
部4を有するレジスト・母ターン5を形成する(第1図
(、)図示)。次いで、このレジストパターン5をマス
クとして反応性イオンエツチング(RIE)によシ絶縁
膜3を選択的に除去し、コンタクトホール6を形成して
半導体装置を製造する(第1図(b)図示)。Conventionally, it has been manufactured on a semiconductor substrate as shown in FIGS. 1(&) and (b), for example. First, a 1r type diffusion layer 2 is formed on the surface of a Pfi silicon substrate 10 by a well-known technique, and then an insulating film 3 is formed on the entire surface. Subsequently, a resist/mother turn 5 having an opening 4 in a portion corresponding to a portion of the diffusion layer 2 is formed on the insulating film 3 (as shown in FIG. 1(, )). Next, using this resist pattern 5 as a mask, the insulating film 3 is selectively removed by reactive ion etching (RIE) to form a contact hole 6 to manufacture a semiconductor device (as shown in FIG. 1(b)). .
しかしながら、従来技術によれば、レジスト膜やターン
5をマスクとしてRIEによシ絶縁膜3を選択的に除去
してコンタクトホール6を形成するため、レジストツヤ
ターフ5のツクターンサイズがそのままコンタクトホー
ル6のサイズ°となる。従って、コンタクトホール6の
サイズはレジスト膜リーン5のAターンサイズに依存し
、微細なコンタクトホール6を得ようとした場合、その
限界はいかにレノスト・母ターン5を微細に74ターニ
ングできるかによって決定される。つまシ、露光装置の
レジスト開孔最小の限界像が、そo”tま最小コンタク
トホールサイズとなシ最小のコンタクトホールサイズは
露光装置の性能できまる。そのため、所望の微細なコン
タクトホールが得られない可能性がある。However, according to the prior art, since the contact hole 6 is formed by selectively removing the insulating film 3 by RIE using the resist film and the turns 5 as a mask, the contact hole 6 is formed using the resist film and the turns 5 as they are. The size is 6°. Therefore, the size of the contact hole 6 depends on the A-turn size of the resist film lean 5, and when trying to obtain a fine contact hole 6, the limit is determined by how finely 74 turns of the lean mother turn 5 can be made. be done. However, the minimum limit image of the resist aperture of the exposure equipment is not always the minimum contact hole size.The minimum contact hole size is determined by the performance of the exposure equipment.Therefore, it is difficult to obtain the desired fine contact hole. There is a possibility that it will not be possible.
本発明は上記事情に鑑みてなされたもので、コンタクト
ホールサイズが露光装置の性能に依存することなく微細
なコンタクトホールを得ることのできる半導体装置の製
造方法を提供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain fine contact holes without making the contact hole size dependent on the performance of an exposure device.
本発明は、半導体基板上に絶縁膜を介して該絶縁膜に対
して選択エツチング性を有する第1の被膜を形成する工
程と、この被膜を・母ターニングする工程と、全面に前
記被膜に対して選択エツチング性を有する第2の被膜を
形成する工程と、この第2の被膜を前記第1の被膜の側
壁にのみ残存するようにエツチングする工程と、残存す
る第2の被膜及び第1の被膜をマスクとして前記絶縁膜
をエツチングする工程とを具備することによって、微細
なコンタクトホールを得ようとしたものである。The present invention includes a step of forming a first film having selective etching properties with respect to the insulating film on a semiconductor substrate via an insulating film, a step of turning this film, and a step of etching the first film over the entire surface. a step of etching the second film so that it remains only on the side wall of the first film; and etching the remaining second film and the first film. This method attempts to obtain fine contact holes by etching the insulating film using the film as a mask.
以下、本発明の一実施例を第2図(a)〜(h)を参照
して説明する。An embodiment of the present invention will be described below with reference to FIGS. 2(a) to 2(h).
〔1〕まず、例えばP型のシリコン基板11上にダート
酸化膜12を介して多結晶シリコンからなるダート電極
13を形成した後、このダート電極13をマスクとして
基板1ノにn型不純物を導入しP型の拡散層14を形成
した。つづいて、全面に層間絶縁膜としての厚さ1μm
のCVD SIO,膜15を堆積した(第2図(a)図
示)。[1] First, a dirt electrode 13 made of polycrystalline silicon is formed on, for example, a P-type silicon substrate 11 via a dirt oxide film 12, and then an n-type impurity is introduced into the substrate 1 using the dirt electrode 13 as a mask. Then, a P-type diffusion layer 14 was formed. Next, a 1 μm thick interlayer insulating film was applied to the entire surface.
A CVD SIO film 15 was deposited (as shown in FIG. 2(a)).
次いで、このCVD5iO,膜15上に第1の被膜とし
ての厚さ5000Xのモリブデン(Mo)膜1°6を堆
積した。しかる後、このMo膜16上にレジスト膜を堆
積し、写真蝕刻法によシ前記ダート電極13及び拡散層
14の夫々の一部に対応するレゾスト膜に第1の開孔部
17m、I’lbを開孔し、レジスト・リーン18を形
成した(第2図(b)図示)。更に、このレジスト・母
ターン18をマスクとして前記Mo膜16をRIEによ
シ選択的にエツチング除去し、第2の開孔部19a11
9bを形成した(第2図(C)図示)。Next, on this CVD5iO film 15, a molybdenum (Mo) film 1°6 with a thickness of 5000× was deposited as a first film. Thereafter, a resist film is deposited on this Mo film 16, and first openings 17m, I' are formed in the resist film corresponding to parts of the dirt electrode 13 and the diffusion layer 14 by photolithography. 1b was opened to form a resist lean 18 (as shown in FIG. 2(b)). Furthermore, using this resist/mother turn 18 as a mask, the Mo film 16 is selectively etched away by RIE to form a second opening 19a11.
9b (as shown in FIG. 2(C)).
〔11〕次に、前記レジス)ノfターン18を酸素プラ
ズマを用いて剥離した後、全面に第2の被膜としての厚
さ3oooKのアルミニウム(At)膜20を堆積した
(第2図(d)図示)。つづいて、このA/、膜20を
RIEによシエッチング除去し、前記Mo膜16の第2
の開孔部19m、19bの内壁にのみテーノ9−状のk
l膜20 a、 20 bを残存させた(第2図(、)
図示)。次いで、この残存するAt膜20m、20b及
びMO膜16をマスクとして前記CVD 810.膜1
5をRIEによシ選択的に除去し、コンタクトホール2
1 m、 21bを形成した(第2図(f)図示)。し
かる後、前記残存At膜20&、20b及びMo膜16
を硫酸と過酸化水素水の混合液を用いてエツチング・除
去した(第2図−)図示)。更に、全面にAtを蒸着し
、ノぐターニングしてコンタクトホール21&、21b
を介して前記ダート電極13、拡散層14に夫々接続す
るAt電極配線22 a、22 bを形成し、半導体装
置を製造した(第2図(h)図示)。[11] Next, after peeling off the resist f-turn 18 using oxygen plasma, an aluminum (At) film 20 with a thickness of 300K was deposited on the entire surface as a second film (see Fig. 2(d) ). Subsequently, this A/ film 20 is etched away by RIE, and the second film 20 of the Mo film 16 is removed by RIE.
Only on the inner wall of the openings 19m and 19b is a Teno 9-shaped k.
The l membranes 20a and 20b remained (Fig. 2(,)
(Illustrated). Next, using the remaining At films 20m, 20b and MO film 16 as masks, the CVD 810. Membrane 1
5 is selectively removed by RIE to form contact hole 2.
1 m, 21b was formed (as shown in FIG. 2(f)). After that, the remaining At films 20&, 20b and the Mo film 16
was etched and removed using a mixture of sulfuric acid and hydrogen peroxide (as shown in Figure 2). Furthermore, At is vapor-deposited on the entire surface and then turned to form contact holes 21&, 21b.
At electrode wirings 22a and 22b were formed to connect to the dirt electrode 13 and the diffusion layer 14, respectively, through the wafer, thereby manufacturing a semiconductor device (as shown in FIG. 2(h)).
しかして、本発明によれば、シリコン基板11上のCV
D5iO,膜15上にMo膜16を形成し、これをレジ
ストノぐターフ18を用いて開孔した後、レジストノリ
ーン18の剥離、At膜26’i;ji5’堆積、該A
t膜2oのRIEによるエツチングを行なってMo H
!X16の第2の開孔部19m、19bの内壁にのみA
t膜20m、20bを残存させ、しかる後この残存At
膜20 a、 20 bとMO膜16をマスクドしテC
’VD Sin、膜15をRIEにょシ選択的に除去す
るため、従来と比べAt膜20g。Therefore, according to the present invention, the CV on the silicon substrate 11
D5iO, after forming a Mo film 16 on the film 15 and opening it using a resist nozzle turf 18, peeling off the resist nolene 18, depositing an At film 26'i;ji5', and depositing the A
The t film 2o is etched by RIE to form MoH
! A only on the inner walls of the second openings 19m and 19b of X16
The T films 20m and 20b are left, and then the remaining At
The films 20a, 20b and the MO film 16 are masked and
'In order to selectively remove the VD Sin film 15 by RIE, the At film is 20g compared to the conventional one.
20bをエツチング時のマスクの一部として用いた分、
微細なコンタクトポール21 a、21bをCVD s
io、膜15に形成できる。Since 20b was used as part of the mask during etching,
CVD s of minute contact poles 21a and 21b
io, can be formed on the membrane 15.
ンタクトホール21*、21bの径を任意に変更するこ
とができる。これについて、第3図(a)〜(c)及び
第4図(、)〜(a)を参照して説明する。ここで、前
者はAt膜の厚みが薄い場合を、後者はAt膜の厚みが
厚い場合を夫々示す。なお、上記実施例と同部材のもの
は同符号を付して説明する。即ち、前者の場合は、まず
、上記実施例と同様にMo膜16を含む全面に薄いAt
膜23を形成した(第3図(a)図示)。つづいて、こ
のAt膜23をRIEでエツチング除去してMO膜16
の開孔部19の内側壁にのみ該At膜23′を残存させ
た(第3図(b)図示)。次いで、残存するAt膜23
′及びMO膜16をマスクとしてCVD Sin、膜1
5をエツチング除去し、径の大きいコンタクトホール2
4を形成して半導体装置を製造した(第3図(c)図示
)。一方、後者の場合、全面に厚いAt膜25を形成し
た(第4図(a)図示)後、これをRIBによシエッチ
ング除去してMO膜16の開孔部19の内側壁にのみ該
At膜25′を残存させ(第4図(b)図示)、更に残
存するAt膜25′及びMo膜16をマスクとしてC・
VD S 10.膜15をエツチング除去し、径の小さ
いコンタクトホール26を形成して半導体装置を製造し
た(第4図(c)図示)。以上よシ、At膜16の厚み
を変えることによってコンタクトホール21の径を任意
に変更することができることが明らかである。The diameters of the contact holes 21* and 21b can be changed arbitrarily. This will be explained with reference to FIGS. 3(a) to 3(c) and FIGS. 4(a) to 4(a). Here, the former indicates the case where the At film is thin, and the latter indicates the case where the At film is thick. Note that the same members as those in the above embodiment will be described with the same reference numerals. That is, in the former case, first, as in the above embodiment, a thin At
A film 23 was formed (as shown in FIG. 3(a)). Next, this At film 23 is removed by RIE to remove the MO film 16.
The At film 23' was left only on the inner wall of the opening 19 (as shown in FIG. 3(b)). Next, the remaining At film 23
' and MO film 16 as a mask, CVD Sin, film 1
5 is removed by etching to form a contact hole 2 with a large diameter.
4 was formed to manufacture a semiconductor device (as shown in FIG. 3(c)). On the other hand, in the latter case, after forming a thick At film 25 on the entire surface (as shown in FIG. 4(a)), this is etched away by RIB so that it is applied only to the inner wall of the opening 19 of the MO film 16. The At film 25' remains (as shown in FIG. 4(b)), and C.
VDS 10. The film 15 was removed by etching and a contact hole 26 with a small diameter was formed to manufacture a semiconductor device (as shown in FIG. 4(c)). From the above, it is clear that the diameter of the contact hole 21 can be changed arbitrarily by changing the thickness of the At film 16.
なお、上記実施例では、第1の被膜としてM。In addition, in the above-mentioned example, M was used as the first coating.
膜を、かつ第2の被膜としてAt膜を用いたが、これら
に限らず、第1の被膜としてはCVD5iO。Although an At film was used as the film and the second film, the first film may be CVD5iO.
膜とシリコン基板に対して選択エツチング性を有するも
の、第2の被膜としてはCVD5iO,膜とシリコン基
板と第1の被膜に対して選択エツチング性を有するもの
なら全てよい。Any material that has selective etching properties for the film and silicon substrate, CVD5iO for the second coating, and selective etching properties for the film, silicon substrate, and first coating may be used.
上記実施例では、Mo膜、残存するテーパー状のAt膜
を除去した後にCVD Sin、膜のコンタクトホール
にAt電極配線を形成したが、本発明はこれに限らない
。例えば第5図に示す如く、Mo膜の代シに第1の被膜
としてシリコン窒化膜31を用い、このシリコン窒化膜
31と残存するテーノぐ一部のAt膜20&、20bを
マスクとしてコンタクトホール21m、21bを形成し
た後、残存するAt膜20h、20b及びシリコン窒化
膜31を含む全面にAtを堆積、パターニングしてA/
、電極配線32 m、32 bを形成してもよい。In the above embodiment, after removing the Mo film and the remaining tapered At film, At electrode wiring was formed in the contact hole of the CVD Sin film, but the present invention is not limited thereto. For example, as shown in FIG. 5, a silicon nitride film 31 is used as a first film in place of the Mo film, and a contact hole 21 is formed using this silicon nitride film 31 and the remaining At films 20 and 20b as a mask. , 21b, At is deposited and patterned on the entire surface including the remaining At films 20h, 20b and the silicon nitride film 31, and A/21b is formed.
, electrode wirings 32 m and 32 b may be formed.
こうした方法によれば、上記実施例の場合と比べMo膜
、残存At膜を除去するという工程を省くことができる
とともに、従来と比べAt電極配線32m、32bのコ
ンタクトホール21m、21bでの断切れを防止できる
。この断切れについて、第6図(a)、(b)を参照し
て説明する。即ち、第1図の従来構造の場合、第6図(
a)に示す如く、絶縁膜3の切シ立ったコンタクトホー
ル6の所に直接At電極配線33を形成するため、At
電極配線33に断切れ34が生じる。しかるに、第5図
図示の本発明の半導体装置の場合、コンタクトホール2
1a、21bの上部周辺にテーパー状のAt膜20h、
20bを残存させた状態でAtの蒸着、ノリーニングを
行なうため、第6図(b)に示す如く、断切れのないA
4電極配線32を形成できる。According to this method, the step of removing the Mo film and the remaining At film can be omitted compared to the case of the above embodiment, and the disconnection at the contact holes 21m and 21b of the At electrode wirings 32m and 32b can be avoided compared to the conventional method. can be prevented. This disconnection will be explained with reference to FIGS. 6(a) and 6(b). That is, in the case of the conventional structure shown in Fig. 1, the structure shown in Fig. 6 (
As shown in a), in order to form the At electrode wiring 33 directly in the cut-out contact hole 6 of the insulation film 3, the At
A break 34 occurs in the electrode wiring 33. However, in the case of the semiconductor device of the present invention shown in FIG.
A tapered At film 20h is provided around the upper portions of 1a and 21b.
In order to perform the vapor deposition and nolining of At with the 20b remaining, as shown in FIG. 6(b), an unbroken A
A four-electrode wiring 32 can be formed.
以上詳述した如く本発明によれば、従来と比べ微細なコ
ンタクトホールを形成できる半導体装置の製造方法を提
供できるものである。As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that can form contact holes that are finer than conventional methods.
第1図(、)、(b)は従来の半導体装置の製造方法を
工程順に示す断面図、第2図(a)〜(h)は本発明の
一実施例に係る半導体装置の製造方法を工程順に示す断
面図、第3図(&)〜(C)はAt膜が薄い場合の本発
明に係る半導体装置の製造方法を工程順に示す断面図、
第4図(、)〜(C)はAt膜が厚い場合の本発明に係
る半導体装置の製造方法を工程順に示す断面図、第5図
は本発明の他の実施例に係る半導体装置の断面図、第6
図(&)、(b)は従来及び本発明に係る半導体装置の
コンタクトホールにおけるAt電極配線の断切れの有無
を説明するための断面図である。
1ノ・・・P型のシリコン基板、12・・・ダート酸化
膜、13・・・ダート電極、14・・・拡散層、15=
−CVD Sin、膜、16− Mo膜(第1の被膜)
、17m、17b、19th、19b−開孔部、1 B
・・・レジストツクターフ、20.20 m、20b
。
23.23′、25.25’ ・At膜、21a、21
b。
24.26・・・コンタクトホール、22IL122b
132&、32b、33・・・At電極配線、31・・
・シリコン窒化膜、34・・・断切れ。
出願人代理人 弁理士 鈴 江 武 彦第1図
(a) (b)
第2図
第2図
’r!’52図
第3図 第4図FIGS. 1(a) and 1(b) are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps, and FIGS. 2(a) to (h) are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3(&) to (C) are cross-sectional views showing the method of manufacturing a semiconductor device according to the present invention in the order of steps when the At film is thin;
4(a) to 4(c) are cross-sectional views showing the manufacturing method of a semiconductor device according to the present invention in order of steps when the At film is thick, and FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure, 6th
Figures (&) and (b) are cross-sectional views for explaining the presence or absence of breaks in the At electrode wiring in the contact holes of semiconductor devices according to the prior art and the present invention. 1 No... P-type silicon substrate, 12... Dirt oxide film, 13... Dirt electrode, 14... Diffusion layer, 15=
-CVD Sin, film, 16- Mo film (first film)
, 17m, 17b, 19th, 19b-opening section, 1 B
...Resist Turf, 20.20 m, 20b
. 23.23', 25.25' ・At film, 21a, 21
b. 24.26...Contact hole, 22IL122b
132&, 32b, 33... At electrode wiring, 31...
・Silicon nitride film, 34...broken. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (a) (b) Figure 2 Figure 2 'r! '52 Figure 3 Figure 4
Claims (1)
選択エツチング性を有する第1の被膜を形成する工程と
、この被膜を・ぐターニングする工程と、全面に前記被
膜に対して選択エツチング性を有する第2の被膜を形成
する工程と、この第2の被膜を前記第1の被膜の側壁に
のみ残存するようにエツチングする工程と、残存する第
2の被膜及び第1の被膜をマスクとして前記絶縁膜をエ
ツチングする工程とを具備することを特徴とする半導体
装置の製造方法。 (2)絶縁膜をエツチングした後、残存する・第2の被
膜及び第1の被膜をエツチング除去し、電極配線材料層
を全面に堆積し、しかる後これを・臂ターニングして電
極配線を形成することを特徴とする特許請求の範囲第1
項記載の半導体装置の製造方法。 (3) コンタクトホールを形成した後、電極配線材料
層を残存する第2の被膜及び第1の被膜を含む全面に堆
積し、更にこれをノやターニングして電極配線を形成す
ることを特徴とする特許請求の範囲第1項記載の半導体
装置の製造方法。 (4) 第1の被膜としてMo膜を、かつ第2の被膜と
してAj膜を用いることを特徴とする特許請求の範囲第
1項記載の半導体装置の製造方法。 (5) 第1の被膜としてシリコン窒化膜を用いること
を特徴とする特許請求の範囲第3項記載の半導体装置の
製造方法。[Scope of claims] forming a second coating having selective etching properties with respect to the coating; etching the second coating so that it remains only on the sidewalls of the first coating; and etching the remaining second coating. and a step of etching the insulating film using the first film as a mask. (2) After etching the insulating film, remaining second film and first film are etched. Claim 1, characterized in that the film is removed by etching, a layer of electrode wiring material is deposited on the entire surface, and then this is turned to form the electrode wiring.
A method for manufacturing a semiconductor device according to section 1. (3) After forming the contact hole, an electrode wiring material layer is deposited on the entire surface including the remaining second coating and the first coating, and this is further turned to form the electrode wiring. A method for manufacturing a semiconductor device according to claim 1. (4) The method for manufacturing a semiconductor device according to claim 1, characterized in that a Mo film is used as the first film and an Aj film is used as the second film. (5) The method for manufacturing a semiconductor device according to claim 3, characterized in that a silicon nitride film is used as the first film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7939384A JPS60224218A (en) | 1984-04-20 | 1984-04-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7939384A JPS60224218A (en) | 1984-04-20 | 1984-04-20 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60224218A true JPS60224218A (en) | 1985-11-08 |
Family
ID=13688613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7939384A Pending JPS60224218A (en) | 1984-04-20 | 1984-04-20 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60224218A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185024A (en) * | 1989-01-11 | 1990-07-19 | Rohm Co Ltd | Manufacture of semiconductor device |
US5705420A (en) * | 1990-03-08 | 1998-01-06 | Fujitsu Limited | Method of producing a fin-shaped capacitor |
JP2009105225A (en) * | 2007-10-23 | 2009-05-14 | Yamaha Corp | Magnetic sensor, and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5788746A (en) * | 1980-11-25 | 1982-06-02 | Fujitsu Ltd | Preparation of semiconductor device |
JPS5834917A (en) * | 1981-08-27 | 1983-03-01 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-04-20 JP JP7939384A patent/JPS60224218A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5788746A (en) * | 1980-11-25 | 1982-06-02 | Fujitsu Ltd | Preparation of semiconductor device |
JPS5834917A (en) * | 1981-08-27 | 1983-03-01 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185024A (en) * | 1989-01-11 | 1990-07-19 | Rohm Co Ltd | Manufacture of semiconductor device |
US5705420A (en) * | 1990-03-08 | 1998-01-06 | Fujitsu Limited | Method of producing a fin-shaped capacitor |
US6144058A (en) * | 1990-03-08 | 2000-11-07 | Fujitsu Limited | Layer structure having contact hole, method of producing the same, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor and dynamic random access memory having the fin-shaped capacitor |
US6528369B1 (en) | 1990-03-08 | 2003-03-04 | Fujitsu Limited | Layer structure having contact hole and method of producing same |
JP2009105225A (en) * | 2007-10-23 | 2009-05-14 | Yamaha Corp | Magnetic sensor, and manufacturing method thereof |
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