JPS60223161A - Charge transfer device output circuit - Google Patents

Abstract

PURPOSE:To sharply reduce the input capacitance of a source follower output circuit, to eliminate a back gate effect, and to obtain an output circuit of high sensitivity and high S/N for a CCD (charge coupled device) having excellent linearity by a method wherein the second semiconductor region is connected common to the source terminal of the MOS transistor having a drain terminal connected to a power source. CONSTITUTION:The transistor Q3, whereon the drain terminal of the MOS transistor constituting an output circuit, is formed in a semiconductor region 27 separately from the semiconductor region 42 where a CCD will be constituted. As a result, the source terminal of the transistor Q3 constituting an output terminal can be connected common to a P-well 27. As the P-well, which is the effective substrate of the Q3, is connected common to an output terminal 29, the threshold voltage of the Q3 can be constantly maintained irrespective of the fluctuation of the output voltage BOUT, thereby enabling to remove the so- called back gate effect.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to an output circuit of a charge transfer device (prior art and its problems). Charge transfer devices, represented by (denoted as ), are based on conventional advanced integrated circuit technology, and have been rapidly developed along with their development, and have recently been used for various applications such as solid-state imaging, analog delay lines, and memories. In particular, solid-state image sensors using COD have many features such as low power consumption, small size, light weight, and high performance, and their development is active. There is a trend toward increasing the number of pixels and increasing the density, and as a result, the amount of signal charge that can be handled is decreasing.

Therefore, a high-performance output amplifier is required to detect this minute signal charge.

The performance required for such an output amplifier is 8/
N, linearity, amplification degree, etc. are sufficiently good. Conventionally, source follower circuits or inverter circuits using MOS transistors are generally used as such output amplifiers. However, In an output amplifier composed of a large number of MOS transistors formed in a semiconductor region, the so-called back gate effect of the MOS transistors whose drain terminals are connected to the power supply side deteriorates the nearness, amplification degree, etc. as described above. .

FIG. 1 shows a simplified cross-sectional view of the vicinity of the output of a conventional CCD and an equivalent circuit of the output amplifier. In FIG. 1, 1 is a semiconductor substrate, and in this example, assuming an N channel, P
A mold silicon substrate is used.

2 is an N-type semiconductor region that forms a buried channel of the CCD. This area may be omitted since it is not directly related to the gist of the present invention. 3 and 4 are N4 diffusion layers of the opposite conductivity type to the P-type substrate 1, 5 is a reset gate electrode, 3 is a drain,
A reset transistor is constructed with 5 as a gate and 4 as a floating source. Reference numerals 6 to 10 indicate transfer electrodes of the CCD, and in this example, a two-layer gate electrode structure is shown, but the reference numeral 043 indicates an oxide film. Q 1r
Q2 is a MOS transistor forming an output amplifier formed on the same P-type substrate 1 as the CCD.

In this example, a source follower circuit is used as the output amplifier, but an inverter circuit or the like may also be used. The gate i2 of the transistor Qi is connected to the floating diffusion layer 4 through the arrangement ll.
The drain terminal 13 of oQl, which is connected to Alternatively, the source terminal 17 of OQ2, which is grounded, is normally grounded. Transistor Q1? Since Q2 is formed on the same substrate as the CCD, the substrate terminals 18 and 19 of Ql and Q2 are connected to CCD.
It is set to the same potential as the substrate 1 of the CD, that is, the ground potential in this example.

Next, the operation of this device will be explained. First, electrons, which are signal charges, are transferred from the right side to the left side of the drawing by the transfer electrodes 6 to 1O of the CCD, and are transferred from the reset gate 5 to the diffusion J
At this time, the potential V of the floating diffusion layer flows into the floating diffusion layer 4, which is set to a reference potential in advance, by the reset transistor constituted by a reset transistor such as @3. The capacitance of the diffusion layer 4 and the capacitance of the wiring 11.

If CyJ is the sum of the input capacitance, etc. of transistor Q1, and QHa is the signal charge to be transferred, then Vy = Qs□G/C
O given as FJ Furthermore, this vl value is passed through a source follower amplifier. Output as UT. By the way, in general, as an output amplifier for a CCU, the input capacitance of the amplifier is required to be small, the amplification degree is large, and the linearity is good.The input capacitance C1n of the source follower amplifier shown in this example is given by the following formula. O Cin=Cgd + (1-A) Cgs (11 Here, Cg is the gate 12 and drain 1 of the transistor Q1
3, Cgs is the capacitance between the gate 12 and the source 14, and A is the amplification degree of the source follower. Furthermore, assuming that transistor Q2 is an ideal constant current circuit, this person is given by the following equation.

A= gm / (gm + gmb) (2) where gm is the mutual conductance of transistor Ql, gtn
b is the pack gate conductance O conventional COD
In the source follower amplifier, since Ql is formed of the same semiconductor as the COD, the substrate terminal 18 of Ql is at a fixed potential, that is, in this example, the ground potential. Therefore, in general, gmb does not become zero but has a finite value. Therefore, the amplification degree A shown in equation (2) also takes a value of 1 or less. As can be seen from equation (1), this increases the input capacitance C,n. A similar problem occurs not only when a source follower circuit is used but also when an impark circuit is used. In addition, the linearity of the amplifier generally deteriorates due to the back gate effect. Furthermore, the input capacitance C
As in increases, kTC noise at the CCD output section also increases. As described above, sufficient performance could not be obtained with the conventional COD output amplifier. (Objective of the Invention) An object of the present invention is to provide an output circuit for a charge transfer device that eliminates the above-mentioned conventional drawbacks. There is a particular thing.

(Structure of the Invention) According to the present invention, an arbitrary number of MOSs are formed in a semiconductor having one conductivity type and are formed in a first semiconductor region having a conductivity type opposite to the semiconductor, for detecting signal charges. ) In an output circuit of a charge transfer device constituted by a transistor, at least one MO transistor whose drain terminal is connected to a power supply is provided. A charge transfer element formed in a second semiconductor region, and wherein the second semiconductor region is commonly connected to a source terminal of a MOS transistor whose drain terminal is connected to a t source. An output circuit is obtained.

(Example) Next, the present invention will be explained in detail using the drawings.

2 and 3 show an embodiment of the output circuit of the charge transfer device according to the present invention, respectively showing a plan view and a sectional view thereof, and FIG. 4 shows an equivalent circuit of only the output circuit. In this embodiment, the CCD and output circuit are N
P-well 42 or 27 formed on mold substrate 41
is formed inside. In the figure, Q3 and Q4 are MOS) transistors that constitute the output circuit, and Q3 is o21 whose drain terminal 22 is connected to the power supply VDD.
, 23 are the gate and source of Ql, and 23 is connected to the P well 27 in which Ql is formed and the drain terminal 24 of Q4 to form an output terminal. 25 and 26 are the gate and source of Q4.

The feature of the device according to the present invention is that the MOS that constitutes the output circuit
) transistor whose drain terminal is connected to the power supply is the semiconductor region (
In this embodiment, the semiconductor region (P-well 42) is independent of the semiconductor region (
In this embodiment, the source terminal of Q3, which constitutes the output terminal, can be commonly connected to the P well 27 because it is formed in the P well 27). The equivalent circuit of the output circuit in this embodiment is shown in FIG.

In this circuit, the effective board of Q3 is P/I.
/27 is commonly connected to the output terminal 29, so the output voltage is ■. The threshold voltage of Q3 is kept constant regardless of the variation in U, so that the so-called back gate effect can be eliminated. Therefore, as long as the pack gate conductance gmb as described above is zero, the amplification degree of the present output circuit can be almost a value close to 1. This means that the input capacitance of the present source follower output circuit can be significantly reduced, and an output circuit with high sensitivity and high S/N can be realized for COD. Furthermore, since there is no backgate effect, a high performance output circuit with extremely good linearity can be realized.

(Effects of the invention) As described above, according to the present invention, a high-performance output circuit can be realized◎
It is clear that the gist of the present invention can also be applied to a P-channel circuit or a circuit using an inverter.

[Brief explanation of drawings]

FIG. 1 shows a cross-sectional view near the output of a conventional COD and an equivalent circuit of the output circuit, and FIGS. 2 and 3 show a plan view and a cross-sectional view of a device according to the present invention. FIG. 4 shows an equivalent circuit of the output circuit according to the present invention.
Q4 is a MOS) transistor, 1 is a P-type substrate, 2 is an N-type semiconductor region forming a buried channel, 3.4.5 is the drain, source, and gate of the reset disk, 6
~10 is a CCD transfer electrode, 43 is an oxide film, 12.13
．． 14 is the gate, drain, and source of Ql, 15.16
．． 17 is the drain, gate, and source of Q2, 18, 19
is the board terminal where Ql and Q2 are configured, 20 is the output terminal,
21, 22.23 are the gate, drain, and source of Q3,
24, 25, 26 are the drain, gate, and source of Q4,
27 is a P-well where Q3 is formed, 41 is an N-type substrate, and 42 is a P-well where a CCD and Q4 are formed. @Figure 1 Figure 2

Claims (1)

[Claims] A charge transfer element is formed in a first semiconductor region having a conductivity type opposite to that of the semiconductor and is formed in a semiconductor having a conductive turtle shape, and is constituted by an arbitrary number of MOS transistors for detecting signal charges. In the output circuit, at least one of said M whose drain terminal is connected to a power supply
The OS transistor is formed in a second semiconductor region that is independent of the first semiconductor region and has a conductivity type opposite to that of the semiconductor, and the second semiconductor region is an MO8 transistor whose drain terminal is connected to a power source. ) An output circuit for a charge transfer element, characterized in that it is commonly connected to a source terminal of a transistor.