JPS60215270A - Access system of direct memory - Google Patents

Abstract

PURPOSE:To improve the working efficiency of a system requiring the multiplex processing by performing the switching with a DMA action among an address bus, data bus and a write signal by means of each switch, and preventing a holding state of a CPU in a DMA mode. CONSTITUTION:A signal line led from a CPU301 is connected directly to a ROM304 and also to a RAM305 via an address bus and a data bus. A write signal line is connected to the RAM305 via switches 307-309. The input of the other side of each of switches 307-309 is connected to an address bus 316 led from a DMA controller 310, a data bus 317 led to an external device and a write signal line 318 led from the controller 310, respectively, and controlled by the CPU301 via a switch signal line 315. No problem is produced in a period when the CPU301 reads the program of the ROM304 even in case the controller 310 supplies a simultaneous access to the RAM305 since the bus is separated. Thus it is possible to perform a DMA action with holding the CPU301.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for reading data from a computer system's memory and transferring it to an external device. relates to a direct memory access method for shortening transfer time.

(Prior Art) In the conventional direct memory access method as shown in FIG. This was accomplished through two operations: transfer to and from RAM. In Figure 1, 101 is the CPU, 102 is the R
OM.

103 is a RAM, 104 is an accumulator.

105 is a buffer, 106 is a boat forming an external device, 1
07 is a transfer path between the boat 106 and the accumulator 104, 108 is the accumulator 104 and the RAM 10
3, 10B is a DMA transfer path, 11G is a data bus, and 111 is a computer system.

Transfer speed in the above mode is slow, so boat 1
The so-called direct memory access method, or DMA method, is a method in which the transfer operation between the 011 and the accumulator 104 is omitted, and data is transferred only between the accumulator 104 and the RAM 103. In the conventional DMA method, the data bus 110 is baud)
Since the bus between 108 and RAM 103 is occupied, the CPU 101 is unable to read the program code from the program storage device composed of ROM 102, and is forced into a temporary halt state, that is, a hold state. There was the problem of being abused.

Which fact is one C! When assuming a multi-processing method that performs multiple processes compared to PUK, this would be a major drawback.

(Object of the Invention) The object of the present invention is to avoid the hold state of the CPU in DMA mode by switching the address bus, data, '&, and memory write signals using respective switchers to enable DMA operation. In particular, it eliminates the above-mentioned drawbacks, improves the efficiency of systems requiring multiple processing, and
The object of the present invention is to provide a direct memory access method configured to eliminate bottlenecks in system construction.

(Structure of the invention) The memory access method according to the present invention is RAM.

This is realized by comprising first to eighth switching devices.

RAM is used for direct memory access as well as for CPU control.

The first switch selects the address bus from the CPU or the address bus from the DMA controller, and
This is for giving as address information to.

The second switch is for selecting either a data bus from the CPU or a data bus from an external port, and supplying the data to the RAM as data information.

This is to select either the memory write information line from the eighth switch CPU or the memory write information line from the DMA controller and provide it as RAMK memory write information.

(Example) Next, a direct memory access method according to the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the principle for realizing the direct memory access method according to the present invention. In FIG. 2, 201 is a RAM.

202 to 204 are first to eighth switching devices. RAM2
Address bus signal line 2 that passes input/output signals to 01
12. Data bus signal line 213. Also, the RAM 201 and each of the switches 202 to 204 are connected via a write control input signal line 214. The first switch 202 selects either the address bus signal line 208 or the address bus signal line 2011 from the external DMA controller. The second switch 203 selects the data bus signal line 206 to the CPU, or the data bus signal line 207 between the port F and the RAM 201.

The eighth switch 204 selects either the write control input signal line 210 from the CPU or the control input signal line 211 from the DMA controller. The above switching is performed by a timing pulse on signal line 205. During DMA operation, the CPU is forced to enter a hold state, but this is because the address bus signal line 212 and data bus signal line 213 of the RAM 201 become common traps with the CPU's address bus signal line and data bus signal line. It is.

Therefore, as shown in FIG. 2, the first switch 202 is used to transfer address information from the CPU or DMA address information output from the DMA control unit to the signal line 202.
05 timing pulse CI F s ) K J niche time division LTE RAM 201 K is supplied. The data and RAM write pulses are supplied in a similar manner to v
The timing pulse on the sbo signal line 205 is the ROM
It is also possible to use an internal search signal to indicate that the instruction code is to be read out and φ.

FIG. 8 shows an embodiment of the direct memory access method according to the present invention. In Figure 8, 301 is C
PU, 302 is an accumulator, 303 is an address bus signal line, and 304 is a ROM.

305 is a RAM, 306 is a data bus signal line, 307~
309 is the first to eighth switch, $10 is the DMA controller,
311 is a buffer, 312 is an external device, 313 is a transfer request signal line, 314 is a control signal line, 315 is an instruction fetch signal line, 31@ is an address signal line, 31
7 is a data bus signal line, and 318 is a memory write signal. FIG. 8 shows the operation when a transfer request is rarely received from an external device. When a transfer request is sent to the DMA controller 310 from the external DMA request signal line 313, the DMA controller 310 transfers the request to the CP via the control signal 8314.
Notify U301. Upon receiving this, the CPU 301 sends the address information to the DMA controller 310 via the data bus signal line 306, and further sends the address information to the DMA controller 310 via the control signal line 314.
Trigger the MA controller 310. When the transfer ends, the DMA controller 31G notifies the end of the transfer through the control signal line 314. This DMA transfer is performed by the CPU 301
Or, because it is carried out during the index fetch cycle period when the program is read from the ROM 304,
CPU301 will no longer hold 50CPU30
During the period when No. 1 reads the program, an instruction signal is output from the signal line 315. As a result, the first to eighth switching devices 807 to 3Q9 are respectively DM
The address signal line 316 from the A controller 310, the data bus signal line 317° from the external device, and the memory write signal line 318 from the KDMA controller 310 are switched to be selected. Therefore, data from the external device is written to the address specified by address bus signal line 316 to DMA controller 310. On the other hand, at the same time, the CPU 301 uses the data bus 1306t'A to read the program code from the RAM 104 into the accumulator 302.
Perform normal operations.

(Effects of the Invention) As explained above, according to the method according to the present invention, address information, data, and memory write signals are switched using respective switchers to enable DMA operation.
By avoiding the CPU hold state during DMA mode, the efficiency of systems that require multiple processing is improved, and bottlenecks in system construction are removed, making system implementation easier. Ai.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a device for realizing direct memory access according to the prior art. FIG. 2 is a block diagram showing the basic configuration of a device for realizing direct memory access according to the present invention. FIG. 8 is a block diagram showing an embodiment for realizing the principle of FIG. 2. IQl, 301-@-CPU 102.304...ROM 103.201.305 ・ ・ ・RAM104.3
02/111 Accumulator 105. 311...Buffer 1G6, 312...External device 111/Lo...System 202-2'04, 307-309...Switcher 310
------DMA controller 107~110, 2'05~214, 303°3
06.313~31B--Su・Hai name Patent applicant NEC Corporation Representative Patent attorney Hisashi Inoro Figure 1 Figure 22 L14 Figure 23

Claims (1)

[Scope of Claims] A RAM related to CPU control and used for direct memory access, and an address bus from the CPU or an address bus from a DMA controller can be selected and connected to the RAM. a first switch for providing address information; a second switch for selecting either a data bus from the CPU or a data bus from an external port and providing it as the RAM busy data information; An eighth switch for selecting the memory write information line from the CPUt or the memory write information line from the DMA controller and providing it as the RAMK memory write information is configured as K. A direct memory access method that is characterized by the realization of