JPS60214560A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accomplish stabilization of the source resistance or the drain resistance of a field-effect type transistor by a method wherein a dummy transistor, having a source and a drain of the same potential, which does not form an inversion layer at the lower part of a gate part at all times, is formed using the same mask as a field-effect type transistor. CONSTITUTION:A dummy transistor 14 is formed using the same mask used for the gate 3-1 of the driver transistor 3 located on a memory cell. This dummy transistor 14 has the source and the drain of the same potential by connecting the source and the drain or by performing a wiring connection using other metal and the like. As a result, no inversion layer is formed on the lower part of said dummy transistor 14, and a non-conductive state is maintained by the dummy transistor. Also, the same effect that an inversion layer is not formed on the lower part of the dummy transistor 14 will be available by applying a voltage on the gate electrode of the dummy transistor 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor integrated circuits, and particularly to improvements in semiconductor integrated circuit devices such as static random access memories.

[Prior art] A conventional device of this type is shown in FIGS. 1 and 2.

Figure 1 shows static random access memory (hereinafter referred to as
FIG. 2 is a new view taken along line 1--1 in FIG. 1. In FIG. 1, a memory cell 1 of a static RAM includes a driver transistor 3 and an access transistor 4. As shown in FIG.

The drain and gate of the driver transistor 3 are cross-connected to each other. Further, both the driver transistor 3 and the access transistor 4 are field effect transistors. On the p-type semiconductor substrate 10, an n+ type scattered layer 6 shared with adjacent cells and an n+ type scattered layer 8 not shared with adjacent cells are formed, and field oxidation is applied to the outside of the n++ scattered layer 8. There is 119. Both n++ diffusers 6 and 8 are grounded. Furthermore, a power supply line 5 and a high resistance 7 made of second polysilicon are formed. High resistance 7 and driver transistor 3 are separated by insulation WA11, and gate oxide 1112 exists between driver transistor 3 and p-type semiconductor substrate 10. The n++ scattered region on the substrate and the bit line are connected through a through hole 13. However, for simplicity, the bit lines are omitted in FIG. 1.

FIG. 3 shows an equivalent circuit of the memory cell 1 described above.

In FIG. 3, Ql and Q2 each correspond to access transistor 4 in FIG. 1. In addition, Q3 and Q4 are
Driver transistor 3 in FIG. 1 constituting a memory cell
corresponds to R3 and R4 correspond to high resistance 7 in Figure 1,
R1 and R2 are respectively the above Q3. This is the source resistance of Q4. Next, the operation of the conventional device will be described. A driver transistor Q3, whose drain and gate are cross-connected to each other, constitutes a memory cell of a static RAM. Source resistances R1 and R2 of Q4 are determined by the distance between the gates of driver transistors 3 of adjacent memory cells inside the memory cell array. However, at the end of the memory cell array, the source resistances R1 and R2 are connected to the gate 3-1 of the driver transistor 3 of the memory cell and LOGO8I.
It is determined by the distance from the field oxidation l119 created by etc. Therefore, during the manufacturing process, due to mask misalignment, the gate 3-1 of the driver transistor 3
and field oxidation W! If the distance to A9 changes,
Generally, this distance is short, so the source resistance at this portion varies greatly. In this way, in conventional devices,
In cells at the ends of a memory cell array including field effect transistors, an imbalance occurs in the source resistances R1 and R2, resulting in a disadvantage that the memory cells become unstable.

[Summary of the Invention] Therefore, the main object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor integrated circuit device including a field-effect transistor that has stable operation.

To summarize, the present invention provides that in a semiconductor integrated circuit device having a plurality of field effect transistors, the field effect By forming the field effect transistor using the same mask as the field effect transistor, it is possible to stabilize the source resistance or train resistance of the field effect transistor, which becomes unstable due to mask misalignment during the manufacturing process.

The above objects and other objects and features of this invention * tr
, will become more apparent from the detailed description referred to below.

[Embodiment of the Invention] FIG. 4 shows one memory cell 1 and a dummy gate 14 at the end of a memory array according to an embodiment of the invention, and FIG. 5 is a cross section taken along the line I-1 in FIG. 4. It is a diagram. Figure 4,
In FIG. 5, FIG.

The same or corresponding parts as in FIG. 2 are designated by the same reference numerals. In the embodiment, the dummy transistor 14 is formed using the same mask as the gate 3-1 of the driver transistor 3 of the memory cell. The source and drain of this dummy transistor 14 are at the same potential because the source and drain are continuous or -0- are connected by wires such as other metals. As a result, no inversion layer is formed under the dummy transistor 14, and the dummy transistor 14 is in a non-conductive state. The same effect can also be obtained by applying a voltage to the gate electrode of the dummy transistor 14 so that no inversion layer is formed under the dummy transistor 14. Note that in FIG. 4, bit lines are omitted for simplicity. When using the dummy transistor 14 that does not always form an inversion layer under itself as described above, this dummy transistor 14 is formed with the same mask as the gate 3-1 of the driver transistor 3 in the memory cell, so the memory In the memory cell at the end of the cell array, the distance between the gate 3-1 of the driver transistor 3 and the dummy transistor 14, that is, the width of the n+ diffusion layer 8, is kept constant without being affected by mask displacement. That is, according to the embodiment of the present invention, even if mask displacement occurs, the driver transistors Q3 . The source resistance R1°R2 of Q4 is stable, and it is possible to prevent the memory cell from becoming unstable, resulting in a stable memory cell. In the above embodiment, the end portion of the memory cell array has been described, but the same holds true for a portion equivalent to the end portion inside the cell array, for example, between the ground line and the driver transistor in the memory cell. Although the present invention has been described with respect to a memory cell, the same resistance control effect as in the above embodiment can be obtained also in other semiconductor integrated circuit devices having a plurality of field effect transistors.

[Effect of the invention] As described above, this invention can achieve the following without complicating the manufacturing process.
This stabilizes the drain resistance and source resistance of the field effect transistor, making it possible to provide a semiconductor integrated circuit device including a well-balanced and stable field effect transistor.

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram of a part of the edge of a conventional memory cell array. FIG. 2 is a cross-sectional view of the I-wiring shown in FIG. 1. FIG. 3 is an equivalent circuit diagram of the memory cell 1. FIG. 4 is an embodiment of the present invention, and is a pattern diagram of one memory cell and a dummy 1 transistor at the end of the memory cell array. FIG. 5 is a cross-sectional view taken along line T'' in FIG. VS4. In the figure, 1 is a memory cell, 2 is a word line, and 3 is a field effect type in which the drain and gate of memory cell 1 are cross-connected to each other! Helangistor, 3-1 is the gate of the driver transistor 3, 4 is the access transistor, 5 is the power supply line, 6 is the grounded n+ diffusion layer shared with the neighboring cell, 7 is the high resistance polysilicon, 8 is the neighboring cell 9 is a field oxide film, 10 is a p-type semiconductor substrate, 11 is an interlayer insulator between the gate 3-1 of the driver transistor 3 and the high resistance 7, 12 is a gate oxide A film, 13, connects the bit line and the n+ diffusion layer on the p-type substrate, an S through hole, 14, dummy transistors, Ql, Q2, access transistors, Q3. Q
4 is a driver transistor, R1 and R2 are each Q3. Q4 source resistance, R
3.R4 is a resistance. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent: Masuo Oiwa 10 - Written amendment to procedures for 3 diagrams, 4 diagrams, 5 diagrams (spontaneous) 29 Name of invention: Semiconductor integrated circuit device 3, Person making the amendment Representative: Hitoshi Katayama Department 4, Agent 5, Amendment Claims column and Detailed Description of the Invention column 6 of the subject specification, contents of amendment (1) The claims of the specification are corrected as shown in the attached sheet. (2) "See below" on page 6, line 9 of the specification is corrected to "r see drawings". (3) The word "formed" on page 6, line 19 of the specification is corrected to "formed outside the edge memory cell in a manner that limits the source region 8." (4) Delete "As a result..." from lines 2 to 4 of page 7 of the specification. (5) On page 7, line 7 of the specification, "the same is true" should be corrected to "shidaru". 2. Claims (1) In a semiconductor integrated circuit including a plurality of field effect transistors formed using the same mask, a dummy whose source and drain are at the same potential by the same mask as the plurality of field effect transistors. A semiconductor integrated circuit device characterized in that a transistor is formed. (2) The semiconductor integrated circuit device according to claim 1, wherein the source and drain of the dummy transistor are continuous. (3) The semiconductor integrated circuit device according to claim 1, wherein the source and train of the dummy transistor are interconnected by another metal or the like. (4) The semiconductor integrated circuit device according to claim 1, wherein the dummy transistor limits a part of the boundary of the source or drain region of at least one of the field effect transistors. (5) The semiconductor integrated circuit according to claim 1, wherein a voltage is applied to the gate electrode of the dummy transistor so that an inversion layer is not formed under the dummy transistor. Device. (6) The semiconductor integrated circuit device has an array of memory cells configured by cross-connecting the drains and gates of a pair of field-effect transistors, and the field-effect transistors of adjacent memory cells in the array includes a static random access memory having a common source area;
The dummy transistor is provided outside an end memory cell located at an end of the array of memory cells, and has a thickness of 11%.
2. The semiconductor integrated circuit device according to claim 1, wherein a part of the IJ is limited. 4- Mr. Commissioner of the Patent Office 1. Indication of the case: Japanese Patent Application No. 59-73254 2, Name of the invention: Semiconductor integrated circuit device 3, Person making the amendment Representative: Hitoshi Katayama Department 4, Agent 5: Number of inventions increased by the amendment 1 6, Subject of the amendment Claims column 9 Detailed description of the invention column 1 of the specification
Brief Description of Drawings Column 1 Figures 1 and 4 of the drawings, Figure 7, Contents of amendment (1) The scope of claims is amended as shown in the attached sheet. (2) "Source and..." in lines 1 to 4 of page 6 of the specification shall be corrected to the following sentence. A limited region is provided adjacent to the source region or drain region of the field effect transistor to limit the source region or train region and does not have an on/off function as a gate of the transistor, and this limited region and the above field effect By forming the gate region of the type transistor using the same mask, (3) "Dummy gate 14Jt=r dummy gate (limited region) 14" on page 6, line 13 of the specification.
"Correction 2- Correct. (4) “In the specification, page 6, line 17, page 7, lines 2 to 3, page 7, lines 9 to 10, page 10 to line 11, page 15, “ dummy transistor”
Corrected to ``dummy gate (limited area)''. (5) From page 6, line 19 to page 7, line 2 of the specification
Delete "This dummy transistor...". (6) "A voltage is applied to the gate electrode of the dummy transistor 14, and the dummy transistor 14" is changed from "A voltage is applied to the dummy gate (limited region) 14, and the dummy gate (Limited area) Corrected to 14. (7) "Dummy transistor" in lines 3 to 4 of page 9 of the specification and line 19 of the same page is replaced by "dummy gate (
(limited area)”. (8) Figures 1 and 4 of the drawings will be corrected as shown in the attached sheet. Above 3-2, Claims Integrated Circuit Device. lie 1 1all! O semiconductor integrated circuit device. Device. 4- (4) Semiconductor integrated circuit equipment is affected by space and radiation. 5- 1 fig.

Claims (6)

[Claims] (1) In a semiconductor integrated circuit including a plurality of field effect transistors formed using the same mask, a dummy transistor whose source and drain are at the same potential is formed using the same mask as the plurality of field effect transistors. A semiconductor integrated circuit device characterized by: (2) The semiconductor integrated circuit device according to claim 1, wherein the source and drain of the dummy transistor are continuous. (3) The semiconductor integrated circuit device according to claim 1, wherein the source and drain of the dummy transistor are interconnected by another metal or the like. (4) The semiconductor integrated circuit device according to claim 1, wherein the dummy transistor limits a part of the boundary of the source or drain region of at least one of the field effect transistors. (5) The semiconductor integrated circuit device according to claim 1, wherein a voltage is applied to the gate electrode of the dummy transistor so that an inversion layer is not formed under the dummy transistor. (6) The semiconductor integrated circuit has an array of memory cells configured by cross-connecting the drains and gates of a pair of field effect transistors, and the field effect type of the adjacent memory cells in the array is a static random access memory in which the transistors have a common source region;
2. The semiconductor integrated circuit device according to claim 1, wherein the dummy transistor is provided at an end of the array of memory cells.