JPS6021439B2 - sense amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier, and more particularly to a one-transistor cell RAM (RAM) in which a memory cell is configured using one FET (insulated gate field effect transistor) and one capacitor.
This invention relates to sense amplifiers used in random access memories.

In a one-transistor cell RAM, information from a memory cell is input to a printer sense amplifier and amplified by the printer sense amplifier.

The relationship between the memory section and the pre-sense amplifier is as shown in FIG. 'In the same figure, pairs of data lines D, ~D4, D, ~D4 are connected to a pair of input points of a presense amplifier having a flip-flop circuit configuration in which an FET as a load is controlled by a signal OP^, respectively. A plurality of memory cells each consisting of an FET as an information transfer means and a capacitor as an information storage means are connected to the data line. Word lines W, ~W, in a direction crossing the data lines. are provided, and each data line is connected to the gate of an FET serving as the information transfer means. (Hereinafter, this group of memory cells will be referred to as a memory cell array.) The sources of the drive FETs constituting each of the above flip-flops are commonly connected, and on the other hand, the sources are connected to the reference potential point of the circuit via FETQ25 which receives the signal JP^. A power supply V, which will be described later, is connected to the power supply V via an FET which receives a chip non-selection signal CE on the other hand. Connected to P. The purpose of distributing the memory cells to the left and right around the pre-sense amplifier in this way is to increase the storage capacity and to speed up the operation of the pre-sense amplifier.
The purpose of this is to speed up information processing operations. Next, for convenience of explanation, only the data lines D4 and D4 of FIG. 1 and the related pre-sense amplifiers are shown again in FIG.
The circuit will be explained based on the diagram.

As shown in Figure 2, the Brisense amplifier uses a load FET.
A flip-flop circuit consisting of Q milk, Q23 and drive FETs Q22 and Q24, and a discharge FET provided between this flip-flop circuit and the ground terminal.
Q25 and a FET Q26 provided between this flip-flop circuit and the function source VoP, and the drain of the load FET is connected to the power supply V. . is connected to F for load.
The gates of ETQ2, Q23 and discharge FETQ25 are both connected to a drive signal source P^. The power source VoP generates approximately half the voltage of the power source Voo. The gate of the top FET Q26 connected to the power supply VoP is connected to the signal source CE which becomes a muddy bell when the chip is not selected. This FETQ26 is provided to prevent the flip-flop circuit from malfunctioning. One data line D4 connected to the flip-flop circuit is also connected to a main amplifier (not shown). Each is FETQ
■ and capacitor C, and FETQ3, and capacitor C2
A word selection signal is applied to word lines W5 and W6 connected to the gates of memory cells consisting of series-connected circuits. For example, the last word x is added to the word line W5. FETs Qphantom and Qcrab, which receive a chip non-selection signal at their gates, are connected between each data line ○4, D4 and the power supply VDP. With these FETs Q27 and Q28, when the chip is not selected (CE=high level), the capacitances (not shown) that exist between the data lines D4 and D4 and the reference potential point of the circuit are set to V, respectively. Precharged to P level. FET Q33 connected in series between the data line D4 and the reference potential point of the circuit and the data line D
FETQ connected in series between 4 and the reference potential point of the circuit.
34 and Q35 each constitute a dummy memory cell for applying a reference potential to the pre-sense amplifier. In the above dummy memory cell, when the chip is not selected, FETs Q3 and Q35 are turned on by the high level of the signal CE, so the capacitance (not shown) between FETs Q2 and Q34 and the reference potential point of the circuit is in a discharged state. be.

In the above circuit, when the signal CE becomes low level depending on the chip selection state, the FETs Q26, Q27, Q28, Q
3 and Q turbidity are in the off state.

After the signal CE goes low, the word line for the dummy cell connected to the data line paired with the selected word line and data line for the selected memory cell goes high. For example, if word line W5 is selected, the word line signal connected to FET Q34? o is at a high level. In this state, FETQ3. and Q
34 is turned on, and the status of the data lines ○4 and D4 is determined by the mutual relationship between the capacitance of the data line D4 and the capacitance C of the memory cell, and the mutual relationship between the capacitance of the data line D4 and the source side capacitance of the FET Q4 of the dummy memory cell. It is determined by the distribution of charge that occurs. 0. If the capacitor C, had stored a high level, the level of the data line D4 would be higher than the level of the data line D4 after the charge distribution.

The above capacity of the dummy cell is 4・more than the capacity of each memory cell.
Conversely, if the capacitor C had stored a low level, the drop in the level of the data line D4 would be greater than the drop in the level of the data line D4 due to the dummy cell, so the data line ○4 would be lower. The level will be lower than the level of ○4. When the signal ◇P^ becomes 0 high level following the high level of the signals Jx and 0o, the pre-sense amplifier becomes operational. In this state, FETQ2 and Q2
Due to the positive feedback effect caused by the mutual connection of the data lines, the difference between the two data lines is amplified, and the level of the data lines becomes the power supply Voo level or the reference level. The read signal amplified by the pre-sense amplifier of the data line D4 is input to the main amplifier. Similarly, the storage information can be read from the capacitor C2 of the memory cell connected to the data line D4 using a dummy cell consisting of FETs Q2 and Q33. In this case, data is read from the same data line D4 as above. By the way, the pre-sense amplifier described above performs the following undesirable operation when the signal P^ is applied. That is, while the sources g of the load FETs Q2, Q235 are at the VoP level in advance due to precharging for the data lines D4, D4, the source potential of the driving FET Q25 is at the reference potential (GND). The discharge FET Q25 is turned on earlier than the FETs Q2, Q23 by the drive signal ◇P^ which rises from the GND level to these FETs Q2, Q23, and Q25. Due to the preceding ON state of FET Q25, the precharge charges of both data lines D4 and D4 are simultaneously extracted. After that, F.E.
By turning TQ2, . For this reason, as shown in Figure 3, a period Δt occurs in which both data lines have a potential lower than the VoP level, and during this period it is not possible to supply a sufficient level signal to the main amplifier. becomes. Therefore, this was a factor causing a delay in access time. By the way, when the inventor calculated the above delay Δt for a 1-transistor RAM with a pine bit configuration, it was found that 2 times Se
It also became c. Therefore, an object of the present invention is to provide a sense amplifier that can contribute to high-speed information processing.

The present invention will be specifically described below along with examples and with reference to the drawings.

FIG. 4 is a circuit diagram showing an example of the sense amplifier according to the present invention, in which load FETQa, Q23 and drive FETQ
The flip-flop circuit consists of a flip-flop circuit made of Q and a discharge FET Q, and data lines D4 and D4 are connected to both output points, and further,
The configuration is exactly the same as that shown in FIG. 2 above in that it has a malfunction prevention FET Q26 and that each data line is provided with precharge FETs Q27 and Q28.

However, the load FETs Q2, . A drive signal ◇P^2 that rises from the VoP level to the Voo level is applied to the gate of Q23, whereas a drive signal that rises from the GND level to the Voo level is applied to the gate of the discharge FET Q25. OP^, is applied. According to the present invention as described above, the reason why the object is achieved can be understood from the voltage waveform diagram shown in FIG.

As shown in FIG. 5, after the word line selection signal ◇x rises, the pre-sense amplifier drive signals JP^,
and ◇P^2 will rise, but as mentioned above, the signal ◇P^, applied to the discharge FET Q25
rises from the GND level, whereas the signal applied to the load FETs Q2, , and Q of the flip-flop circuit
^2 will rise from the VoP level.

For this reason, this discharge FET and load FE
The gate-source voltage of T changes at an equal rate, and both FETs turn on almost simultaneously. Therefore, the flea pressures ya and Vb of the data lines ○4 and D4 produce a clear no-bell state immediately after the drive signal is applied (time et al.), and no waiting time is required as in the prior art. From the above, if the sense amplifier of the present invention is used, a dynamic memory with short access time and capable of high-speed information processing can be obtained.

Figure 6 shows the drive signal OP^ used for the above sense amplifier.
,,OP^2 is a circuit diagram showing an example of a circuit for generating FETs Q,,QJ as shown in the figure.
A flip-flop circuit consisting of skin driving FETs Q3 and Q5, and a first bootstrap circuit provided on the output side of this flip-flop circuit (FET Q driven by chip selection signal CE, capacitor C, chip non-selection) (consisting of a series connection circuit with FETQ7 driven by signal CE), load FETQ, Q,3, backflow prevention FETQ,Q,2, and bootstrap capacitance C2,C
A decoder selection signal Jdc is applied to the input side of the flip-flop circuit via a gate circuit FETQ2, and a decoder selection signal Jdc is applied to the input side of the flip-flop circuit. FETQ
, the chip non-selection signal CE is applied, the gate of the load FETQ is connected to the source of FETQ6 of the first bootstrap circuit, the output point of the flip-flop circuit is connected to the output point of the first bootstrap circuit, and , second
and the bootstrap capacitors C2 and C3 of the third bootstrap circuit, and F for one input of the flip-flop circuit and the input of the second and third bootstrap circuits.
Connect with the gates of ETQ,o,Q,4.

Drive signal ◇P from the output point of the second Pootstrap circuit
Assume that P^2 is extracted from the output point of the third bootstrap circuit with a drive signal. In addition, in the same figure, FETQ, . , Q, and 5 are for preventing malfunction. Further, in the above embodiment, all FETs are n-channel enhancement type 0 FETs. FIG. 7 is a voltage waveform diagram for explaining the operation of the above circuit. As shown in the figure, when the decoder selection signal ◇dc rises after the chip selection signal CE rises, the flip-flop circuit operates. , the output of the second bootstrap circuit ◇P^. GN
The voltage is raised from the D level to the Voo level, and the output P^2 of the third Pootstrap circuit is set to V.

It is caused to rise from the P level to the Voo level. Is the signal obtained by such a circuit the aforementioned driving signal? If used as P^,,guP^2, a predetermined effect can be obtained. The present invention can be widely used as a sense amplifier for dynamic memories.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the schematic configuration of a dynamic memory.
Figure 2 is a circuit diagram showing the configuration of a conventional sense amplifier; Figure 3 is a circuit diagram showing the configuration of a conventional sense amplifier;
The figure is a voltage waveform diagram for explaining its operation, Figure 4 is a circuit diagram showing the configuration of the sense amplifier of the present invention, Figure 5 is a voltage waveform diagram for explaining its operation, and Figure 6 is a voltage waveform diagram for explaining its operation. FIG. 7 is a circuit diagram showing an example of a generation circuit for forming the drive signal used, and FIG. 7 is a voltage waveform diagram for explaining the operation of the generation circuit. Q,~Q,7,Qa~Q3,...FET,C,~C4...
...Capacitor? P^・, ◇P^2... Drive signal, D, ~D4, D, ~D4... Data line, W,
~W,. ...Word line. Younger brother' figure Younger brother Z figure Tsutomu 3 figure 4 Younger brother's figure 6 Younger brother figure 7

Claims (1)

[Claims] 1 A sense amplifier has a flip-flop circuit consisting of an FET and a discharge FET connected in this order between a first power supply terminal and a second power supply terminal, and a data line is connected to both output points of this flip-flop circuit. In this circuit, the flip-flop circuit precharges both data lines to an intermediate voltage between the first and second power supply voltages when the sense amplifier is not in operation, and detects the potential difference between the two output points when the sense amplifier is in operation. The load FET of the circuit is driven to be on by a first signal rising from the intermediate voltage to the first power supply voltage, and the discharge FET is driven to the on state by a first signal rising from the intermediate voltage to the first power supply voltage. A sense amplifier, characterized in that it is driven to be turned on by a second signal that is directed to the first power supply voltage and rises substantially simultaneously with the first signal.