JPS60214266A - Signal storage device - Google Patents

Abstract

PURPOSE:To store an input signal roughly and also store respective aimed parts finely by storing the input signal in plural sub memory areas almost at the time point of the generation of each trigger signal according to a high-frequency clock signal. CONSTITUTION:An A/D converter 12 converts the input signal into a digital signal according to the high-frequency clock H; and the 1st memory 32 stores the signal when a low frequency clock L is generated and the 2nd - the 4th memories 34-38 store the signal when the high frequency clock H is generated. When a trigger circuit 14 generates the 1st trigger signal, a memory control circuit 40 stops the writing operation of the 2nd memory 34 a specific time later and then stops the writing operation of the 3rd and the 4th memories 36 and 38 a specific time after the 2nd and the 3rd trigger signals are generated. The memory control circuit 40, on the other hand, counts the low frequency clock L up to a specific number and then stops the writing operation of the 1st memory 32. Then, an MUX42 selects the 1st - the 4th memories during reading operation and a desired waveform is displayed on a CRT46.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal storage device that stores human input signals in a storage circuit in response to a clock signal.

[Background of the invention]

Signal storage devices include waveform storage devices (also known as transient digitizers, transient recorders, waveform digitizers, or digital onroscopes) and logic analyzers. A waveform storage device converts an analog input signal into a digital signal using an analog-to-digital (A/D) converter, stores this digital signal in a digital storage circuit (memory) in synchronization with a clock signal, and stores the stored digital signal. is converted into an analog signal using a digital-to-analog (D/A) converter. Note that the waveform storage device stores the analog input signal in synchronization with the clock signal.
There is also a type that stores data on an analog memory such as a CD. In addition, a logic analyzer stores logic (digital) signals in digital memory in synchronization with a clock signal, and in principle it is a waveform storage device, except for the A/D converter and D/A converter. is similar to These signal storage devices are very convenient because they can also store or measure input signals before the trigger signal is generated.

By the way, there are cases where it is desired to use these signal storage devices to measure in detail a portion of interest where a trigger signal occurs (for example, a portion where a transient occurs) while measuring the entire input signal. In this case, by lowering the clock frequency, the entire input signal can be stored in a memory with limited storage capacity. However, it is not possible to measure the part of interest in detail. Furthermore, if the clock frequency is increased, the part of interest can be measured in detail, but measuring the entire waveform requires a very large storage capacity.

[Prior art and its problems]

The conventional technology that cannot solve these problems is disclosed in Japanese Patent Application Laid-open No. 5
It is disclosed in No. 7-33363 or Japanese Unexamined Patent Publication No. 58-224498. If the signal storage device is a waveform storage device, this prior art stores the human input signal in the first memory according to the low frequency clock signal, and stores the input signal in the second memory according to the high frequency clock signal. Then, the trigger circuit counts a predetermined number of clocks from the focused part of the input signal (transient point), stops the 1-inclusive mode in the first and second memories, and roughly stores the entire input signal in the first memory. The transients of the input signal are stored in detail in the second memory.Therefore, the entire input signal can be measured, and the transients of the input signal can be measured in detail.

Incidentally, there are cases where it is desired to continuously store a plurality of intermittently occurring parts of interest using a signal storage device. Even in such a case, it would be very convenient to be able to measure a plurality of parts of interest as a whole and also to be able to measure each part of interest in detail. However, with the above-described conventional technology, only one part of the human input signal of interest can be stored, and the timing relationship between the contents stored in the first memory and the second memory cannot be accurately known.

Therefore, with this conventional technique, it is not possible to measure in detail each of a plurality of intermittently generated portions of interest of a human input signal, and to roughly measure the entire input signal.

The same problem arises when the prior art described above is applied to a logic analyzer instead of a waveform storage device.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal storage device that roughly stores the entire input signal including a plurality of parts of interest, and also stores each of the parts of interest in detail.

[Summary of the invention]

According to the signal storage device of the present invention, a predetermined amount of input signals after the trigger signal generation time are stored in the main memory area according to the low frequency clock signal, and the input signals after the trigger signal generation time are stored in the main memory area. A human input signal near the time point at which each trigger signal is generated after the time point is stored in each of the plurality of sub-memory areas in accordance with the high frequency clock signal. Therefore, the main memory area roughly stores the entire input signal including a plurality of parts of interest, and each of the sub memory areas stores each part of interest in detail.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention, in which the signal storage device is a waveform storage device. An analog input signal at an input terminal 10 is supplied to an A/D converter 12, and this analog input signal is supplied to a trigger circuit 14 to generate a trigger signal. This l/II circuit 14
As shown in FIG. 2, there is a comparator 18 that compares the input signal from the input terminal 10 and the 1-rega level from the potentiometer 16, and a comparator 18 that shapes the output signal of the comparator 18 into a waveform. It is composed of a waveform shaping circuit 20 which is a multivibrator. Therefore, trigger circuit 1
4. When the input signal exceeds the trigger level, a positive pulse (trigger signal) is generated.

The clock generator 22 includes a reference clock generator 24, which is a crystal oscillator, and a reference clock generator 24, as shown in FIG.
The frequency divider 26 divides the output signal of the frequency divider 26 to generate a plurality of divided outputs, and the multiple frequency divider 26 (MUX) 28 and 30 selects one of the plurality of output signals of the frequency divider 26, respectively. do. Note that the MUXs 28 and 30 may be controlled by external control signals, or a mechanical switch may be used instead of the MUX. The output end of MUX28 is designated as terminal H, the output end of MUX30 is designated as terminal 1]
The frequency of the clock signal at the terminal is always higher than the clock signal at the terminal.

The A/D converter 12 converts the analog input signal from the terminal 10 into a digital signal according to the high frequency clock signal from the clock generator 22, and transfers this digital signal to the first memory 32, second memory 34, and third memory. 36 and a fourth memory 38. The first memory 32 serves as a main memory area, and the second to fourth memories 34 to 38 serve as sub memory areas. These memories 32-38 are, for example, random access memories (RAM). The memory control circuit 40 receives the trigger signal from the trigger circuit 14 and the low frequency clock signal and high frequency clock signal from the clock generator 22, and generates address signals etc. for the memories 32 to 38.
The write and read operations of these memories 32 to 38 are controlled. MUX 42 selects one of the read output signals of memories 32 to 38 in response to a control signal from memory control circuit 40 and supplies it to D/A converter 44 . This D/A
A converter 44 converts the digitized human signal back into an analog signal and supplies it to vertical deflection means of a display 46, for example a cathode ray tube (CRT). On the other hand, the D/A converter 48 converts the horizontal address signal synchronized with the read address from the memory control circuit 40 into a staircase wave signal, and converts the horizontal address signal synchronized with the read address from the memory control circuit 40 into a staircase signal as a time axis signal.
Supplied to the horizontal deflection means of RT46.

Next, the operation of FIG. 1 will be explained with reference to the waveform diagram of FIG. 4. In a write operation, the memory control circuit 40
2 to 38 are placed in write mode, and the chip select (Cl3) terminal of each memory is enabled. The control circuit 40 also generates address signals for the first memory 32 in response to the low frequency clock signal from the clock generator 22, and generates address signals for the second to fourth memories 34 to 38 in response to the high frequency clock signal H. generates an address signal. Note that these address signals are circular address signals depending on the storage capacity of the memory, and the address signals for the memories 34 to 38 may be common. As mentioned above, the A/D converter 12
converts the analog input signal I from the input terminal 10 into a digital signal in response to the high frequency clock signal [1]. However, since the low frequency clock signal is synchronized with the high frequency clock signal H, the first memory 32 sequentially stores the digital signals at the time when the low frequency clock signal is generated. on the other hand,
The second to fourth memories 34 to 38 store digital signals at the time when the high frequency clock signal H is generated. Since the address signal is a circular signal, when the tental signal is stored at all addresses in the memory, the oldest (first stored) digital signal is sequentially updated with the new digital signal.

When the trigger circuit 14 generates the first trigger signal at time T2, the memory control circuit 40 begins dividing the high frequency clock signal H. When the control circuit 40 finishes dividing the predetermined number of high-frequency clock signals H at time T3, it stops enabling the chip select terminal of the second memory 34, that is, stops the write operation of the second memory 34. Therefore, the second memory 34 stores time points T1 and T determined by the relationship between this counting operation and the storage capacity of the memory 34.
The digital values of the input signals between 3 are stored. Similarly, when the trigger circuit 14 generates a second trigger signal at time T5, the memory control circuit 40 stops the write operation of the third memory 36 at time T6. The third memory 36 thus stores the digital value of the input signal between times T4 and T16. Also, the trigger circuit 14 is activated at time T8.
When the second trigger signal is generated, the memory control circuit 40 stops the write operation of the fourth memory 38 at time T9.

The fourth memory 38 thus stores the digital value of the input signal between times T7 and 19.

Meanwhile, the memory control circuit 40 starts counting the low frequency clock signals in response to the trigger signal at time T2. Then, when the control circuit 40 asks for a predetermined number of sets of low frequency clock signals at time TIO and ends,
The high-pull of the chip select terminal of the first memory 32 is stopped, that is, the write operation is stopped.

Therefore, the first memory 32 performs this counting operation and the memory 32
The digital value of the input signal between the time TO and T10 determined in relation to the storage capacity of is stored. Therefore, the first memory 3
2 roughly stores the entire input signal including a plurality of parts of interest (transients), and the second to fourth memories 34 to 38
Each of them memorized each noteworthy part in detail. Note that the control circuit 4o operates at the trigger time T2. The address of the first memory 32 and the addresses of the second to fourth memories 34 to 38 at T5 and T8 are stored. ``In a read operation, if it is desired to display the entire input signal on the display 46, the MUX 42 selects the first memory 32 in response to a control signal from the memory control circuit 40. Finally, the control circuit 40 puts the first memory 32 in a read mode, generates a read address signal in response to a predetermined read clock signal, and supplies it to the first memory. This read address signal reads the oldest stored content of the first memory 32 at the first level of the above-mentioned time axis (horizontal) signal. Therefore, the display 46
The entire input signal is roughly displayed.

Note that the time axis signal is synchronized with the read operation of the memory. In addition, if you want to display only a specific part of interest in detail, the MUX 42
Instead of simply selecting a desired one from among them and reading out the stored contents of the selected memory in the same manner as described above, the present invention allows simultaneous measurement of the entire stored input signal and of the part of interest in detail. To avoid this, the memory control circuit 40 first checks the address of the first memory 32 at each trigger time and the address of the memory 34 at each trigger point.
~38 storage capacity at time T1. , T3. T4.
T6° Calculate the addresses of the first memory 32 corresponding to T7 and T9. The control circuit 40 generates the time axis signal T from the portion corresponding to the time point TO, and the MUX 42 generates the first signal T.
The memory 32 is selected. The MUX 42 selects the second memory 34 when it corresponds to time TI, selects the first memory 32 when it corresponds to time T3, selects the third memory 36 when it corresponds to time T4, and selects the 17th memory when it corresponds to time T6. memory 32 is selected, and when corresponding to time T7, the fourth memory 38 is selected, and when corresponding to time T9, the first memory 32 is selected.
Select. Then, when corresponding to time TIO, the time axis signal T ends, and the above-described operation is repeated again from time TO.

That is, the digital values of the input signals between time points TO and T1, between time points T3 and T4, between time points T6 and T7, and between time points T9 and T10 are read from the first memory 32,
The digital value of the input signal between time points T4 and T3 is read from the second memory 34, the digital value of the input signal between time points T4 and T6 is read from the third memory 36, and the digital value of the input signal between time points T7 and T9 is read from the second memory 34. Read from memory 38. Therefore, the entire input signal can be roughly measured, and only the portion of interest can be measured in detail.

Next, an example of the memory control circuit 40 that controls the memories 32 to 38 and the MUX 42 as described above will be described. Fifth
The figure is a block diagram of the write control section of the control circuit 40, and FIG. 6 is a block diagram mainly centered on the read control section. The entire writing and reading operations are controlled by an arithmetic and control unit 50 shown in FIG. This device 50 is composed of a microprocessor, a read-only memory that stores programs for the microprocessor, a random access memory that operates as a temporary storage device, and a keyboard for making various settings. , bus 52
is connected to.

When the start of the write mode is input from the keyboard of the arithmetic and control unit 0, the D-type flip-frog 5 shown in FIG.
4 to 64 are reset by the device 50 (control lines for reset are not shown). Control signals from device 50 also cause MUX 66 to select address counter 68 and MUX 70 to select address counter 72. Additionally, the device 50 places the memories 32-38 in a write mode;
A predetermined number of seven steps is applied to delay counters 74 and 76 (control lines are not shown).

Since delay counter 74 is not enabled and its output is at a "high" level before the trigger signal is generated, address counter 68 is enabled to count the low frequency clock signal from clock generator 22 and generate an address signal. do. This address signal is supplied to the address terminal of the first memory 32 via the MUX 66. On the other hand, the address counter 72 counts the high frequency clock signal H from the clock generator 22, generates an address signal, and supplies this address signal to the address terminals of the memories 34-38 via the MUX 70. Since the capacities of memories 34 to 38 are equal,
Common address signals can be used.

Note that the address signals from counters 68 and 72 are circular signals. By the way, the "high" level outputs from the OR gates 77-82 are supplied to the chip select terminals of the memories 32-38, respectively.
8 is operating in write mode.

When the trigger circuit 14 generates the first trigger signal at time T2, the Q output of the Frisogge flop 54 goes high and the delay counter 76 is reset and begins counting from the beginning.

On the other hand, at time T2, the launch circuit 84
The latch circuit 86 latches the address signal for the second
~Latch the address signals for the fourth memories 34-38. Still, the Q output of fringe flop 54 enables delay counter 74 to begin operating on the low frequency clock signal, and AND gate 88 is enabled. At time T3, when delay counter 76 has counted a predetermined number of clock pulses, the output signal of counter 76 is passed through AND gate 88 to flip-flop 60.
clock. Therefore, the output of the flip-flop 60 goes to a "low" level, stopping the operation of the second memory 34 via the OR gate 78. Therefore, the second
The memory 34 stores, for example, the digital value of the input signal 2 between time points T1 and T3, which is determined by its storage capacity and the set value of the counter 76.

Similarly, when trigger circuit 14 generates a second trigger signal at time T5, the Q output of flip-flop 56 goes to +d r high level, pulling AND gate 90 high. The end counter 76 is reset again and starts a new count.

Chips 84 and 86 each latch a corresponding address signal. At time T6, when color/return 76 has counted a predetermined number of clock pulses, its output signal clocks flip-frog 62 via ant gate 90. Therefore, the output of the flip-flop 62 stops the operation of the third memory 36 via the OR gate 80. The third memory 36 thus stores the digital value of the input signal between times T4 and T6.

At time T8, when trigger circuit 14 generates a third trigger signal, the Q output of flip-flop 58 enables cyand gate 92 and counter 76
The beam is set and a new count is made. On the other hand, latch circuits 84 and 86 latch their respective address signals. At time T9, when counter 76 has counted a predetermined number of clock pulses, flip-flop 64 is
clocked by the output of gate 92;
2, the operation of the fourth memory 38 is stopped.

The fourth memory 38 thus stores the input signals between times T7 and T9. On the other hand, at time TIO, when the delay counter 74 has counted a predetermined number of clock pulses, its output goes to the "I" level and the operation of the first memory 32 is stopped via the OR gate 77. Thus, the first memory 32 stores the input signals between the times TO and T10.

Next, the read operation of the memory control circuit 4° will be explained mainly with reference to FIG. The arithmetic and control unit 50 has memories 32 to 38
is placed in read mode, and the chip select terminal of each memory is enabled via OR gates 77-82. Additionally, MUX 66 and 70 are also switched. Clock generator 9
4 generates a read clock signal, and color/receiver 96 counts this read clock signal. This count output (address signal) causes the D/A converter 48 to generate a time axis signal T, so that the minimum count value and the maximum count value are displayed on the display 46.
corresponds to the left and right edges of the screen.

Note that the time point to which the address signal from the counter 96 corresponds is different from the address of each memory corresponding to this time point, and in order to make these addresses correspond to each other, an offset corresponding to the address of each memory at the end of the write operation is required. Please note that this is necessary. Therefore, the arithmetic control device 50
are the times TI, T3 based on the addresses latched by the latch circuits 84 and 86 at each trigger time, the values of the counters 74 and 76, the storage capacities of the memories 32 to 38, etc.
．． T4, T6. 'Counter 9 corresponding to T7 and T9
6 and calculates the address from time T3. The addresses from the counter 68 (addresses for the first memory 32) corresponding to T6 and T9 are calculated.

When the address of counter 96 corresponds to time TO,
The arithmetic and control device 50 stores the first memory 3 corresponding to the time point To.
2 is loaded into address counter 9B, and the address of counter 96 corresponding to time TI is loaded into register 1.
Load to 00. In addition, D type flip-flop 10
2 and 104 are reset, AND gate 106 is enabled and AND gate 108 is not enabled. Thus, address-counter 98 begins counting the clock signals from clock generator 94 that have passed through AND gate 106. In addition, at this time M
Since the UX 42 has selected the first memory 32, the time T
After O, the digital values of the corresponding input signals are sequentially supplied from one memory to the D/A converter 44. Additionally, the arithmetic and control unit 50 loads the address of the second memory corresponding to the time T1 into the address counter 110, and loads the address of the counter 96 corresponding to the time T3 into the register 112.

Digital comparator 114 is connected to counter 96 and register 10.
Comparing the output signals of 0 and detecting that the address of counter 96 corresponds to time T1, comparator 114 locks flip-flops 102 and 104, and MU
X42 selects the second memory 34. Since the Q output of flip-flop 102 goes to a "low" level, AND gate 106 closes and color/return 98 stops counting. Also, the Q output of flip clock 104 goes high, AND gate 108 opens, and address counter 110 begins counting from the address of second memory 34 at time TI. On the other hand, the arithmetic control unit 50 loads the address of the 17th memory 32 corresponding to the time T3 into the counter 98, and loads the address of the counter 96 corresponding to the time T4 into the register 00. Digital comparator 116 includes counter 96 and register 112.
counter 96 corresponding to time T3.
, it resets flip-flops 102 and 104 and resets flip-flops 118-1.
Clock 22.

Thus, the AND gate 106 opens and the address counter 98 generates the address of the first memory 32 after time T3, and the AND gate 108 closes and the address counter 110 stops counting. On the other hand, the Q output of the flip-flop 118 changes, and the MUX 42 outputs the first memory 3.
Select 2. Therefore, the digital value of the input signal after time T3 is supplied from the first memory 32 to the D/A converter 44. Next, the arithmetic and control unit 50 controls the third
The address of memory 36 is loaded into address counter 110 and the address of counter 96 corresponding to time T6 is loaded into register 112.

Similar operations are performed thereafter, and at time T4, the address signal from the counter 110 is supplied to the third memory 36 in accordance with the output signal of the comparator 114, and the MUX 42
Select memory 36. Then, the address of the first memory 32 corresponding to time T6 is loaded into the counter 98, and the address of the counter 96 corresponding to time T7 is loaded into the register 1.
Load to 00. At time T6, comparator 116 generates an output signal, counter 98 starts counting, and a change in the Q output of flip-flop 120 causes MUX4 to
2 selects the first memory 32. Furthermore, the address of the fourth memory corresponding to time T7 is loaded into the counter 110,
The address of counter 96 corresponding to time T9 is loaded into register 112. Thus, at time T7, address counter 110 begins dividing and MUX 42 selects fourth memory 38. Next, the first one corresponding to time T9
The address of memory 32 is loaded into counter 98. At time T9, address counter 98 begins counting and MUX 42 selects first memory 32. When the arithmetic and control unit 50 detects the address of the counter 96 corresponding to the time TIO, it returns to the state of the above-mentioned time TO and repeats the above-described operation. Note that since the oscillation frequency of the clock generator 94 is low, there is no problem with the above-described loading operation.

Although the above describes only preferred embodiments of the invention,
It will be understood by those skilled in the art that various modifications can be made without departing from the spirit of the invention. For example, in the above embodiment, the signal storage circuit was a waveform storage circuit, but the logic
It may be applied to analyze and the. In this case, the A/D converter and the D/A converter may be removed and the trigger circuit may be a word recognizer (detects a predetermined digital word from the input digital signal). Further, an external trigger signal and an external clock signal may be used, or a shift register may be used in the storage circuit. Further, the number of the plurality of sub-memory areas may be any desired number, and each sub-memory area may not be used as each memory element, but a plurality of sub-memory areas may be provided in a single memory element.

In this case, the addresses of the memory elements are divided into multiple groups, and each group is specified by the upper bits of the address signal.
Addresses within each group may be specified using lower bits of the address signal. To avoid this problem, it is convenient for the write operation to prepare a counter for upper bits that counts the trigger signal as a clock and a counter for lower bits that counts the high frequency clock signal. Also, in the read operation, the upper bits and lower bits of the address signal may be generated separately.

〔Effect of the invention〕

As described above, according to the present invention, the entire input signal including a plurality of portions of interest can be roughly stored in the main memory area, and each of the portions of interest can be stored in detail in a plurality of sub-memory areas. It is also possible to roughly reproduce the entire input signal using the main memory area, and replace only the portion of interest with a signal that is finely reproduced using the sub memory area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred embodiment of the present invention, FIG. 2 is a block diagram showing an example of the trigger circuit used in FIG. 1,
3 is a diagram showing an example of the clock generator used in FIG. 1, FIG. 4 is a waveform diagram for explaining the present invention in detail, and FIG.
6 are block diagrams showing an example of the memory control circuit of FIG. 1. FIG. In the figure, 32 is a main memory area, 34 to 38 are sub memory areas, and 40 is a memory control circuit.

Claims (1)

[Claims] a clock generator that generates a high frequency clock signal and a low frequency clock signal, a main memory area, a plurality of sub memory areas, and a clock generator that generates a high frequency clock signal and a low frequency clock signal; In addition to storing the input signal in the memory area, the input signal near the trigger signal generation time point and each trigger signal generation time point after the trigger signal generation time point is stored in each of the plurality of sub-memory areas in accordance with the high frequency clock signal. A signal storage device comprising a memory control circuit.