JPS60214135A - Supervisory circuit of spare line - Google Patents

Abstract

PURPOSE:To obtain an economical spare line supervisory circuit with simple circuit constitution by converting an N-line AMI coded bipolar signal into an NRZ signal, comparing N-sets of the NRZ signals mutually and using a compared output to detect a line fault. CONSTITUTION:Output NRZ signals 27-1-27-N of N-set of AMI coding/decoding circuits 1-1-1-N inputting N-set of identical consecutive zero suppressing and converting bipolar signals 20-1-20-N and converting the AMI coded bipolar signals into the NRZ signals are inputted to a comparator circuit 32. The circuit 32 compares mutually the N-set of the NRZ signals to obtain an error inforamtion signal 42, which is inputted to a line fault detection circuit 33. The circuit 33 discriminates whether or not the identical N-set of spare line signals are transmitted based on the signal 42 or supervises the quality of spare lines and outputs a line fault detecting signal 43.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a protection line monitoring circuit that monitors a protection line in a line switching system in wireless digital transmission.

(Prior Art) FIG. 1 is a block diagram of an example of a conventional protection line monitoring circuit.

The positive polarity codes of consecutive zero suppression permutation encoded bipolar signals (hereinafter referred to as bipolar input signals) 20-1 to 20-N in N columns are determined by positive polarity discriminating circuits 10-1 to 10-H as RZ ( Return-to-Ze-ro) signals 21-1 to 21-N. The negative polarity signs of the bipolar input signals 20-1 to 20-N in the same column N are determined by the RZ signals 22-1 to 22-N by the negative polarity discrimination circuits 11-1 to 11-N.
22-N. Positive and negative polarity discrimination circuits 12-1 to 12
-N is the two-column ORZ signal, that is, the positive polarity discrimination circuit 1
R2 signals 21-1 to 21-N of 0-1 to 10-N and negative polarity discrimination circuits 11-1 to 1l-N (7) RZ signals 22-1 to
22-Nt Convert to i-column OR2 signals 23-1 to 23-N. That is, bipolar input signals 20-1 to 20-
N rectified waveform ti. RZ signals 23-1 to 23-Nc,
NRZ by 1/2 frequency divider circuits 14-1 to 14-N
(Non-R-eturn-Zero) signal 25
-1 to 25-N. NRZ signal 25-1~2
5-N is converted by delay circuits 15-1 to 15-N into NRZ signals 26-1 to 26-N, which are υ bipolar input signals 2°-1 to 20-N and are delayed by one bit. The phase comparator circuits 16-1 to 16-N receive the NRZ signals 25-1 to 25-2.
5-N and the NRZ signal 26-1~ delayed by 1 bit
26-N and output signals 27-1 to 27-2.
7-N'. The above is an example of the operation of a conventionally well-known bipolar input signal-NRZ signal conversion circuit.

However, since the output signals 27-1 to 27-N are converted into NRZ signals even as replacement signals for continuous zero suppression replacement,
The resulting signal is different from the original signal on the transmitting side.

On the other hand, the replacement information detection circuits 13-1 to 13-N receive the RZ signals 21-1 to 21- of the positive polarity discrimination circuits 10-1 to 10-N.
N, negative polarity discrimination circuit 11-1 to 1l-NORZ signal 22
-1 to 22-N, the replacement information of the continuous zero suppression replacement code is detected 5, and the replacement information signals 24-1 to 24-Ne are sent out. Consecutive zero suppression permutation code decoding circuits (hereinafter referred to as code decoding circuits 9117-1 to 17-N)
~24-Nt-based on phase comparison circuits 16-1 to 16-N
The output signals 27-1 to 27-Nt are decoded into original signals. The comparison circuit 32 includes N code decoding circuits 17-1 to 17-N.
The output signals 28-1 to 28-Nf are used as input signals, and by comparing them with each other, a mismatch between the input signals of the comparison circuit 32 is detected, and an error information signal 42fc is obtained. Based on this error information signal 42, the line fault detection circuit 33 determines whether or not the same protection line signals of N columns are being transmitted to the protection line, or monitors the quality of the protection line to detect a line failure. A signal 43 is output.

In addition, in FIG. 1, from the positive/negative polarity determination circuit to the phase comparison circuit, excluding the replacement information detection circuit, AMI (A
1 ternate -Mark -Invers 1
on) encoded bipolar signal k NRZ (Non −
AMI to convert to Return-Z-ero) signal
It constitutes code/decoder circuits 1-1 to 1-N.

As described above, the conventional protection line monitoring circuit decodes the bipolar input signal into the same signal as the original signal on the transmitting side, and detects all line failures based on the decoded signal.

Therefore, a code/decoding circuit is required to decode the signal into the same signal as the original signal on the transmitting side, which has the disadvantage that the circuit configuration becomes complicated and the circuit size increases.

(Object of the Invention) An object of the present invention is to provide an economical protection line monitoring circuit with a simple circuit configuration using a conventional AMI code decoding circuit by eliminating the above-mentioned drawbacks.

(Structure of the Invention) The line failure detection circuit of the present invention includes N AMI code decoding circuits that receive N (N22) consecutive zero suppression permutation coded bipolar signals and convert them into AMI coded bipolar signals eNRZ signals; Comparing the NRZ signals of the columns with each other 1
The circuit includes a comparison circuit, and a line failure detection circuit that detects a line failure from the output signal of the comparison circuit.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

This embodiment inputs N (N22) zero consecutive suppression permutation encoded bipolar signals 20-1 to 20-N, and outputs an output signal 27- as an AMI encoded bipolar signal '&NRZ signal.
N AMI code decoding circuits 1- to convert into 1 to 27-N
1 to 1-N and the output signal 27 as an NRZ signal of N columns
-1 to 27-N, one comparison circuit 32 and an error information signal 42 which is an output signal of this comparison circuit 32.
The line failure detection circuit 33 detects a line failure and outputs a line failure detection signal 43.

That is, in this embodiment, in the conventional example shown in FIG.
Replacement information detection circuit 13- for decoding the signal into the original signal
1 to 13-N and code/decoding circuits 17-1 to 17-N are omitted, and only conventional AMI code/decoding circuits 1-1 to 1-N are provided.

Therefore, positive pole discrimination circuits 10-1 to 10-N, negative pole discrimination circuits 11-1 to 11-N, and positive and negative pole discrimination circuits 12-1 to 12
-N, 1/2 frequency divider circuit 14-1 to 14-N, delay circuit 1
The operations of phase comparator circuits 5-1 to 15-N and phase comparator circuits 16-1 to 16-N are the same as in FIG.

The input signal of the comparison circuit 32, that is, the phase comparison circuit 16
Since the output signals 27-1 to 27-N of -1 to 16-N have not been decoded by the code/decoding circuit, they are decoded into signals different from the original signals on the transmitting side. However, even if the same bipolar input signals of N columns are decoded by the conventional AMI code decoding circuit without replacement information of the zero consecutive suppression replacement code, there are differences in the decoded signals 27-1 to 27-N between the N columns. does not occur at all, resulting in the same decoded signal.

The comparison circuit 32 outputs N columns of output signals 27-1 to 27-Nt.
By using the signals as input signals and comparing them with each other, an error information signal 42 is obtained as in the conventional example. Based on this error information signal 42, the line failure detection circuit 33 determines whether or not the same protection line signal in N columns is being transmitted, or monitors the quality of the protection line, and outputs a line failure detection signal 43. Output.

(Effects of the Invention) As described above in detail, the protection line monitoring circuit according to the present invention has the same function as the conventional one without the conventional zero consecutive suppression permutation code decoding circuit, so the circuit size can be reduced. This has the effect of realizing a protection line monitoring circuit with an economical and simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional protection line monitoring circuit.
FIG. 2 is a block diagram of one embodiment of the present invention. 1-1 to 1-N...AMI code decoding circuit, 1
0-1~10-N...!・Positive polarity discrimination circuit, 11-1
~11-N...Negative polarity discrimination circuit, 12-1~12
-N...Positive/negative polarity discrimination circuit, 13-1 to 13-N
...Replacement information detection circuit, 14-1 to 14-N.
...1/2 frequency divider circuit, 15-1 to 15-N...
... Delay circuit, 16-1 to 16-N ... Phase comparison circuit, 17-1 to 17-N ... Zero continuation suppression replacement -1 to 25-N, 26-1 ~26-N, 27-1~
27-N, 28-1 to 28-N...Signal, 31
...timing black, extraction circuit, 32...
... Comparison circuit, 33 ... Line fault detection circuit,
41, 42, 43... Signal.

Claims (1)

[Claims] N AMI code decoding circuits that receive N (N≧2) columns of consecutive zero suppression permutation encoded bipolar signals and convert the AMI encoded bipolar signals into NRZ signals;
1. A protection line monitoring circuit comprising: a comparison circuit for mutually comparing Z signals; and a line failure detection circuit for detecting a line failure based on the output signal of the comparison circuit.