JPS60214042A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To easily obtain high function by composing a microprocessor of plural function blocks in hierachical structure divided by functions. CONSTITUTION:The operation code field and operation objective field of a machine instruction code is provided with hierachical structure respective, and the microprocessor is composed of plural function blocks 23, 23- in hierachical structure divided by functions. Further, a black code bus for transmitting codes for identifying those function blocks 23, 23-, a command bus for transmitting indication codes for operations of the function blocks 23, 23-, a communication bus for transmitting input data or output data of the blocks 23, 23-, and a bus driver group are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic processing device such as a highly functional microprocessor.

[Technical background of the invention]

FIG. 1 is a block diagram showing the general configuration of a conventional microprocessor. In the figure, 1 is an external address bus, 2 is an external data bus, 3 is an external control bus, 4 is an internal data bus, 5 is a machine instruction bus, 6 is a bus control logic circuit group, 7 is an address register file, and 8 is a An instruction register, 9 an instruction decoder, 10 a micro operation sequence control logic circuit, 11 a data register file, and 12 an arithmetic unit (ALU). In such a configuration,
The instruction register 8 takes in instructions from the external data bus 2 via the machine instruction word bus 5. The instruction taken into the instruction register 8 is decoded by the instruction decoder 9, and the decoding result is provided to the micro operation sequence control logic circuit 10. This micro operation sequence control logic circuit 10
is from a PLA (programmable logic array) etc. that generates micro operation commands, and the micro operation commands sequentially generated here control the bus control logic circuit group 6, address register file 7, instruction register 8, instruction decoder 9, and data register. File 11 and ALU 12
operation is controlled. The ALU 12 receives data via the internal data bus 4 under the control of the micro operation sequence control logic circuit 10, performs various arithmetic processing on the data, and outputs the data to the internal data bus 4 again.

Furthermore, in the conventional microprocessor, the machine instruction word taken into the instruction register 8 is composed of an operation code field 21 and an operation target field 22, as shown in FIG. Assigned horizontally to the code table. Moreover, regarding the operation target field 22 that is the target of the operation,
Physical objects such as immediate values, registers, or addresses of areas where data to be operated are stored are written, and the bit pattern of the machine instruction word expressed by these is extracted from the data register file 11. This is decoded by the instruction decoder 8.

[Problems with background technology]

When a conventional microprocessor with the configuration shown in FIG. The function of a machine instruction is attempted to be performed relatively brute force by the instruction decoder 9 and the micro-operation sequence control logic circuit 10.

As a result, there is no hierarchical classification by function, and the logic of the instruction decoder 9 and micro operation sequence control logic circuit 10 is created in an extremely sophisticated manner in order to reduce the chip size. Instead, it takes more time and money to expand and modify functions than necessary. In particular, it is difficult for people other than the author to understand, it is difficult for organizations and society to accumulate the technology, and it is difficult to understand even though it is a well-known technology, so it is easy to be perceived as if it was an originality. However, the disadvantage is that it hinders the development and spread of technology.

In addition, in order to achieve higher functionality, the transmission and reception of control signals between the micro operation sequence control logic circuit 10 and other parts becomes overcrowded, and the length of wiring within the chip and the area occupied by the wiring increase. Put it away. In order to achieve even higher functionality, PLA constituting the micro operation sequence control logic circuit 10
It has the disadvantage that it becomes huge, making it difficult to arrange each part and interconnect them. Moreover, the individual random logics that directly control each part must be newly modified each time a microprocessor with new functions is designed and manufactured, resulting in a significant loss of time and cost.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to easily construct a highly functional product, reduce development time and cost, and at the same time The object of the present invention is to provide a highly reliable, low-cost arithmetic processing device that can avoid overcrowded wiring, is easy to test, and is highly reliable.

[Summary of the invention]

In order to achieve the above object, the present invention provides a hierarchical structure for the operation code field and the operation target field of the machine instruction code, and corresponds to this by functionally decomposing the microprocessor into a plurality of hierarchically structured Consisting of functional blocks, there is a block code path that transmits the code that identifies the functional block, a command path that transmits the instruction code for the operation of the functional block, and communication that transmits the input data or output data of the functional block. Nogs, their current status that should be notified to other functional blocks, and the reception of commands connect upper-level and lower-level functional blocks with a path group consisting of status paths through which the status is transmitted, and further communicate with the above bus group. A path driver group consisting of a block code path driver, command path driver, communication bus driver, and status path driver that exchanges code or data with the outside is provided, and when integrating these into one chip, the above four drivers are The functional blocks at the highest level are placed adjacent to the command path driver and block code path driver, and the upper level functional blocks are placed at the periphery of the chip on each of the four sides of the chip. and place their immediate lower-level functional blocks sequentially inside the chip, with the lowest-level functional blocks placed in the center of the chip, and the upper-level functional blocks and the lower-level functions they use. The above-mentioned bus groups are placed between the blocks in a direction that extends along the four sides of the chip, and the bus groups related to the upper level are brought closer to the periphery of the chip, and the bus groups related to the lower level are brought closer to the center of the chip. I'm trying to place it.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. An arithmetic processing device, such as a microprocessor, according to the present invention has an operation code field and an operation target field of a machine instruction word arranged in a hierarchical structure as shown in FIGS. 3 and 4, respectively. In other words, the operation code field is separated into n levels of functional hierarchy from the highest level 1 to the lowest level n, as shown in Figure 3, and the operation target field is also divided into levels as shown in Figure 4. As shown, the levels are separated to have n gutter structure levels from the highest level 1 to the lowest level n. Accordingly, from a functional point of view, the main body of the microprocessor is composed of a plurality of functional blocks 23, which have a hierarchical structure as a whole and have a number of levels corresponding to the levels of the operation code field, as shown in FIG. As shown in FIG. 6, the object 24 also has the number of levels corresponding to the level of the field to be operated, and has a hierarchical structure as a whole.

Figure 7 shows the operation code field shown in Figure 3 and the
The structure of one machine instruction code that combines the operation target fields shown in the figure is shown. These instruction codes include a task level operation code 31, a lower control structure level operation code 32, a lower level operation code 33, and a lower level operation code 33. Operation code field 2 consisting of 34
and an operation target field 22 consisting of task level data 35, control condition data 36 at a lower level, operation target data 37 at a lower level, and lower level data 38 at a lower level. It consists of In other words, the machine instruction code in FIG.
The generalized operation code shown in FIGS. 3 and 4 is for the case where n is 4 in the field to be operated,
Level separation is performed at four levels: task level, control structure level, calculation level, and lower levels.

FIG. 8 is a block diagram specifically showing one of the plurality of functional blocks 23 that are level-separated as shown in FIG.

On the input side of this functional block 230, an operation command decoder 41 having an input/output interface function with an upper level functional block is provided. This decoder 41 and upper level functional blocks are block code bus 42.
, a command bus 43, a communication path 44, and a status signal 45-1). A code for identifying a functional block is transmitted to the block code 0 bus 42. An instruction code for instructing the operation of the functional block identified by the identification code is transmitted to the command bus 43.

The communication log 44 is transmitted with input data to be input to the functional block and output data to be output from the functional block. The status path 45 transmits the current status of the block itself to be notified to other functional blocks and the status of command reception. The operation command decoder 41 decodes the codes and data output from the upper-level functional blocks and transmitted via the buses 42 to 45, and also decodes the codes, codes, and data stored in the circuit to be operated, which will be described later. Output to upper level functional block.

Further, this functional block 23 is provided with an operation target circuit 46 and an operation logic circuit 47.

The operation target circuit 46 is a memory circuit such as a register, latch, or counter, and the operation logic circuit 47 is an AND, O
R, NOT, NAND, NOR, EX-OR
(exclusive OR) and other combinational circuits of dart circuits. The operation logic circuit 47 includes the decoder 4
In response to the decoding output of No. 1, data is read from the decoder 4, the data is manipulated, and the result of the manipulation is written to the circuit to be manipulated 46. In addition, the operation target circuit 46 and the operation logic circuit 47 are used for task 2 control, task delay, task selection, task control, task delay, task selection,
If any one of the other task processes is executed and the function block is at the control structure level, LOOP,
CASE, WHEN, IF ~TI(EN
Executes any one of NELI, subprogram call, and other processing, and if that functional block is at the operation level, executes one of the operations such as addition and subtraction, and that functional block is at the lower level. In the case of level, execute the processing at the level below the operation.

Further, on the output side of each functional block 23, an output signal synthesizer 48 having an input/output interface function with lower level functional processors and controllers is provided. The output signal synthesizer 48 and lower level functional blocks include a block code path 49, a command bus 50, and a communication path 51 corresponding to each of the buses 42 to 45.
and a status bus 52. This output signal synthesizer 48 synthesizes the code and r-signal for the lower level functional block and outputs it to each of the paths 49 to 52, and is also output from the lower level functional block and transmitted through each path 49 to 52. Capture code and data.

FIG. 9 shows a microprocessor according to an embodiment of the present invention, which is constructed using a plurality of functional blocks having the structure shown in FIG. In the figure, No. 6 is the operation command decoder 4.
1. The operation target circuit 46, the operation logic circuit 47, and the output signal synthesizer 48 are first level (for example, task level) functional blocks. The (kth
-1) level functional blocks (not shown). Further, the function block 61 at the above-mentioned th level is connected to the (k+1)th level via a bus group 63 for the lower level and a bus group 64 for the upper level of the (k+1)th level.
+1) level i functional blocks 65□ to 651 are connected. The function block 6 at the above-mentioned level uses the i function blocks 651 to 65i at the (k+1)th level, which is a directly lower level, as necessary, and uses the details of its own processing functions to integrate these functions. Block 65□
~65 amounts can be performed.

Furthermore, the (k+1)th level functional block 65
One functional block 65□ among □ to 65i connects to the (k+2)th level directly below it via a bus group 66 for the lower level and a bus group 67 for the upper level of the (k+2)th level. ) level /I- (for example, calculation level) t functional blocks 68□ to 68t. Another function block 65 at the (k+1)th level is connected to the U functions at the (k+2)th level via a bus group 66 for the lower level and a bus group 67 for the upper level of the (k+2)th level. It is coupled with blocks 69□ to 69u. That is, the two sets of functional blocks 681 to 6 at the (k+2)th level
8t.

691 to 69u are the upper level functional blocks 65
．． ．． This is used when the 65i executes the details of its own processing functions.

Furthermore, the above (k+1)th level functional blocks 65□~
65i is coupled to two functional blocks 711.71□ via bus group 64 and bus group 70 to its upper level, and these two functional blocks 711.71'
l is the (k+1)th level functional block 65□ to 65i
commonly used for

In such a configuration, various codes and data are supplied from the outside to the functional blocks 6 at the second level via the bus group 62. In this functional block 61, in response to the decoded output of the operation command decoder 48, the operation target circuit 46 operates under the control of the operation logic circuit 47 to perform a predetermined process. The data decoded by the decoder 4 is used. Also, this functional block 61
When it is necessary to use a lower level functional block in executing processing in the output signal synthesizer 48, various codes and data for the lower level are synthesized.

The code and data synthesized here are bus group 63.6.
4 through the 1st. +1) level is supplied in parallel to i functional blocks 65□ to 65i. Among these i functional blocks 651 to 65i, a functional block is identified by an identification code transmitted on a block code path, and is classified as an operation target circuit and an operation logic circuit according to a code transmitted on a command path. Predetermined processing is executed. The processing results are then supplied to the functional block 6 at the second level via bus groups 64 and 63. Further, the (k+1)th level functional blocks 65□, 6
51, when it is necessary to use a lower level functional block, each output signal synthesizer synthesizes various codes and data for the lower level, and combines this with the (k+2)th level function block. Blocks 681-68t.

691 to 69u in parallel. After this, the (k+
2) A specific functional block at one level executes predetermined processing, and the processing results are supplied to the functional blocks 65□, 651 at the upper level. Also, the (k+1)th
The functional blocks 65□ to 651 of a level are the common functional blocks 71. ,．． 712 as needed to perform that level of processing (correct utilization of common blocks makes the hierarchical structure more effective). In this way, a certain required function is realized by a collection of functional blocks having a hierarchical structure at different levels.

That is, in the microprocessor according to the above embodiment, the operation code field has a hierarchical structure, the microprocessor itself is also functionally decomposed to form a hierarchical structure, and an instruction decoder is provided on the input side of the functional block at each level. It is designed to perform the operations required within the system.

For this reason, there are drawbacks to increasing the functionality of conventional microprocessors, which are configured using simple machine instruction codes, such as overcrowding of the control section and unstructured data representation, which is an obstacle to creating advanced systems. It is possible to avoid forcing

Top-down recursive functional decomposition is still required when forming a huge system as a super LSI, and future C
This point is particularly important in AD, and as shown in FIGS. 5 and 6, the functional blocks and operation objects have a hierarchical structure, so this point is also satisfied.

One of the methods for analyzing and designing more complex system requirement specifications is 5ADT (Struct.
Tured Analysis and Design
In addition, there is a composite design method summarized by IBM's Myers. The microprocessor of the present invention is extremely compatible with the upstream process of such system development, and when operated in a highly reliable system description language such as Ada II, it can be used with the Ada description model shown in FIG. Both agree well.

In FIG. 10, 91 is a task level function, 92 is a control structure level function, 93 is an operation level function,
This example shows a real-time parallel operating environment for controlling the frequency of a generator, where two tasks within this module can be selected and executed from other tasks. Furthermore, it can be expected that object program generation, which is the output of Ada's computer program, will be performed efficiently and safely.

Therefore, with the microprocessor of the above embodiment, a highly functional one can be easily constructed, development time and cost can be reduced, and since the instruction decoding function is not concentrated in one place, Tight wiring can be avoided, testability is easy, reliability is high, and price can be reduced.

FIG. 11 is a layout diagram showing the structure of a chip when the microprocessor shown in FIG. 9 is actually integrated into one chip. This chip has an external block code bus of 10
1, an external command bus 102, an external communication path 103, and an external status bus 104. In addition, each peripheral part on the four sides of the chip includes a block code bus driver IQ5, a command bus driver 106, and a communication path driver 107, which are connected to each bus of the external bus group.
and status bus driver 108 are arranged. Each of the above bus drivers 105, 106, 107, 108
Inside each of the external buses 101, 102, 103.
A bus group 109 consisting of an internal block coat bus, command bus, communication bus, and status bus corresponding to 104 is arranged so as to go around the chip. Furthermore, among the functional blocks at each level, the one at the highest level is basically the outermost one (periphery of the chip).
The lowest level one is placed in the innermost area (in the center of the chip). That is, first, the highest level 10 functional block 11θ is placed near the professional code bus driver 105 and the command bus driver 105 in order to issue commands to the entire chip. Level 20 function block 111 used by this level 1 function block 110
~114d, between level 1 and level 2 (7) The fock code nozzle, command bus communication path, and status bus are connected to the level 10 function block 110 via the terminal bus 7j4115. Furthermore, inside one level 2 function block 111 are two level 3 function blocks 116 and 117 that are directly used by this function block 111, and inside the function block 112 are two level 3 function blocks 116 and 117 that are directly used by this function block 112. Inside the function block 113 are two level 3 function blocks 120 and 121 that are directly used by this function block 113.
Level 3 function blocks 122 that are directly used by this function block 114 are arranged inside It fo and Ri J J 4, respectively. In addition, the above functional block 110
Inside are the above level 2 function pockets 111 to 114.
Functional blocks 123 and 124 that are commonly used are arranged.

The level 2 functional block 11 and the level 3 functional blocks 1'16 and 117 are connected by a bus group 125 provided between them. The level 2 functional block 112 and the two level 3 functional blocks 118 and 119 are connected by a bus group 126 provided between them. The level 20 function block 113 and the two level 3 function blocks 120.
121 are connected by a bus group 122 provided between them. Functional block 114 of level 2 above
and level 30 function block 122 are connected by a bus group 128 provided therebetween. Inside the two level 3 function blocks 116 and 117, there are four level 4 function blocks 129 and 130°131.1.
32 are arranged, and these 404 functional blocks are arranged such that the functional block 129 is the level 30 functional block 11.
6, the functional block 130 is adjacent to each of the two level 3 functional blocks 116 and 117, the functional blocks 131 and 132 are adjacent to the level 3 functional block 117, and the functional block 129 is located in the center of the chip. be arranged to be located. Four level 4 function blocks 133, 134, 135, 136 are arranged inside the above two level 3 function blocks J 18 and 119, and these four level 4 function blocks are such that the function block 133 is level 3 adjacent to the functional block 119 of
Function block 134 is two function blocks 1 of level 3
Adjacent to each of functional blocks 18 and 119 are functional blocks 135 .
1367bX adjacent to level 3 functional block 118;
In addition, the functional block 133 is arranged at the center of the chip. Above level 30 two functions p2ri1
Four level 40 function blocks 137, 138, 139, and 140 are arranged inside 20 and 121, and these four level 40 function blocks are such that the function block 132 is adjacent to the level 30 function block 120, and the function block 138 is adjacent to the level 30 function block 120. Level 30 is arranged so that it is adjacent to two functional blocks 12θ and 12, respectively, functional blocks 139 and 140 are adjacent to functional block 121 of level 3, and functional block 137 is located at the center of the chip. A level 4 functional block 141 is placed inside the level 30 functional block 122, and a level 5 functional block 142 is placed inside this level 4 functional block 141, and this functional block 142 is located at the center of the chip. It is arranged so that it is located in the section. Above level 3
function block 116 and level 4 function block 129
and are connected by a bus group 143 provided between them. The level 3 functional block 117 and the three level 4 functional blocks 130, 131 and 132 are connected by a bus group 144 provided between them. The level 3 functional block 118 and the two level 4 functional blocks 135 and 136 are connected by a bus group 145 provided between them.

The level 3 functional block 119 and the two level 40 functional blocks 133 and 134 are connected by a bus group 146 provided between them. The level 3 functional block 120 and the two level 4 functional blocks 132 and 138 are connected by a bus group 147 provided between them. The level 3 function block 121 and the level 4 two function blocks 139,
140 are connected to each other by a bus group 148 provided therebetween.

The level 3 functional block 122 and the level 4 functional block 141 are connected to a bus group 149 provided between them.
further connected to level 4 functional block 14
1 and a level 50 functional block 142 are provided therebetween. 42 groups 150. The block code bus (command bus), communication bus (command bus), communication bus, and status bus constituting each of the above bus groups are arranged in directions parallel to the four sides of the chip, respectively, as shown in the figure. In this manner, this microprocessor has a systematic hierarchical structure in which functional blocks at each level are arranged within the chip along with a group of buses at each level. By configuring the chip in this way, the area occupied by the bus group is minimized, and rational chip size and high-speed operation can be achieved.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, the machine instruction code is composed of the operation code field 2 and the operation target field 22 as shown in FIG.
As shown in the figure, a task level machine instruction code 203 consisting of a task level operation code 201 and task level data 202, a control structure level machine instruction code 206 consisting of a control structure level operation code 204 and control condition data 205, and an operation level operation Operation level machine instruction code 209 consisting of code 207 and operation target data 208, lower level operation code 210 and lower level data 21
1 by the lower level machine instruction code 212 consisting of 1
The machine instruction code may be configured as one machine instruction code. In addition, the level separation does not necessarily have to be of the four types described above; in short, the structure of the machine instruction code is such that the structure of the system description language used and the hierarchical structure of the functional blocks in the microprocessor are well matched. I wish it were possible.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily construct a highly functional product, reduce development time and cost, avoid overcrowded wiring, and test It is possible to provide an easy-to-use, highly reliable, and low-cost arithmetic processing device'.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the general configuration of a conventional microprocessor, Figure 2 is a diagram showing the configuration of a machine instruction word used in a conventional microprocessor, and Figure 3 is a machine instruction word used in the present invention. FIG. 4 is a diagram showing the configuration of the operation target field, FIG. 5 is a diagram showing the general configuration of the arithmetic processing device of the present invention, and FIG. 6 is a diagram showing the configuration of the operation target field. 7 is a diagram showing the configuration of one machine instruction code used in the device of the present invention, FIG. 8 is a diagram specifically showing the configuration of one functional glock in FIG. 5, FIG. 9 is a diagram showing a microprocessor according to an embodiment of the present invention using the functional blocks of FIG. 8, FIG. 10 is a diagram showing an Ada description model used to explain this invention, and FIG. 9th
FIG. 12 is a layout diagram showing the structure of a chip when the microprocessor shown in the figure is integrated into a single chip, and FIG. 12 is a diagram showing the structure of another machine instruction code corresponding to FIG.

Claims (3)

[Claims] (1) The operation code field of the machine instruction code has a hierarchical structure of requested functions, and the operation target field has a corresponding hierarchical data structure, and the fields corresponding to each level of the hierarchical structure are a plurality of functional blocks that are respectively provided and configured to form a hierarchical structure as a whole; a block code bus that is provided to connect each of the functional blocks and transmits a code for identifying the functional blocks; A command bus through which instruction codes for the operation of the functional blocks are transmitted, a communication bus through which input data and output data of the functional blocks are transmitted, the current state of the functional blocks to be notified to other functional blocks,
1. An arithmetic processing device comprising a bus group consisting of a status bus for receiving instructions and transmitting status. (2) The operation code field of the machine instruction code has a hierarchical structure of requested functions, and the operation target field has a corresponding hierarchical data structure, and the field corresponds to each level of the hierarchical structure. A block code bus is provided to connect each of the functional blocks and to transmit a code for identifying the functional blocks. , a command line through which the instruction code for the function block's operation is transmitted, a communication path through which the input data and output data of the function block are transmitted, the current state of the function block that should be notified to other function blocks, and the state in which commands are accepted. A bus group consisting of a status bus for transmitting information, and a block code (pass driver, command bus driver, communication bus driver,
When integrating these into a single chip, each of the four bus drivers of the status driver group is arranged on each peripheral part of the four sides of the chip, and each of the above functional blocks is The highest-level functional blocks are placed adjacent to the command bus driver and block code bus driver, and the upper-level functional blocks are placed on the periphery of the chip, and their directly lower-level functional blocks are placed inside the chip. The functional blocks at the lowest level are arranged sequentially in the center of the chip, and the above bus groups are arranged parallel to the four sides of the chip between the functional blocks at the upper level and the lower level functional blocks used by this functional block. What is claimed is: 1. An arithmetic processing device characterized in that the busses associated with the upper level are arranged closer to the periphery of the chip and the buses associated with the lower level are arranged closer to the center of the chip. (3) Each of the functional blocks includes a decoding means for decoding the codes and data transmitted through the bus group, an operation target means for realizing the required function of the corresponding level, and an operation logic means for controlling the operation target means. 2. The arithmetic processing device according to claim 1, wherein the arithmetic processing device comprises: and a signal synthesizing means for synthesizing codes and data to be supplied to lower-level functional blocks.