JPS6021087A - Address generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an address generation circuit, and particularly to an address generation circuit for a display memory of a raster scan type display device.

[Prior art]

Conventionally, access to the display memory of a two-star scan type display device is often performed using the DMA (Direct Memory Access) method, in which the start address to start accessing and the length of the memory address to be accessed are specified. In doing so, a series of consecutive addresses become accessible. However, when accessing a small area set in the display memory, the memory addresses are discontinuous, so with the normal DMA method, it is not possible to access all addresses consecutively in time. However, each time the addresses became discontinuous, it was necessary to reset the DMA start address length with the help of a microprocessor or the like. As a result, memory access operations tend to be discontinuous, creating additional costs.

[Purpose of the invention]

The object of the present invention is to set the length M of the memory address per raster at the first address A11 of the memory address, the length m of the memory address in the raster direction of the memory area to be accessed,
By setting the number n of rasters in advance, addresses of the memory areas expressed by A, m, and n can be generated sequentially in time, so that the addresses can be stored in the display memory of the raster scan type display device. An object of the present invention is to provide an address generation circuit that enables high-speed access to a certain time-determined area.

[Structure of the invention]

According to the present invention, among the memory walls of M columns and N rows to which consecutive addresses 0 to MXN-1 are assigned, the M.

When setting a memory space of m rows and n columns with values m and n smaller than N by determining a starting address A, registers holding the values of A, M, m, and n, m,
m rows n including a control circuit that generates a control signal to control addition and subtraction based on the value of n, an addition/subtraction circuit that performs addition or subtraction based on the control signal, and a memory address register that holds the operation result. An address generation circuit is obtained which is characterized in that it continuously generates addresses of column memory spaces in time.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Assume that there is a raster scan type display device and that it has display memory for the display screen. (The size of the display memory is generally larger than or equal to the width of the display screen.) As shown in Figure 1, the size of the display memory is N rows and N columns (-rows are 1 17 (, , a small area of m rows and n columns with A as the starting address is set up in the display memory. At this time, A, , m.

The value of n determines a unique small area within the display area of M rows and N columns.

The present invention relates to an address generation circuit that continuously generates memory addresses for this small area in time.
The figure shows a block diagram of an embodiment of the present invention.
, m , and n register 1゜2.3.4
and a circuit that generates a constant +1 5. A small memory of m rows and n columns held in a register 1 consisting of an adder circuit 6, a memory address register (MAR) 7, and a control circuit 8 that generates a control signal based on the values of m and n. The start address A of the area is passed through the adder circuit 6 and set in the memory address register (MAR) 7 to generate the memory address of the time chart shown in FIG. In order to perform the operation, the side division circuit 8 selects the JJn arithmetic circuit 608 input from the output of the register 1 or the tu power of the memory address register 7, and sends the signal a%B input to the register 2 and register 3 constant circuits. Select signal 1) from 5), pulse signal to set memory address register 77 C1 Select input of register 1 from external or output from memory address register 7 (pulse signal to set jl and z raster 1t) e is generated at the valley unit timing.

Next, to briefly explain the unit timing in the time chart of FIG. 3, first, at unit timing 1, the A input of the adder circuit 6 is selected from register 1,
B input is not given and register 1 is not set. At the next unit timing 2, the output of the memory address register 7 is selected as the A input, and the output of the constant circuit 5 is selected as the B input.
output is selected and register 1 is not set.

At this time, A+1 is set in the memory address register 7. Thereafter, the address is incremented in the same manner until unit timing m, and at unit timing m, the memory address register 7 is A+m-1.

At the next unit timing m+l, the output of register 1 is selected as the A input, the output of register 2 is selected as the B input, and register IFi is not set. At this time as well, the memory address register 7 becomes A0M. At the next unit timing m + 2, the A input again selects the output of the memory address register 7, and the B input selects the output of the constant circuit 5, but at this time, the input of the register 1 selects the output of the memory address register 7, Register 1 is set due to set pulse e, and memory address register 7 is A0M+1.
However, register l changes to A+M.

After the next unit timing m+2, register 1 is not set again, and memory address register 7 is incremented until unit timing 2m. When the unit timing reaches 2m, the eight-person power is register 1 (the contents at this time are A+M).

The B input selects the output of register 2, and memory address register 7 becomes A+2M.

In the next unit timing '2 m -1-1, m+
1, register 10 is also set, and the resultant memory address register 7 is A+2M+1. Register 1 is A
+2M. Thereafter, the memory address register 7 is incremented up to nm.

In this way, by generating control signals up to unit timing mn, memory addresses are generated as shown in FIG.

〔Effect of the invention〕

According to the present invention, it is possible to continuously access some areas of a 5-star scan type display memory at high speed without intervention by a host device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a display memory, FIG. 2 is a block diagram of an embodiment of an address generation circuit of the present invention, and FIG. 3 is a time chart of generated memory addresses. 1 to 4...Register for holding the values of A, M, m, and n, 5...Constant circuit, 6...Addition/subtraction circuit, 7... Memory access register, 8
...control circuit. Bamboo l Figure 3

Claims (1)

[Scope of Claims] In a memory space of M columns and N rows to which consecutive addresses 0 to MXN-1 are assigned, m and n are smaller than JN, respectively.
When setting a memory space of m rows and n columns having
, a register holding the value of n, and m. A control circuit that generates a control signal to control addition and subtraction based on the value of n, an addition and subtraction circuit that performs addition or subtraction based on the control signal, and a memory address and
1. An address generation circuit comprising a register and continuously generating addresses in a memory space of m rows and n columns.