JPS60205639A - Address stopping circuit - Google Patents

Abstract

PURPOSE:To define optional addresses as stop addresses at the same time by reading an instruction in an address where a stop is expected to be made, writing a parity bit and detecting a parity error, and the generating a stop signal. CONSTITUTION:Instructions are read out of program memory 1 with a step operation signal l when a program which uses 1 as an address stop ready signal (m) is executed. Read data (g) is sent to a parity checking circuit 4 and when it is defined as a stop address, a parity error signal (h) goes up to 1. The signal lis 0, so the parity error signal (h) is sent to an FF7 and stored at the rise of a read signal (i) and a stop signal (j) is outputted. Further, the signal l is 1 and the stop signal (m) is 1 in step operation; when an instruction is read out, the parity error signal (h) holds the stop signal (j) at 1 without fail, thereby stopping the execution of the program. When a restart signal (k) is generated, the program is executed by one step.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to program-controlled equipment, particularly to an address stop circuit for an information processing apparatus.

Description of the Prior Art Conventionally, an address stop circuit compares an address register that stores an address to stop execution of a program with the execution address of the program and the content stored in the address register, and when they match, stops the execution of the program. It is generally comprised of a comparator circuit that generates a stop signal to stop the motor.

However, in the case of the above configuration, in order to be able to define a plurality of stop addresses, the same number of address registers and comparison circuits as the number of addresses to be defined are required, which has the disadvantage of being expensive.

Purpose of the Invention The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a novel address stop circuit that does not require an address register or a comparison circuit, and can simultaneously define any address as a stop address. be.

Structure of the Invention In order to achieve the above object, an address stop circuit according to the present invention includes a program memory which is rewritable and has a parity bit, a parity generation circuit which can control a generated parity signal, and a parity signal read from the program memory. a parity error signal that checks the validity of the data and generates a parity error signal in the event of an abnormality, and a storage circuit that stores the parity error signal;
The present invention is characterized in that a program execution stop address is defined as data in which a parity error occurs in the program memory.

3. Detailed Description of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an address stop circuit according to the present invention. In the figure, one embodiment of the present invention includes a program memory 1 that is rewritable and has parity pits, a parity generation circuit 2, and a first
an OR gate 3, a parity check circuit 4, a second OR gate 5 that ORs the parity error signal and the step mode signal l, and a memory circuit (flip 70 block) 7.
, and an AND gate 6 which calculates the logical sum of the restart signal and the negative logic of the address stop enable signal m.

The operation of setting the first K1 stop address will be explained.

The stop address is set by once reading the contents of the address to be set and rewriting the same contents. That is, when setting a stop address, the stop address set mode signal d is set to "φ", and when rewriting, a write address signal, write data b, and a negative logic write signal C are applied from the outside. At this time, the stop address set mode signal d is "1".
Therefore, the parity generation mode signal e connected to the parity generation circuit 2 is the same as the write signal C.

The parity generation circuit 2 is configured so that the parity generation mode signal e is “
If the parity generation mode signal e is 1, an even parity is generated, and if the parity generation mode signal e is 1, an odd parity is generated as the parity signal f. For this reason, when the stop address set mode signal d is "indicator", the parity signal f generated as an odd parity is written into the program memory IK. That is, when the instruction at the address defined as the stop address is read out, it is written so that it becomes parity 2-.

Next, the operation during program execution will be explained.

First, when executing a program in which the step operation signal l is set to "■" and the address stop enable signal m is set to "1", the first
The instruction is read from program memory 1. At this time,
Address signal a as a read address and negative logic read signal 1 are externally applied. The read data g, which is an instruction read from the program memory 1, is
At the same time as being sent to the outside, it is sent to the 1-parity check circuit 4. At this time, if the address is not defined as a stop address, the parity error signal becomes "1", and if it is defined as a stop address, the parity error signal becomes "1".

As mentioned above, since the step operation signal l is the mark, the same signal as the parity error signal is connected to the storage circuit (7 lip-flop) 7, and is stored in the 7 lip-flop 7 at the rising edge of the read signal 1, and the chip is stopped. It is output as signal j.

The next VC% restart signal is a negative logic pulse signal, and when the restart signal is generated, the memory circuit (flip 70 tube) 7 is reset, and the program does not stop until the next instruction defined as the stop address is read. is executed.

Next, the step operation will be explained. In the case of a step operation, the step operation signal l is "1" and the address stop enable signal m is "1". Since the parity error signal outputted from the parity check circuit 4 is ORed with the step operation signal l and the second OR gate 5, when an instruction is read out, the stop signal j is always output. The program stops execution each time an instruction is read. Therefore, when the restart signal k is generated, the program is executed one step.

Next, if the address stop enable signal m is active, the memory circuit (flip 70 block) 7 is always reset, so the stop signal j is "φ", and the program is executed without stopping. .

Effects of the Invention As described above, according to the present invention, the operating mode of the parity generation circuit is controlled, a parity bit is written so that a parity error occurs when an instruction at an address to be stopped is read, and a parity error is detected. In some cases, instead of generating a stop signal, any number of addresses can be defined as stop addresses, and an address stop circuit that does not require an address register or a comparison circuit can be constructed.

In addition, program execution will also stop if a parity error occurs due to an abnormality in the program memory.
The original parity check function is not lost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Program memory, 2... Parity generation circuit, 3... First OR gate, 4... Parity check circuit, 5... Second OR gate, 6... Logic Product gate, 7...Memory circuit (flip-flop), a
...Address signal, b...Write data, C...
・Write signal, d: Stop address set mode signal, e: Parity error signal, f: Parity signal, g: Read data, h: Parity error signal, 1: Read signal , j...Stop signal, k...
...Restart signal, l...Step mode signal, m
...Address Stop Signal Patent Applicant NEC Corporation Representative Patent Attorney Yutabe Kumagai

Claims (1)

[Claims] A program memory that is rewritable and has a parity pit, a parity generation circuit that can control the generated parity signal, and a parity generation circuit that inspects the validity of data read from the program memory and generates a parity error signal in the event of an abnormality. and a storage circuit that stores the parity error signal, and is characterized in that a program execution stop address is defined as data at which a parity error 2- occurs in the program memory. Address stop circuit.