JPS60202596A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and particularly to a memory array configuration method suitable for high integration and low power consumption.

[Background of the invention]

As semiconductor memory devices become more highly integrated and have larger capacities in the future, it will become increasingly difficult to design them with sufficient consideration given to lower power consumption.

FIG. 1 shows the configuration of a conventional semiconductor memory device. Memory cells MeFi word lines W0 to W and data lines. - They are arranged in a matrix at the intersection of D3. In this configuration, the read operation is performed as follows.

When an external address signal Pt o "" A s is input, an X decoder (XDEC) is determined. As a result, for example, when word *Ws is selected, the X driver (
XDRV) outputs a selection pulse to word 11Ws, and each data line D0~ is output from the memory cell connected to this.
A readout signal is applied to D. On the other hand, the Y decoder (Y
Data line by DEC). Suppose that D is selected.

The signal read out passes through the switch Y
It is output to the 0 line and the data is output. 1t and is output to the outside. In writing, the data input Dtm is sent to the I10 line, the switch YGO, and the data HDo by the write control signal WE, and data is written into the memory cell MC connected to the intersection with the selected word line W. Here, timing generation circuit TM is generated by clock φ.
Various internal timings are generated from GI and TMG2, and various circuit operations are controlled. Further, in the figure, AR indicates a memory array k, and CHIP indicates the entire chip.

Now, in the conventional configuration shown in FIG.
8) The entire data line, from the connection point with the switch YG to the farthest end, is also involved in the read or write operation of the memory cell connected to the memory cell, and the entire data line is charged and discharged as the memory operates, resulting in lower power consumption. There was a problem from the viewpoint of reducing power consumption.

[Object of the Invention] An object of the present invention is to provide a memory array structure that improves the conventional memory array structure described above and can reduce power consumption.

[Summary of the invention]

To achieve the above object, the present invention divides a data line into a plurality of parts using a switch, and separates the data line part that does not form the access path of a selected memory cell from the access path by opening and closing the switch. This makes it possible to reduce power consumption.

[Embodiments of the invention]

The present invention will be explained in detail below with reference to Examples.

FIG. 2 shows an embodiment of the present invention, which corresponds to a part of the memoriano of the conventional configuration shown in FIG. In this embodiment, the data line is divided into two by the data at switch SW, and the connection switch YG to the I10 line among the divided data lines is
The first data # part (Dot, Dot
-Dt, Ds+) is selected, the switch SW is turned OFF, and the second data diverter (Do., Dl., D, ., D, .) is selected. Data line part (Dolls DII+I)
Separate from HI I)81). On the other hand, if the memory cell connected to the second data line is selected,
The switch SW is in the ON state, and the switch SW and YG
%- through which the selected memory cell and I10 line are connected. According to this embodiment, when the memory device connected to the first data input section as viewed from the switch YG is selected, the data line capacitance that is charged and discharged during memory operation is cut off by turning the switch 8W'k OFF. Data section (
Doo, D+o, Dao, Dao), and the power consumption can be reduced accordingly. In other words, when the data line is divided into two parts by the switch SW as shown in FIG. Compared to this, when word mWo7 or W is selected, it is equal to the conventional example, and as a result, the average consumption due to charging and discharging of the data line '
The power consumption can be increased by 3/4 times compared to the conventional example. Although FIG. 2 shows the case where one switch SW is provided and the data line is equally divided into two, the switch f n−
One data line may be provided, and the data line 't-n may be divided (it does not have to be equally divided). In that case, the memory cell located in the m-th data line portion as seen from the switch YG among the divided data lines is selected. Similarly, the time is m- as seen from switch YG.
The switches 8W'k up to the first scan should be in the ON state, and the m-th switch should be in the OFF state. Accordingly, average power consumption 1≦n≦(number of memory cells connected to one data line).

FIG. 3 shows another embodiment of the present invention, in which the memory array is equally divided into memoria V- and the divided memory arrays (A Ra,
This is an example in which the present invention is applied to the case where memory cells are operated in A Rb ).

As shown in the figure, data # is divided by switch SW and 8Wb in the memory array. In such a configuration, a connection switch (YG,
), when operating the memory cell connected to the second data line portion (D, .), the first data line portion (Db+) in the other memory array (ARb) is operated.
operate the memory cells connected to it. In this case, the switch (SW, ) dividing the data line in the former memory array <'A Ra ) is set to ON state, and the switch (SWb) of the latter memory array is set to OFF state. According to this embodiment, since the data line portion (D, or Dbn) is always disconnected in either memoria V-, the power consumption is reduced by 3/4 compared to the conventional method of charging and discharging the entire data line. It can be reduced by 2 times. Further, in the embodiment shown in FIG. 2, the average power consumption can be reduced, but in this embodiment, even if an arbitrary memory cell is selected, the power consumption can always be 3/4 times that of the conventional method. In addition, in Fig. 3, the data of each memory array? When the number of memory cells connected to each part of the data line divided equally by the fIij switch is equal, the power consumption can always be increased by 31374 times compared to the conventional method even if any memory cell is selected.

FIG. 4 shows another embodiment of the present invention, in which the data line shown in FIG. 3 is further divided into four equal parts, and the selected word line is divided into four parts. Table 1 shows the relationship between the states of each switch.

Blank columns can be either ON or OFF. According to this embodiment, power consumption can be reduced by 5/8 times compared to the conventional method in any case shown in the table. Similarly, if the data line is divided into n equal parts by a switch, the memory cell connected to the m-th data m part in one memory array as seen from the connection switch with the I10 line, and the memory cell connected to the m-th data m part in the other memory array V-. (n+1-
m) It is possible to operate the memory cell connected to the e-th data line portion. Also, set the m-th switch of the former memory array V- and the (n+1-m)-th switch of the latter memory array to the 't-0FF state, and connect the switch on the connection switch side to the I10 line from these switches to both memory arrays. Turn both V- and ON. As a result, power consumption can always be reduced by a factor of two compared to conventional methods.

n Although the concept of the present invention has been shown above using several examples, below, in order to explain the present invention more specifically,
An embodiment using a one-transistor MOS memory configured with n-channel MO8) transistors will be described.

FIG. 5 shows memory cells (folded bitlinearr) in which data pairs D are laid out close together.
FIG. 6 shows a more detailed example of FIG. 5. That is, in FIG. 5, the data pair # is taken as D Io and D to by the switch sw.

(2) An example of division into (i=0 to n in the figure) is shown.

In this configuration, when a memory cell connected to the divided data line portion D1° or DIG is selected, the X decoder (XDEC) turns on the switch 8VION.
state, the read signal voltage from the memory cell is amplified by the differential amplifier circuit SAK, and this amplified signal is input to I1 by the signal line YC controlled by the X decoder (YDEC).
Readout to the 0 line is controlled. Similarly for write operation, data input from outside the chip is I10 line, YG.

D++ (or E) is written to the selected memory cell through 8W. On the other hand, Data Ivi! Partial DI
When a memory cell connected to I or FiI)tt is selected, the XDEC sets it to 5Wt-OFF state, disconnects Dto and Dto'r, and performs a memory operation. This operation will be explained in more detail using FIGS. 6 and 7. First, the precharge signal φP and the signal φa't controlling the switch 5Wt which divides data m are both set to a high level (V+α), and the data pair 1jDoo, Do is output from the precharge circuit pc-. and Dot, D.
Precharge to a certain level V. At the same time, the node in the dummy cell DM is set to the ground potential (Va8). Then, after the φP value has been lowered, if the Qv level of the memory cell MCk begins to rise now, φG′l
1-XDEC to separate Mr. Do09 from 8.■T. Word l1ljlWk is selected by XDEC and word pulse φW is applied, and dummy word line DW is selected by XDEC and dummy word pulse φDW is applied. As a result, a signal voltage is outputted from the memory cell in equation (2), and a reference signal voltage is outputted from the dummy cell in (2)=, and a minute differential signal is generated between Do, D, and π. After that, the starting pulse φa't-falls and SA
' to amplify the above differential signal. At this time, the switch 8Wfl is in the OFF state, so Do. ,D
π is maintained at the precharge level Vt-. After that, a pulse φ is output to YCo selected by YDEC,
The amplified differential voltage is taken out to line I10 via switch YGt-.

When selecting memory cell MCIk, signal φG is kept at a high level (V+α) (indicated by a dotted line in FIG. 7). In this case, take D0°. l is also connected to the shadow and the picture, DlM-0, DOQ or , , D,
, is discharged to ground potential.

The signal φG for controlling the switch SW can be easily controlled by using, for example, the upper bit of the address signal input to the X decoder that selects the word line.

According to this embodiment, when the memory cells connected to the data line portions D11 and Dtl are selected, the data line portions D11 and Dtl. Since 5DIO can maintain a precharged state even during memory operation, the data line capacitance to be charged and discharged can be reduced compared to a conventional example without a switch SW. Reducing the data line capacitance to be charged and discharged not only reduces power consumption, but also reduces noise caused by the peak value of the power supply current or the coupling between the board and the data line.

Furthermore, power consumption when inverting and writing memory cell information can be reduced.

In FIGS. 5 and 6, the dummy cell DM and the differential amplifier 5At-I2O3 are arranged near the connection switch YG, but they may be arranged near the switch SW, for example. It is sufficient if it is placed between SW and YG.

Further, the data line precharge circuit PC may be placed on the side of the beam, , or U hole.

Figure 8 is a specific example of Figure 3 using two intersection cells.
．． The structure and operation of each memoria V- divided into 11 is the same as that shown in FIG. 5, FIG. 6, and FIG. As explained in FIG.
Alternatively, memory cells connected to each other and Dbs1 t
The memory cells b or Dbst are operated, φG is kept at a high level, and φah is lowered to the ground potential. On the other hand, D a 11 or a tile π memory cell and Dbs.

Alternatively, the memory cell of Kaoru is operated, φG is lowered to the ground potential, and φabk is kept at a high level. In the 1-transistor MO8 memory, as shown in this embodiment, the memory array may be divided due to refresh cycles, S/N, etc., and each memory cell may be operated in the divided memoria V-. According to an example, the data line capacitance to be charged and discharged can be reduced, and the reduction can be made equal regardless of which memory cell is selected. Although FIG. 8 shows an example in which two sets of l101i)f are provided, this need not be two sets and may be one set, four sets, or any other set.

FIG. 9 shows another embodiment of the present invention. In the embodiment shown in FIG. 8, the differential amplifier circuit 8A, dummy cell DM, and data line precharge circuit are arranged on the switch SW side, and these circuits and It has a configuration in which switches XG and Gbk are added between the memory cell and the memory cell. By adding this switch, for example, Dl. Or switch XG during the read operation of the memory cell connected to Dalg.

'1 OFF state (switch SW is ON as mentioned above)
state), and after amplifying the signal voltage by 8A,
t” ON state. On the other hand, Il or FiD,...
FiXG during read operation of memory cells connected to
, remains ON (8W, is OFF). X G
The operation of b is similar. According to this embodiment, the effect shown in FIG.
A read signal voltage equivalent to that of the memory cell connected to □Da++ * Di+ll IDbu can be obtained.

FIG. 10 shows another embodiment of the present invention, in which the data line high potential compensation circuit I (STt
- An example of addition is shown. This R8TH1 for example l5
8CC' 81 Technical DigestP
, 85, and after signal amplification by 8A, compensates the level of the data line on the high potential side and obtains a sufficient rewrite voltage. As shown in the 10th color, R8T is the 8A described above in Figures 5 and 6.
Similarly, it is placed between 8W and YG. Also this)L
In the method of precharging the data line between the rewrite voltage obtained by ET and the ground potential, it is also possible to omit the dummy cell DMk.

Although the embodiments described above from FIG. 5 to FIG. 10 have been described with respect to the case where the precharge levels of each divided data line portion are equal, the precharge level of each data H portion may be different. Examples are shown below.

In Fig. 11, the data line portion D0°, ■ B is the potential V.

, Do, Dot t Vt (V o > V t )
An example of precharging is shown below. Figure 12 shows memory cell M.
When C,i is selected, FIG. 13 shows the operating waveform when MCk is selected. The read signal voltage obtained when MCIk is selected is smaller by φ because the data line capacitance is thicker than that obtained when Mck is selected. As a result, the amount of drop from the precharge level on the high potential side of the data line after the signal is amplified by 8A becomes large, and the rewrite voltage becomes small.

Therefore, as shown in FIG. 11, Do. , ■ By setting the precharge level t"Dor, Dot higher than that of Dot, even if the high potential side of the data line falls, it is possible to obtain the same rewriting xgt- for both. In this embodiment, the 12th As shown in FIG. 13, unlike the operation shown in FIG. 7, the signal φald controlling the switch 8W is at a low V pel during the precharge operation, and the switch 5WFiD0°,
, D, , -.

Note that in FIG. 11, the transistors Qs, s'Q8!
are each Do. Tori, DO, and D can be omitted as they are used to make them equipotential.

Figure 14 is the opposite of Figure 11. I # I) An example of precharging os with a high potential is shown. The circuit configuration is the 10th
The dummy cell DM is shown in the figure. , DM.

and short circuit 5CkDo. , ■; The configuration is such that it is added to the side. FIG. 15 shows the memory cell MCI.
Figure 6 shows the operating waveform when MCkt'' is selected.The operation will be explained below using this waveform.First, the precharge signal φpt is set to a high level (V+α), and φa' is set to an intermediate level V.
o, by precharge circuit PC and short circuit 8C. ,,Do, to VpelV, Doo, Doo'
t (Vo Vt ). Here vT
is the threshold voltage of the transistor of switch SW. Then, after falling φP, if we now read out the high level of the memory cell MCI (Fig. 15), the word line W+ is selected by the X decoder, the word pulse φwt is applied, and the dummy word pulse φDWo is applied to the dummy word. Line DW,. is applied to Do. , Do. niDo. .

A differential signal determined by the capacitance of the Doo portion and the memory cell capacitance is generated. This differential signal passes through all the switches SW. ,
, D, , - and then amplified by 8A. Then, R8T restores Do to the rewrite voltage V, boosts it to φotV+α, and
Raise o to V and rewrite. - When reading the high level of 10,000 MCk (Fig. 16), after φP falls, φG also falls, and Doo is taken.
The signals of MCk are read and rewritten separately. In this example, Doo or Ri. .

Even when reading memory cells connected to
It has the advantage that it can be made as large as the memory cell for the differential signal kDoI or Dol amplified by A. It's not true.

Unlike the embodiments described above, FIG. 17 shows a switch S.
An example is shown in which W is controlled by two signals φO1+φG. In the configuration shown in FIG. 6, the switch SW is connected to two control lines GC.

Controlled by GC2, a differential amplifier, I/(11, switch YGt-) is also placed on the Doo and Do0 sides.Also, the number of memory cells connected to o and Do is equal, and the dummy cell capacitance is is equal to the memory cell capacity, and a so-called full-size dummy cell method is used.

FIG. 18 shows operational waveforms when reading a high level from memory cell MC. As shown in the figure, when reading the signal, the gate of the switch connected to the data line on the dummy cell side (GC) is kept at a high level (in Figure 18, φG
M), the data line capacitance on the dummy cell side is 2 on the memory cell side.
By doubling it, the reference signal voltage is obtained. Thereafter, before amplification by 8A, φG is also lowered to a low level, and after the unbalance of the data line capacitance is corrected, the signal is amplified.

The reading ratio of M Ch is also performed in the same manner. This embodiment has the advantage of being able to use full-size dummy cells in this way. Although FIG. 18 shows the case where only MCI is operated, it is also possible to operate MCk at the same time.

Up to now, we have shown embodiments using two-intersection cells;
The present invention is also applicable to a memory configured with a bitline arrangement (referred to as a bitline arrangement or one intersection cell). An example thereof is shown in FIG. 19th
FIG. 5 corresponds to FIG. 5, which is an example of a two-intersection cell. In the same figure, since the data pair lines are spread out to the left and right around 8At-center, the switch 8 that divides the data lines
W (SWL, 5WR) 4 extends to the left and right, and a control signal line (GCL, 0CR) is required for each switch. According to the invention, 1
Even in the intersection cell, power consumption can be reduced, as described in the case of the two-intersection cell.

Furthermore, the present invention subdivides the data line, and each line has an I10
& memory array configuration (for example, special fa5
6-81042, patent application 57-125687゜% 58
-4162), and an example thereof is shown in FIG. As shown in the figure, Y
With output control signal YC from decoder and X driver? A switch YG controlled by J is provided, and data is exchanged with l101#A. Each divided data line is further divided by a switch SW controlled by an output control signal #GC from an X decoder and an
The switch SW is opened and closed depending on whether it is connected to the terminal (o + Dnot), thereby reducing power consumption. Also, in this embodiment, the relationship between word line selection and switch opening/closing shown in FIG. 3 or 4 is expanded and applied to this embodiment to reduce power consumption and The amount of reduction can be made equal no matter which memory cell is selected. In FIG. 20, A indicates an address signal t-1RWC and a read/write control circuit.

Although some embodiments of the present invention have been described above, the scope of application of the present invention is not limited to the embodiments described here, and it goes without saying that various changes can be made without departing from the spirit of the invention. For example, Although a case has been described here in which the transistor is configured with an n-channel MO8) transistor, it is also possible to configure it with a P-channel MOS transistor by reversing the potential relationships of all the signals used. Also 0MO8
The present invention is also applicable to a memory configured by (Complementary M OS). Furthermore, although the explanation has been made using a 1-transistor MO8 memory as an example, so-called static memory (for example, 1880083 T
mechanical Digest P, 66) and ROM (for example, 18SCC83Techn
icalDigest P, 168) or a microprocessor in which these memories are mounted on the same chip, the power consumption can be reduced by the present invention. As an example, FIG. 21 shows an embodiment of the present invention for a static memory. As shown in Figure PI3, a data pair line to which a large number of memory cells each composed of 7 lip-flops are connected is divided by a switch SW which is turned on by a signal lfMGC, and a memory cell MCk is connected to a word If! When selected by AWk, SW is turned off, and when memory cell MC+ is selected, it is turned on to 5Wt, thereby reducing power consumption in the same way as the one-transistor MO8 memory.

〔Effect of the invention〕

As described above, according to the present invention, a memory with low power consumption can be realized despite high integration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional semiconductor memory device, and FIGS. 2 to 21 are diagrams explaining the present invention in detail, respectively. MC...memory cell, DM...dummy cell, d,?
r. D, D...Data line, W...Word line, DW...
Dummy word line, XD...X decoder, X driver,
YD...X decoder, Y driver, Ilo, l10-
...Input/output line (IlofIM), YC...Y driver output line, SA...differential amplifier circuit, PC...data line precharge circuit, RAT...data line high potential compensation circuit, SC ...Short circuit, YG...l10f3
! Connection switch, 1st country 2nd] 5th % 61st! l No. 81! l 9th day 1o figure /l prisoner 14th day l horoscope 76th in 17th day time l? Day λshi Kσ No. 21 Continuation of Phantom 1 Page 0 Inventor: Kiyoo Ito 1, Higashikoigakubo, Kokubunji City, Naishitame 28 Hata, Hitachi, Ltd.

Claims (1)

[Claims] 1. A plurality of data line groups and a word line group, a memory cell group arranged at the intersection of the data line and the word line, an input/output line common to the data line group, and a connection between the input/output line and the data line group. In a semiconductor memory device having a first switch circuit that performs connection, at least one second switch circuit that divides the data line into a plurality of data line subgroups is provided, and the selected memory cell and the input/output are connected to each other. A semiconductor memory device characterized in that a group of data line portions not involved in the connection is separated from a group of data line portions involved in connection with the line by opening and closing of the second switch circuit.