JPS60201460A - I/O device access method - Google Patents

Abstract

PURPOSE:To access to a low speed input/output device without lowering a speed of operation of central processing unit by accessing once to the input/output device that operates at low speed while the central processing unit executes access instruction of two bytes over two clock periods. CONSTITUTION:During the course in which a microprocessor MPU executes access instruction of two bytes, address a1 sent out in the first clock period t1 and effective data d1 sent out in the second clock period are transmitted to a circuit controlling section IO, and written by an input/output device selection signal cs transmitted to the circuit controlling section IO in the second clock period t2 and an input/output write/read signal cvw. Accordingly, the circuit controlling section IO operates at low speed of 1/2 of clock signals phi1 and phi2 that operate the operation speed of the microprocessor MPU to the same as the circuit controlling section IO in level.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to information processing systems, and in particular to an input/output device access method that allows a central processing unit that operates at high speed to access input/output devices that operate at low speed. .

(b) Background of the technology In information processing systems, input/output devices such as line control units that control information transmission over communication lines operate at a much lower speed than central processing units and main storage devices that operate using high-speed clock signals. It works.

(C1 Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional input/output device access method using a 1-byte access command. In FIG. 1, a microprocessor MPU operated by clock signals φ1 and φ2 is , when writing data to the line control unit 0, which is a type of low-speed input/output device, write the address a of the required register in the line control unit IO set in the program counter pc via the address bus AB. The line control unit 10 receives the address a and writes the data d transmitted from the accumulator built in the microprocessor MPU via the data bus DB into the register. The above operating speeds are all determined by the cycles of clock signals φ1 and φ2.

As is clear from the above explanation, in the conventional input/output device access method, in order for the microprocessor MPU to access the input/output device that operates at low speed, the speed of the clock signals φ1 and φ2 must be adjusted to the speed of the input/output device. This was not possible unless the operating speed was reduced. However, reducing the speed of the clock signal has been unfeasible because it would reduce the overall processing speed of the information processing system and, in turn, reduce the processing capacity.

+d+ OBJECTS OF THE INVENTION The object of the present invention is to provide means for eliminating the drawbacks of the conventional input/output device access methods as described above, and making it possible to access input/output devices that operate at low speeds without reducing the operating speed of the central processing unit. It is about realizing.

(Ql Structure of the Invention) This object is to provide an information processing system that includes a central processing unit that operates at high speed and an input/output device that operates at low speed, in which the central processing unit executes a 2-byte access command to the input/output device. Means for holding an address that the device sends out in a first clock cycle and invalidating an address that it sends out in a second clock cycle; and an enable signal that invalidates the enable signal that the device sends out in the first clock cycle and sends out in the second clock cycle. This is accomplished by providing means for validating a signal to enable access from the central processing unit to the input/output device.

That is, in the present invention, by accessing the input/output device operating at low speed once while the central processing unit executes a 2-byte access instruction over 2 clock cycles,
It becomes possible to access low-speed input/output devices without reducing the operating speed of the central processing unit.

ffl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an input/output device access method according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating various signal waveforms in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, there is a line control unit I between the microprocessor MPU and the line control unit
Microphone that executes the 2-hide access command to access O 4. The processor MPU holds the address a1 sent out in the first clock cycle, and invalidates the address a2 (-al+1) sent out in the second clock cycle. A decoder DCR1 control circuit CA and a launch circuit LB are provided as means, and the microprocessor MPU
A launch circuit LA and a control circuit CB are provided as means for invalidating the enable signal sent out in the first clock period and validating the enable signal sent out in the second clock period. 2 and 3, the register to be accessed by the line control unit 10 (address a
1), the microprocessor MPU writes the address a1 to the program counter PC and any invalid data dO to the upper 1 byte of the index register IX, which can store 2 bytes of data.
, data d1 is stored in the lower 1 byte, and execution of a 2-byte access instruction is started. first clock period t
At l, the microprocessor MPU sends the address a1 from the program counter PC onto the address bus AB. The address a1 is transmitted to the decoder DCR and the latch circuit LB via the address bus AB. The decoder DCR converts the received address a1 into an input/output device selection signal S, and sends it to the control circuit CA and the launch circuit LA.
to communicate. The control circuit CA that has received the input/output device selection signal S causes the latch circuit LB to hold the address a1 transmitted from the address bus AB, and also causes the decoder D to hold the address a1 transmitted from the address bus AB.
The state of CR is held for a second clock period t2. The latch circuit LB holds the address al transmitted via the address bus AB, and transmits it to the line control unit 10 as an input/output device address ca. On the other hand, the launch circuit LA is
The input/output device selection signal cs is not output until the second clock cycle t2 starts. Furthermore, the microprocessor MPU
In the latter half of the first clock cycle t1, the input data dO is sent to the data bus DB from the upper 1 byte of the index register TX. The invalid data dO is transmitted to the line control unit LCU via the data bus DB, but since the line control unit LCU does not receive the input/output device selection signal C8 during the first clock period t1, the data bus Do not receive invalid data dO transmitted from DB. Before the start of the second clock period t2, the microprocessor MP
U is address a2 (-a
1+1) is stored in the program counter PC.

At the second clock period t2, the microprocessor M
PU sends address a2 from program counter PC to address bus AB. The address a2 is sent to the decoder DCR and the launch circuit L via the address bus AB.
However, since the decoder DCR maintains the output state of the input/output device selection signal S during the second clock period t2 under the control from the control circuit CA, the address a2
No conversion operation is performed. The latch circuit LB is also maintained in a state where it holds the address a1 transmitted from the address bus AB in the first clock period t1, and does not hold the address a2 transmitted via the address bus AB in the second clock period t2. . Therefore, launch circuit LB
continues to transmit the address a1 to the line control unit 10 as the input/output device address Ca during the second clock period t2. On the other hand, when the second clock cycle t2 starts, the launch circuit LA outputs the input/output device selection signal cs and transmits it to the line control unit IO and the control circuit CB. The control circuit CB is
While the input/output device selection signal cs is transmitted from the launch circuit LA, the write continuation signal rw set to the write state transmitted from the microprocessor MPU is sent to the line control unit To as the input/output device write continuation signal crw. introduce. In the second half of the second clock period t1, the microprocessor MP
U sends valid data d1 from the lower 1 byte of index register IX to data bus DB. The valid data d
1 is transmitted to the line control unit 10 via the data bus DB. This time, since the line control unit 0 has received the input/output device selection signal cs and the input/output device write continuation signal CrW set to the write state, the valid data d1 transmitted from the data bus DB is Write to the input/output device address ca (=al) transmitted from the latch circuit LB.

As is clear from the above description, according to this embodiment, in the process of executing a 2-byte access instruction by the microprocessor MPU, the address a1 sent out in the first clock period t1 and the address a1 sent out in the second clock period t2. The valid data d1 is transmitted to the line control unit (2)0, and is written in by the input/output device selection signal cs and the input/output device write continuation signal crw that are transmitted to the line control unit (20) in the second clock period t2. Therefore, the line control unit 10 uses clock signals φ1 and φ to operate the microprocessor MPU.
Since the microprocessor MPU operates at a low speed of 1/2 of 2, there is no need to reduce the operating speed of the microprocessor MPU to the same level as that of the line control unit IO.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the present invention is applied to a microprocessor MP.
The present invention is not limited to writing to the line control unit 10 from U, and the effects of the present invention do not change even if it is applied to reading from the line control unit IO. Also microprocessor MPU
The input/output device accessed by the user is not limited to the line control unit ro, and many other modifications may be considered, but the effects of the present invention remain the same in any case.

(a) Effects of the Invention According to the present invention, in the information processing system, input/output devices that operate at low speed can be accessed without reducing the operating speed of the central processing unit, and the processing capacity of the information processing system can be increased. Deterioration is prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an input/output device access method using a conventional 1-byte access command, FIG. 2 is a diagram showing an input/output device access method according to an embodiment of the present invention, and FIG.
The figure is a diagram illustrating various signal waveforms in FIG. 2. In the figure, a, al and a2 are addresses, AB is an address bus, CA and CB are control circuits, ca is an input/output device address, crw is an input/output device write/read signal, and C3
is an input/output device selection signal, DB is a data bus, DCR is a decoder, 10 is a line control unit, IX is an index register, LA and LB are launch circuits, MPU is a microprocessor, PC is a program counter, rw is a write/read signal , S represents an input/output device selection signal, tl represents a first clock period, t2 represents a second clock period, and φ1 and φ2 represent clock signals. 1 arithmetic 1 a year Z b

Claims (1)

[Claims] In an information processing system comprising a central processing unit that operates at high speed and an input/output device that operates at low speed, the central processing unit that executes a 2-byte access command to the input/output device sends it in a first clock cycle. Means for holding the address and invalidating the address transmitted in the second clock cycle, and means for invalidating the enable signal transmitted in the first clock cycle and validating the enable signal transmitted in the second clock cycle are provided. . An input/output device access method, characterized in that the input/output device can be accessed from the central processing unit.