JPS60196792A - display control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a display control device, and particularly to an output device such as a converter system. The present invention relates to a display control device having a function of dividing a display screen into a plurality of blocks in a CRT display device used as a CRT display device and performing a smooth flow independently in each block.

(Technical Background and Prior Art) In graphic display devices and the like, so-called scrolling is performed in which displayed characters and the like are sequentially moved upward or the like on the screen. Conventionally, in this scrolling, character strings and the like move line by line, making it difficult to check the displayed content during the scrolling operation. In addition, since the character string moves line by line, the display screen of the display device flickers, causing inconveniences such as increased eye fatigue for the user.

(Object of the invention) The object of the present invention is to solve the problems of the conventional type described above.
Based on the concept of allowing the count start value of the raster address counter to be preset externally in a display control device, it is possible to perform a smooth scroll function with a simple circuit configuration, and the screen is divided into multiple blocks. The object of the present invention is to enable independent smooth scrolling, facilitate circuit integration, reduce circuit space, and improve reliability.

(Structure of the Invention) According to the present invention, the present invention provides a memory address counter that sequentially generates memory addresses for sequentially reading out character codes stored in a memory, and a character generator that stores character pattern data. and a raster address counter that generates a raster address for reading character pattern data specified by a code, and the raster address counter returns to the initial state when the count value reaches the raster number of one character, and This is achieved by providing a display control device characterized in that it is configured such that a starting value can be preset from the outside.

(Example of the invention) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows the configuration of a display control device according to an embodiment of the present invention, that is, a display system capable of performing screen division independent smooth scrolling using a CRT controller. The display system shown in the figure includes, in addition to a CRT controller 1, display memory 2, character generator 3, and parallel/serial converter 4, a character counter 5, memory address counters 6, 7, 8, a smooth scroll raster counter 9, and a switchable raster counter. It includes logic 1o, zi, and a processor (CPU) 12.

FIG. 2 shows an example of character number and turn data stored in the character generator 3.

In this example, the character pattern U3X71' is a non-turn, and the address of the corresponding character pattern is specified by the character code, and seven pattern data D1, D2, . ..., ■) 7 is 1
1n order output.

In the display system shown in FIG. 1, a CRT controller 1 generates a memory address, a rask address, a vertical synchronization signal (IVSYNC), a horizontal synchronization signal H8YNC, etc. in response to a character clock.

A memory address generated by the CRT controller 1, that is, memory address 1, is input to the display memory 2 via the switching logic 10, and the corresponding character code is read out and input to the character generator 3 which stores pattern data of each character. . Further, the raster address 9 is inputted from the CRT controller 1 to the character generator 3 via the switching logic 11. Character code 1/A2rr+ > 4-1 LfA 2
,- Tanriki 7-? K◆ Shi-z? 7N; Outputs 5-bit pattern data at each time point based on the star address and outputs this iJ? The turn data is converted into a signal VDO via a parallel-to-serial converter 4, and is converted to a signal VDO (not shown).
Supplied to RT display equipment. = A vertical synchronizing signal VSYNC and a horizontal synchronizing signal H8YNC are supplied from the CRT controller 1 to the CRT display device, and characters, images, etc. are displayed based on these synchronizing signals and the artist signal.

In the display system as described above, when performing smooth scrolling of the display screen, the rask address input to the character generator 3 is input to the CRT controller 1.
The input is not from the smooth scroll raster counter 9 via the switching logic 11. The smooth scroll raster counter 9 counts the horizontal synchronizing signal H8YNC to generate a rask address, and is configured so that the initial value of the count can be changed externally. Therefore, the smooth scroll raster counter 91't C
Counting can be performed with a phase different from that of a normal raster counter built into the RT controller 1. By sequentially changing the initial value of the smooth scroll raster counter 9, scrolling in units of rasters, that is, smooth scrolling can be performed. Note that the initial value of the smooth scroll raster counter 9 can also be changed using, for example, a zologram.

Furthermore, when performing split-screen independent smooth scrolling in the display system shown in FIG. When a certain count value is reached, the memory address is input from the corresponding memory address counter to the display memory 2 via the switching logic 10, and the image data at the address after the memory address is input to the character generator 3. Note that each memory address counter 6.7.8 is sequentially incremented in synchronization with the υ character clock under the control of the character count 5.
The initial value of 8 can be changed to specify the start address of the display memory 2 for storing data of each split screen block. In this way, in the display system of FIG. 1, the display screen can be divided into four at most, and smooth scrolling can be performed independently for each divided block.

The smooth scroll raster counter 9 used in the above-described display system is a counter whose initial count value can be preset from an external circuit such as the processor 12, for example. FIG. 3 shows an example of such a smooth scroll raster counter. In the figure, numeral 13 is a 3-bit output counter, which generates outputs of values from 6"o' to 7". Reference numeral 14 is a register for storing the preset address 9 input manually from a processor, etc., and 15 is a decoder which clears the counter 13 when the count value of the counter 13 reaches puff #. The counter 13 counts the horizontal synchronization signal H3YNC, etc., counts up every raster scan, and when it counts eight rasters, the output value returns to "0". 16 is an OR gate, and a vertical synchronizing signal VSYNC'! ! : It outputs a preset control signal instructing to preset the data in the register 14 to the counter in synchronization with the instruction from the Take processor.

FIG. 4 is a conceptual diagram for explaining the smooth scrolling operation, and shows how character strings are displayed on the screen. The left side of the figure shows a display screen when the raster address of the CRT controller is directly given to the character generator. The right side of the figure shows a display screen when the raster address from the smooth scroll raster counter is given to the character generator. In this case, the register 14 (FIG. 3) is preset with the binary number "100", that is, the decimal number '4', and the data stored in this register 14 is synchronized with the vertical synchronization signal VSYNC. starts counting from 4" and is cleared by the clear signal CLR at 7".

Therefore, the Nohira turn data from the character generator is read out from the fourth rask data and displayed as shown in the right part of FIG. In order to perform smooth scrolling, for example, the value set in the register 14 may be incremented by 2 for each vertical blanking period. As a result, the displayed characters are not scrolled digit by digit as in the conventional case, but are scrolled two rasters at a time, resulting in a so-called smooth scrolling operation.

FIGS. 5(a), 5(b), and 5(e) respectively show the stored contents of the display memory and the display mode on the display screen when performing the screen splitting operation. That is, in the case of normal display without screen division display, character codes such as areas A and B of the display memory in FIG.

It is assumed that each area A and B stores character codes for one screen. On the other hand, when performing split-screen display, for example, the non-contiguous areas C, D, E, F' are read out in a predetermined sequence, for example, as shown in FIG. 5(b) or (c). It is divided and displayed for each area.

In the case of the fifth diagram b), the display screen has four vertical zones.
In the case of FIG. 3(c), the display screen is divided into two in the vertical direction and in the horizontal direction to form four display zones. In addition, MAI.

MA2, MA3, and MA4 represent the start addresses of each area C, D, E, and F of the display memory, respectively, and the character corresponding to the character code of each of these start addresses is displayed at the upper left position of each zone. .

FIG. 6 shows the configuration of a CRT controller in a display control device according to another embodiment of the invention.

The circuit in the figure includes a horizontal counter 17 that counts character clocks, a horizontal ↓υ] signal generation circuit 18, a memory address counter 19, and memory address registers 20 and 21.
．． 22, 23, a vertical synchronizing signal generating circuit 24, a vertical counter or row counter 25, a raster counter 26, a smooth scroll raster counter 27, and a raster control circuit 28.

The operation of the CRT controller shown in FIG. 6 will be explained.

The horizontal counter 17 counts the character clock and inputs a pulse to the horizontal synchronizing signal generating circuit 18 every horizontal scanning period. Based on this pulse, the horizontal synchronization signal generation circuit 18 generates a horizontal synchronization signal H3YNC with a predetermined pulse width and amplitude.
is generated and supplied to a CR'l' display device (not shown) or the like. The output pulses of the horizontal counter 17 are sent to the raster counter 26 and the smooth scroll raster counter 27.
These counters 26 and 27 are respectively counted up or down every horizontal scanning period. The raster counter 26 outputs the rask address when scrolling is not performed, that is, the rask number in one line, and this rask address is supplied to the character generator via the last control circuit 28. When the raster counter 26 has counted a predetermined number of pulses, that is, the number of rasters in one row, that is, when the counting of the number of rasters in one row has been completed, it inputs a pulse signal to the vertical counter 25. The vertical counter 25 counts this pulse signal, and inputs the pulse signal to the vertical synchronization signal generation circuit 24 when it finishes counting the number of lines for one screen. The vertical synchronizing signal generating circuit 24 generates a vertical synchronizing signal VSYNC having a predetermined pulse width and amplitude based on the Norms signal from the vertical counter 25, and supplies it to the CRT display device.

Next, when performing a smooth scroll operation, the raster control circuit 28 is switched and the output of the smooth scroll raster counter 27 is input to the character generator as a rask address. Like the raster counter 26, the smooth scroll raster counter 27 counts the pulses output from the horizontal counter 17 in each horizontal scanning period and counts the number of rasters in one line, but the phase of counting is For example, they can be changed sequentially from the outside by a program. In order to change the counting phase of the smooth scroll raster counter 27, for example, the initial value of the counter 27 may be changed by inputting a preset address signal in response to a preset control signal, or the counted value may be forcibly changed during counting. It may also be increased or decreased independently of the pulses from the horizontal counter 17. In this way, by sequentially forcibly increasing or decreasing the count value of the smooth scroll raster counter 27, the rask address supplied to the character generator can be sequentially adjusted relative to the normal rask address output from the raster counter 26. It is possible to shift the
Therefore, it becomes possible to perform scrolling in rask units, that is, smooth scrolling.

On the other hand, screen split display is performed as follows. The vertical counter 25 counts the number of lines, and this number of lines is stored in each memory address register 20゜21, 22, 23.
When a predetermined value is reached, a dart signal is input to the corresponding memory address register, and a memory address value is set in the memory address counter 19 from the memory address register. This memory address value is an address that stores the image information at the top position in one block of the divided screen, and the image information in the block is sequentially read from this address. That is, memory addresses are sequentially input from the memory address counter 19 to the display memory, and character codes read from the display memory are input to the character generator.

In the configuration shown in Figure 2, there are 4 memory address registers.
Since there are 2 memory address registers, it is possible to divide the display screen into four parts at most.
．． By setting the contents of 23 separately, characters, images, etc. can be displayed independently in each block of the divided screen. In this case, it is clear that each block can be smoothly scrolled by the function of the smooth scroll raster counter 27.

FIG. 7 shows the configuration of an image display system using the display control device of FIG. 6. The system shown in the figure can have an extremely simple configuration since it only includes a display memory 2, a character generator 3, and a parallel-to-serial converter 4 in addition to the display control device 29 shown in FIG. Become.

(Effects of the Invention) As described above, according to the present invention, it is possible to perform smooth scrolling, split display, and screen split independent smooth scrolling by combining these with a simple circuit configuration. This makes it possible to reduce circuit space and improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a display control device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of character pattern data stored in a character generator, and FIG. 3 is a smooth scroll raster diagram. counter 1
A block circuit diagram showing an example; FIG. 4 is an explanatory diagram showing a smooth scroll operation; FIG.
FIGS. 5(b) and 5(C) are plan views each showing an aspect of screen split display on a display screen, and FIG. 6 is a CRT controller used in a display control device according to another embodiment of the present invention. FIG. 7 is a block circuit diagram showing a display control device using the CRT controller of FIG. 6. 1, 29: CRT, controller, 2: display memory, 3: character generator, 4: parallel-serial converter, 5: character counter, 6, 7, 8: memory address counter, 9.27: smooth scroll raster counter, 10.11: Switching logic, 12: CPU, 1
3: Counter, 14: Register, 15: Decoder, 1
6: OR boot, 17: Horizontal counter, 18 Two horizontal synchronization signal generation circuits, 19: Memory address counter, 20.
21, 22° 23: Memory address register, 24: Vertical synchronization signal generation circuit, 25: Vertical counter, 26: Raster counter, 28 Niraster control circuit. Patent applicant Fujitsu Ltd. Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akiyuki Yamaguchi Figure 1 - Kiku MA4 Figure 6

Claims (1)

[Scope of Claims] 1. A memo IJ that sequentially generates memory addresses for sequentially reading out character codes stored in the memory. 7 dress counters and character generators that store character pattern data specified by the character codes. The raster address counter is equipped with a raster address counter that generates a raster address for reading character pattern data, and the raster address counter returns to the initial state when the count value reaches the raster number of one character, and the count start value can be preset externally. 2. The count start value is updated every time the character code for one screen is read out. The display control device according to claim 1, characterized in that: 3. When the count value of the memory address counter reaches a predetermined value, the count value is forcibly changed to another value; The display control device (+') according to claim 1, characterized in that the count is continued from the value that has been set.