JPS60194613A - Pulse delay circuit - Google Patents

Abstract

PURPOSE:To obtain a necessary pulse delay time even when the electrostatic capacity value of a capacitor is small, and reduce the electrostatic capacity value of the capacitor and obtain small chip area during IC-implementation by regarding the base current of a transistor (TR) obtained by reducing the current from a constant current source to 1/h (h: current amplification factor of TR) as the charging current to the capacitor. CONSTITUTION:The charging current to the capacitor 2 is the base current of the TR6 obtained by reducing the current supplied from the constant current source to the TR6 to 1/h (h: current amplification factor of TR6). Then, the output voltage of the 2nd TR6 varies as the capacitor 2 is charged. Thus, the electrostatic capacity value C of the capacitor 2 of the pulse delay circuit need not be increased and sufficient pulse delay is therefore attaind with the small- sized capacitor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse delay circuit that supplies current from a constant current source to a capacitor as a charging current and delays a pulse based on a change in the charging voltage at the capacitor.

FIG. 1 is an electrical circuit diagram showing a conventional pulse delay circuit. In FIG. 1, 1 is a transistor to which the pulse P1 to be delayed is applied, and 2 is the transistor 1.
3 is a constant current source, 4 is a comparator, and 5 is a reference power source. In the pulse delay circuit having such a configuration, a pulse P1 is applied to the base of the first transistor 1. This pulse P1 makes the first transistor 1 conductive, and the charging voltage of the capacitor 2 is discharged through the collector-emitter of the first transistor 1. Next, pulse P1 falls,
When the first transistor 1 is cut off, the current from the constant current source 3 charges the capacitor 2; This constant current source 3
The charging voltage P2 at capacitor 2 increases due to the current from
When the charging voltage P2 exceeds the voltage value ■ of the reference power supply 5,
The output pulse P3 of the humpator 4 falls. In this case, the capacitance of the capacitor 2 is C1, the voltage value of the reference power source 5 is V, and the charging current to the capacitor 2 by the constant current source 3 is I.
, and the pulse delay time is T, the following equation holds true.

T = CX V / 1 Therefore, in order to lengthen the pulse delay time T, it is preferable to increase the capacitance value C and the voltage value ■ of the reference power source 5, or to decrease the charging current I. In this case, assuming that the voltage value ■ and the charging current I are constant, it is necessary to increase the capacitance value C in the conventional example. However, increasing the capacitance value C necessarily increases the size of the capacitor 2, so if such a pulse delay circuit is to be integrated into an IC (integrated circuit), it will require a very large chip area. , it is difficult to adopt this method when trying to downsize a circuit device.

The present invention has been made in view of the above circumstances, and includes:
To provide a pulse delay circuit that can obtain the required pulse delay time even if the capacitance value of the capacitor is small, and that can be made into a small chip area when integrated into an IC by reducing the capacitance value of the capacitor. The purpose is to

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 2 is an electrical circuit diagram of an embodiment of the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals. In FIG. 2, 1 is the first pulse to which the delayed pulse P1 is applied.
Transistor 2 is the collector of the first transistor 1.
A capacitor is connected in parallel between the emitters, 3 is a constant current source, 4 is a comparator, and 5 is a reference power source.

6 is the collector of the first transistor 1 and the capacitor 2
A second transistor whose base is connected to the connection point 7 with. By providing the second transistor 6 in this way, the charging current to the capacitor 2 is 1/1 the current from the constant current source supplied to the second transistor 6.
The base current of the second transistor 6 is multiplied by 1 (where 11 is the current amplification factor of the second transistor). As the capacitor 2 is charged, the output voltage of the second transistor 6 changes. Comparator 4 is the second
The output voltage value of the transistor 6 and the voltage value (2) of the reference power source 5 are compared, and when the output voltage value exceeds the voltage value (2) of the reference power source 5, the comparison output pulse is caused to fall as a delayed pulse.

In this way, in the pulse delay circuit of the embodiment, the charging current to the capacitor 2 is 1/11 times the emitter current of the second transistor 6, which is the base current. Therefore, even a small capacitor 2 can sufficiently delay the pulse without significantly reducing the capacitance value C of capacitor 2. In this embodiment, the conductivity type of the first transistor 11 is n.
Although the second transistor 6 has a pnp conductivity type, it goes without saying that the same implementation can be performed even if the conductivity type is reversed.

FIG. 3 shows the first pulse delay circuit constituting the pulse delay circuit shown in FIG.
．． 2nd) Run transistors 1 and 6 and capacitor 2 are connected to IC
and is a diagram showing the pattern layout of the IC.
FIG. 4 is a structural cross-sectional view taken along line A--A in FIG. 3. In these figures, the region surrounded by the mark indicates a buried diffusion region, the region surrounded by the H mark indicates a P-type diffusion region, and the region surrounded by the symbol ■ indicates an N-type diffusion region.

////C means diagonal line. ) indicates the contact area. The conductivity type of the first transistor 1 shown here is NPN, and that of the second transistor is sub-PNP. 10 is a P-type silicon substrate, 11 is an N+ type buried diffusion region, and 12 is N type epitaxial layer region, 13 and 1.3 are P-type isolation diffusion regions, 14.15 is N1-type diffusion region, and 16.17 is P-type isolation diffusion region.
Type diffusion region, 18°1.9, 20.21 are contacts,
22 is a silicon oxide film.

The symbols 12, 14, and 16 are the first transistor 1, respectively.
collector, emitter, and base regions of 10.17.
Reference numeral 12 indicates the collector, emitter, and base regions of the second transnoster 6, respectively, and 15 indicates the region of the capacitor 2. 18 and 19 are the emitter contact and base contact of the first transistor 1, respectively, 21 is the emitter contact of the second transistor 6, and 20 is the contact of the capacitor 2.

As described above, according to the present invention, there is provided a first transistor to which a pulse to be delayed is applied, a capacitor connected in parallel between the collector and emitter of the first transistor, and a collector of the first transistor and the capacitor. and a second transistor whose base is connected to the connection point with the second transistor, and the current from the constant current source supplied to the second transistor is multiplied by 1/h (where h is the current amplification factor of the second transistor). The base current of the second transistor is used as the charging current for the capacitor, and the pulse is delayed based on the change in the output voltage of the second transistor as the capacitor is charged. The current required is very small, which allows the required pulse delay time to be obtained even with small capacitance values of the capacitor. Further, in the present invention, the first. Each element of the second transistor and the capacitor is formed by an IC, and the IC is arranged so that each element is arranged and formed on the same epitaxial land.
Since the pattern C is laid out, a long pulse delay time can be obtained even if the capacitance value of the capacitor is small, as described above, and therefore, when converting it into an IC, it is possible to create a circuit device with a small chip area. Miniaturization can be achieved.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram of a conventional example, FIG. 2 is an electrical circuit diagram of an embodiment of the present invention, and FIG. 3 shows the components of the circuit in FIG.
FIG. 4 is a diagram showing the pattern layout of the IC when converted into a C, and is a structural cross-sectional view taken along the line A--A in FIG. 3. 1 is a first transistor, 2 is a capacitor, 3 is a constant current source, 4 is a comparator, 5 is a reference power supply, and 6 is a second capacitor. Applicant: - Mu Co., Ltd. Agent Patent Attorney Oka 1) Kazuhide Figure 2

Claims (2)

[Claims] (1) A first transistor to which a pulse to be delayed is applied, a capacitor connected in parallel between the collector and emitter of the first transistor, and a base connected to the connection point between the collector of the first F transistor and the capacitor. the current from the constant current source supplied to the second transistor is multiplied by 1/h (however, b
is the current amplification factor of the second transistor), and the base current of the second transistor is used as the charging current for the capacitor, and the pulse is delayed based on a change in the output voltage of the second transistor as the capacitor is charged. A pulse delay circuit characterized by: (2) A first transistor to which the delayed Beto pulse is applied, a capacitor connected in parallel between the collector and emitter of the first transistor, and its base connected to the connection point between the collector of @1 transistor and the capacitor. the current from the constant current source supplied to the second transistor is multiplied by 1/h (however, h
is the current amplification factor of the second transistor), and the base current of the second transistor is used as the charging current for the capacitor, and the pulse is delayed based on a change in the output voltage of the second transistor as the capacitor is charged. 1. A pulse delay circuit characterized in that each element of a second transistor and a capacitor is formed by an IC, and a pattern of the IC is laid out so that each element is arranged and formed on the same epitaxial land.