JPS60193379A - Formation for low-resistance single crystal region - Google Patents

Abstract

PURPOSE:To enable to obtain a clean forming method in such a way that the gate length on a mask and the actual gate length coincide with each other by a method wherein an anisotropic etching and a selective-and-epitaxial growth are combined together. CONSTITUTION:An oxide film 2 is formed on the surface of a P type Si substrat 1, and after that, a polycrystalline Si film 3, which is used as a gate, is deposited thereon. After an Si nitriding film 4 was deposited on the polycrystalline Si film 3, the film 4 and the film 3 are performed a patterning. The Si nitriding film 4 is further deposited, the Si nitriding film only deposited on the film 2 is removed, and moreover, the film 2 is removed excluding the film 2 just under the Si film 3. As a result, the film 3 is covered with an Si nitriding film 4'. Regions, from where the silicon film 3 is exposing, are etched using an anisotropic etching solution and grooves 5 are formed. An Si film is made to selectively and epitaxially grow in the regions only of the grooves 5 while an impurity is doped and low resistant single crystal regions 6 are formed. As a result, a trouble of contamination, which easily occurs in the process, doesnot generate and the difference between the gate length on a mask and the actual gate length can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for obtaining a fine low resistance region t- at a desired location on a silicon substrate.

[Prior art and its problems]

MOB(Metal-Ozide-8gtnicond
(sctor)) Diffusion or ion implantation is used to form the source and drain regions of transistors. As devices become smaller, a method of using polycrystalline silicon as a gate and performing ion implantation in a self-aligned manner is mainly adopted.

However, this method has the disadvantage that the actual gate length is shorter than the gate length on the mask by about twice the implantation depth of ion implantation, and there is a risk of contamination and defect generation during ion implantation. It had the disadvantage of being

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a low-resistance single-crystal region in which the gate length on the mask matches the actual gate length by eliminating such conventional drawbacks.

[Structure of the invention]

The present invention combines anisotropic etching and selective epitaxial growth to form fine MDS transistors, thereby obtaining source and drain regions without the drawbacks of conventional methods. A region covered with δ and a region where silicon is exposed are provided, and the silicon in the exposed region is etched using an anisotropic etching solution to form a groove, and while doping impurities, the groove is etched. This is a low resistance single crystal region forming method characterized by growing a silicon film only in the region.

[Detailed explanation of the configuration]

Hereinafter, the present invention will be explained in detail using Examples.

〔Example〕

FIGS. 1(G) to 1(d) are diagrams sequentially showing the steps of an embodiment of the present invention. In the figure (α), after oxidizing the surface of a p-type silicon substrate 10 in the (100) orientation to form a thin silicon oxide film 2, a polycrystalline silicon film 3 that will become a gate is deposited on it while doping with impurities. , after depositing a thinner silicon nitride film 4, the silicon nitride film 4 and polycrystalline silicon film 3 are patterned. The polycrystalline silicon film 3 may be doped by ion implantation after deposition. In the figure (6), after the step (α), a thin silicon nitride film 4 is further deposited, and only the silicon nitride film on the oxide film 2 is removed by reactive ion etching.
Furthermore, the state in which the silicon oxide film 2 has been removed with hydrofluoric acid is shown. Polycrystalline silicon film 3 is covered with silicon nitride film 4'. The silicon oxide film 4 removed last is extremely effective in preventing contamination due to ion etching, and fc e (C) uses hydrazine to etch the exposed silicon region in step (b). This is a state in which grooves 5 have been formed. The etching solution is not limited to hydrazine, but since the (111) plane is likely to appear, the side surface of the groove 5 and the substrate surface form an angle of 54.7 degrees. (The chrysanthemum indicates the state after performing selective epitaxial growth while performing doping.The raw material gases include 5illsC1*, HCI
, PI(s) was used to grow the low resistance single crystal region 6 to almost the same level as the initial substrate surface.

(After the step F, the surface of the low resistance single crystal region 60 is oxidized to form a thin silicon oxide film, and then a silicon oxide film is deposited by chemical vapor deposition to form a passivation film. Complete by drilling holes in the source and drain regions and making contact with the wiring.

〔Effect of the invention〕

To show an example of the results of the present invention, when the etching depth of the substrate silicon and the growth thickness are ~0.2 μm, the growth temperature is 9.
Growth is carried out under reduced pressure at 50°C, and the raw material gas is 1cPfI, /5i.
HiClp+ -0,015, HCl/SiruCノ, ~
4, the sheet resistance is 2000/L] and j
c, the difference between the channel length on the mask and the actual channel length was ~0.03 μm on one side, significantly reduced from the value ~0.2 μm using ion implantation.

As described in detail above, according to the present invention, for example, there is no problem of contamination that is likely to occur during the dry process, and a clean process can be performed. This method has the effect of providing a method for forming a low resistance single crystal region that is smaller than that of the previous method.

[Brief explanation of drawings]

FIGS. 1(cL) to 1(d) are cross-sectional views showing the steps of the example of "non-explosion ψ" in order of process. (...1m silicon substrate, 2... thin silicon oxide film, 3... polycrystalline silicon film, 4... silicon nitride film, 5... fc groove formed by etching, 6... n
Low resistance of mold Figure 1 (α)

Claims (1)

[Claims] (A region covered with an amorphous insulating film and a region where silicon is exposed are provided on the surface of a silicon substrate, and the silicon in the exposed silicon region is etched using an anisotropic etching solution to form a groove. 1. A method for forming a low-resistance single-crystal region, the method comprising growing a silicon film only in the region of the trough while doping with impurities.