JPS60193053A - Command checking system - Google Patents

Abstract

PURPOSE:To improve the detection factor of a command error between processors by providing a decoder for commands on a command bus and a comparator which compares the output of the decoder with the data on a direction indicating line to each processor. CONSTITUTION:A processor A is provided with a decoder DEC1, a circuit NOR, a driver DRV1, a control part CON1, a circuit EOR1, an inverter INV1 and a circuit AND1. While a processor B has the same constitution as the processor A excluding the circuits OR. The circuit EOR1 performs an exclusive OR operation between the output of the circuit NOR and the data on a direction indicating line DB. A circuit EOR2 performs an exclusive OR operation between the output of a circuit OR and the data on the line DB. Then signals are outputted from both circuits AND1 and AND2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a command checking method, and more particularly to a method for checking commands communicated between processors operating in the same phase.

[Prior art]

Conventional command checking of this type consists only in adding a parity bit to data on a bus that connects processors, and performing a parity check in the receiving processor.

Such a conventional system has the disadvantage that if a command itself is sent with a mistake, the mistake cannot be extracted, and it is also impossible to check for malfunctions of the decoder that reads the command in the processor on the receiving side.

[Purpose of the invention]

The purpose of the present invention is to achieve the following by adding a small amount of hardware.
Top 1. It is an object of the present invention to provide a command check method capable of eliminating drawbacks and improving the error detection rate of commands communicated between processors.

[Structure of the Invention] - The system of the present invention determines in advance the direction of communication for each command communicated between processors operating with the same phase clock, and transmits at least the command between the processors. a decoder for decoding the commands on the command bus, and a decoder for decoding the commands on the command bus; Front F of output
It is specially mandated that a comparator circuit be provided to compare the output that meets the specifications with the data on the direction indicating line.

〔Example〕

Next, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, in this embodiment 9!1, two processors A and B, which operate with the same phase clock, and processor A
Command bus CB and direction instruction 11 connecting
It consists of 1DB.

The command bus CB consists of 4-bit signal lines, and the opinion of each bit is as shown in FIG.

That is, bit 0, which is the most significant bit (MSD), determines whether the lower bits 1 to 3 (LSL) indicate data in a narrow sense (when bit 0 is logic "1"). And bit 0 to bit 3 are OH-2H
, the command is sent from processor A to processor B.
In addition, when 5H to 7H are indicated, it is assumed that the command is directed from processor B to processor A.
A command when bit 0 to bit 3 indicate 3H to 4H is unused.

Directions! 1)! DB is a 1-bit signal line, which corresponds to the communication direction of each of the above commands and has 92 candy information. In other words, the data (in a broad sense) on the command bus CB or OH
'%J21 (corresponding to 5H to 7H, the bits on the direction indication gDB become logic 11# and @IO#.

Processor A includes a decoder DECI, a negation and sum circuit NOR, drivers DB and Vl, and a control unit C0N1.
Exclusive OR circuit EO1, inverter INVI,
It is composed of an AND circuit ANDl. Processor B has the same configuration as processor A except for the OR circuit OR, and includes a decoder DEC2, a logical sum circuit OR, a driver DRV2, a control unit CON2, and an exclusive OR circuit E.
OR2, inverter INV2, and AND circuit AND2
Tokarararu.

Control 4I (C0N1 and CON2) are the core of processor B, respectively, and control the entire processor. Drivers DRVI and DRV2 each have a control unit C0.
It receives data from NI and CON2 and sends it to the command bus CB and direction indication line DB.

Each of decoders DkJC1 and DEC2 decodes data on command bus CB. Decoders DEel and DE
Starting from the right end, each of the six outputs of C2 becomes logic "1" when the data on the command bus CB is OH*IH12H45Ht6H and 7H. Therefore, the NOR circuit NOR circuit in processor A and the decoder DEC
When 1 does not decode and output the command from processor B to the processor, it outputs 1 - 1', and the OR circuit 0 in processor B decodes and outputs the command from processor A to processor B. When it does not, p・ri "0" will be output.

The exclusive OR circuit EORI performs an exclusive OR operation between the output of the NOR circuit NOR and the data of the direction indication line OH-HI, and the exclusive OR circuit EOR2 performs an exclusive OR operation with the output of the OR circuit OH. Direction IH indication line 1) Exclusive OR operation with data on B is performed.

As a result of this, even though the data on the direction instruction #IDB instructs the command to be sent from processor +B to processor A (logical ``0#''), the decoder DECI
is not decoding and outputting such commands (5H to 7) 1) (#i1 ``1''), or when the decoder D
Even though EC1 is decoding and outputting any of the commands (5H to 7H) directed from processor B to processor A (logic "0"), the direction instruction i1! Data on DB 1.1 Does not indicate such direction (Logic "1"
), exclusive OR circuit goh1 has logic "1"'
You can understand that it outputs .

Similarly, is the data on the direction indicator OB Procera? When the decoder DEC2 does not decode and output such a command (OH-2H) (logical 10") even though A is instructing to send a command to B (logical ``1''). , or even though the decoder DEC2 is decoding and outputting any of the commands (θ□ to 2H) directed from processor A to processor B (!l!ri"1#), the direction instruction @DB is When the data does not indicate such a direction (theory B"O"), the exclusive OR circuit BOR
It can be easily understood that 2 is a logic that outputs ``1#''.

Each of the inverters INV1 and INV2 inverts bit 0 on the command bus CB, so that when the data on the command bus CB represents a command, the logic "'1#" is inverted by the AND circuit ANI)l will be output to AND2.

The AND circuit AND1 performs arithmetic operations on the output of the exclusive #B logical sum circuit OR1 and the output of the inverter INVI, and the logical product circuit AND2 performs arithmetic operations on the output of the exclusive #B logical sum circuit OR1 and the output of the inverter INVI.
An AND operation is performed between the output of the inverter INV2 and the output of the inverter INV2.

After all, when the data on the command bus CB represents a command, if a problem occurs between the output of the decoder DECI or DBC2 and the data on the direction indicator I%IDE as described above, the logic stock circuit AND1 or AND2
H1 outputs error signals ERI and ER2 to the outside.

FIG. 3 is a time chart showing the operation of this embodiment more specifically. Referring to FIG. 3, in the first command cycle (clock cycle in which bit 0 becomes logic "0#"), the data (D
B: Output of decoder DEC2 that matches IK (DEC2)
Therefore, the output (EOB, 2) of the exclusive OR circuit hofL2 is in the acid phase "0#", and therefore the error signal E2 is not output.

However, in the second command cycle, the contents of bit 1 to bit 3''1 indicate the command to be assigned to the command group specified by the data (DB) on the direction indication line DB. However, the DEC2 malfunctions and outputs the logic 00#, so the output (EOB2) of the exclusive OR circuit EOR2 is full of logic 1#, and the AND circuit AND2 outputs the error signal ER2. is outputting.

In clock cycles other than the first command cycle and the second ind cycle, bit O is logic "1", so bits 1 to 3''& represent data in a narrow sense. As described above, inverters INVI and INV2 output the brass door 10'' to the OR circuits AND1 and AND2, respectively, and the outputs of the exclusive OR circuits EOB1 and EOB2 are ignored.

In the embodiment described above, the command path CB conveys commands and data in a narrow sense in a time-sharing manner.
A separate transport path exclusively for data in a narrow sense may be provided, and the command bus CB may be used exclusively for the cloak.

In addition, in the actual example explained above, parity check has not been mentioned so far, but with the command check method of the present invention, it is impossible to detect alternations between commands belonging to the command group in the same direction. Therefore,
It is noted in Appendix 8 that the combined use of the command check method and parity check method of the present invention is effective in improving the detection rate of command errors.

〔Effect of the invention〕

According to the present invention, by employing the above-described configuration, the problem could be detected by the parity check.

Since it becomes possible to check for sending errors in the command itself and malfunctions in the decoder, it becomes possible to improve the rate of error extraction of commands communicated between processors.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIGS. 2 and 3 show diagrams for transferring the embodiment between stations. CB...Command bus, DB...Direction line, A, B-1-17" a*yt, D
BCI, DEC2, 7' coder, NOR...
...Negative OR circuit, OR...OR circuit, EORI, EOR2...Exclusive OR circuit,
INVl, INV2,... Inverter, AND
I, AND2......AND circuit, DB, Vl, D
RV2... Driver, C0NI, CON2...
...control section. Figure 3

Claims (1)

[Scope of Claims] The direction of the communication is determined in advance for each command communicated between processors operating with the same phase clock, and a command bus for transmitting at least the command and a command bus are provided between the processors. a decoder for decoding the commands on the command bus, and a decoder for decoding the commands on the command bus for each processor; A command check system characterized in that a comparison circuit is provided for comparing an output that is combined with data on a direction indicating line.