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JPS6018936A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS6018936A
JPS6018936A JP12670483A JP12670483A JPS6018936A JP S6018936 A JPS6018936 A JP S6018936A JP 12670483 A JP12670483 A JP 12670483A JP 12670483 A JP12670483 A JP 12670483A JP S6018936 A JPS6018936 A JP S6018936A
Authority
JP
Japan
Prior art keywords
circuit
wiring
power supply
terminal
voltage drop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12670483A
Other languages
Japanese (ja)
Inventor
Yukio Minato
湊 幸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12670483A priority Critical patent/JPS6018936A/en
Publication of JPS6018936A publication Critical patent/JPS6018936A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To operate an integrated circuit normally even when wiring width is reduced by dividing a circuit terminal into a plurality of groups by the voltage- drop tolerance values of wirings to reference voltage and separately mounting the power supply wirings at every group. CONSTITUTION:A circuit terminal 2 having the small voltage-drop tolerance values of wirings on an integrated circuit to voltage as a reference and a large circuit terminal 3 are divided, and power supply wirings 4' and 4'' are each connected to a power supply pad 7. Currents i1 and i2 each flow into the terminal 2 and the terminal 3, and currents i1+i2+i3 flow out at a wiring terminal 5'. Accordingly, voltage drop can be reduced by using the wirings 4' and 4'', and wiring width can be minimized remarkably.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、配線方法を改良したところの集積回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an integrated circuit with an improved wiring method.

〔従来技術〕[Prior art]

最近の集積回路は、高集積化が進めらjている一方で、
性能の高速化が進められている。特に、バイポーラ品種
で、その傾向が顕著である。その高速化の手段として、
デバイス性能の向上に加えて、回路電流の増加がある。
While recent integrated circuits are becoming more highly integrated,
Performance is being accelerated. This tendency is especially noticeable in bipolar varieties. As a means of speeding up the process,
In addition to improved device performance, there is an increase in circuit current.

ところが、通常の回路は、電圧降下に対して、敏感な電
圧降下許容範囲値の小さい回路端子と、鈍感で電圧降下
許容範囲値の大きい回路端子を持ち、七わらは同一配線
上に、混在した状態で接続されていた。そのため、内部
回路電流全天きくすれば、内部配線の電圧降下も一段と
犬きくなシ、特に、電圧降下に敏感な回路が、正常動作
しなくなる場合があった。
However, a normal circuit has circuit terminals that are sensitive to voltage drops and have a small voltage drop tolerance value, and circuit terminals that are insensitive and have a large voltage drop tolerance value. It was connected in the state. Therefore, if the internal circuit current were to increase completely, the voltage drop in the internal wiring would also increase, and in particular, circuits that were sensitive to voltage drops could no longer operate normally.

第1図は従来の集積回路の一例の要部を示す平面図であ
る。
FIG. 1 is a plan view showing a main part of an example of a conventional integrated circuit.

回路1の電圧降下許容範囲値の小さい回路端子2と、大
きい回路端子3を同一の配線4で、電源パッド7から接
続しである。
A circuit terminal 2 having a small voltage drop tolerance value and a circuit terminal 3 having a large voltage drop tolerance value of the circuit 1 are connected from a power supply pad 7 by the same wiring 4.

いま、回路1の回路端子2及び回路端子3にそhぞi′
1電流t、l F が流入し、又、配線端5には、電流
(i、+i2+ia )が流ねている場合について必要
な配線4の幅を計算してみる。但し、回路端子3は回路
端子2と同一直線上にあるものとする。配線4の幅をW
l、回路端子2と配線端5間の長さを−e1配綿の層抵
抗をρ、とする。さらに、回路上許容さf]る電圧降下
許容範囲値を回路端子2に対してはl(1、回路端子3
に対してばに2(0≦に、 <K 2 )を満足させる
に必要な最小配線幅をめてみる。この場合は当然のこと
ながら、電圧降下許容範囲値の小さい場合について考え
hばよい。従って、配線4の最小配線幅Waは、Wa=
7ed−(i、+i2+j、)=Wi 、、、(1)と
なる。
Now, connect circuit terminal 2 and circuit terminal 3 of circuit 1.
Let us calculate the necessary width of the wiring 4 in the case where one current t, l F flows in and a current (i, +i2+ia) flows through the wiring end 5. However, it is assumed that the circuit terminal 3 and the circuit terminal 2 are on the same straight line. Width of wiring 4 is W
l, the length between the circuit terminal 2 and the wiring end 5 is -e1, and the layer resistance of the cotton distribution is ρ. Furthermore, for circuit terminal 2, l(1, circuit terminal 3
In contrast, let us look at the minimum wiring width necessary to satisfy 2 (0≦, <K 2 ). In this case, naturally, it is sufficient to consider the case where the voltage drop tolerance range value is small. Therefore, the minimum wiring width Wa of the wiring 4 is Wa=
7ed-(i,+i2+j,)=Wi, (1).

すなわち、最小配線幅Waは、電圧降下許容範囲値の小
さい回路端子の東件に制約されてし寸い、必要以上に幅
の大きい配線を用いなけhばならない。もしも配線幅が
(12式のWaよりも小さい場合には、前述のように回
路端子20回路が正常動作をしなくなることになる。
That is, the minimum wiring width Wa is limited by the requirements of circuit terminals with small voltage drop tolerance values, and it is necessary to use wiring that is wider than necessary. If the wiring width is smaller than (Wa of type 12), the circuit terminal 20 circuit will not operate normally as described above.

こわを防ぐために、従来は配線に使用している金属導体
の膜質、膜厚を改善するか、配線幅を大きくして、電圧
降下を少さくしなけ力ばならなかった。但し、前者の場
合、現在のプロセス技術では限界があり、大幅な改善は
難しく、又、後者の場合も配線幅を大きくすることは、
集積度向上の上から大きな妨げとなるという問題点があ
った。
In order to prevent stiffness, conventionally it was necessary to improve the film quality and thickness of the metal conductor used in the wiring, or to increase the wiring width to reduce the voltage drop. However, in the former case, there are limits to current process technology and it is difficult to make significant improvements, and in the latter case, increasing the wiring width is difficult.
There was a problem in that it was a major hindrance to improving the degree of integration.

一方、複数の同様な回路を並列配置させて、電源が接続
される所定の回路端子(例えば、第1図の回路端子2)
の電位と、回路に入ノJされる信号の電位を等しくシ、
その大きさに一定の傾斜を持たせてやると言った場合が
あるが、このような楊今に第1図に示すような従来技術
では、回路端子2と回路端子3は分離されていないので
、そhらの電位関係を任意に設定することができない。
On the other hand, by arranging a plurality of similar circuits in parallel, a predetermined circuit terminal to which a power supply is connected (for example, circuit terminal 2 in FIG. 1)
If the potential of the signal input to the circuit is equal to the potential of the signal,
There are cases where it is said that the size has a certain slope, but in the conventional technology shown in Figure 1, the circuit terminal 2 and the circuit terminal 3 are not separated. , h cannot be arbitrarily set.

このため、回路端子の電位と入力信号の電位がアンバラ
ンスとなり、回路が誤動作するといった問題点もあった
Therefore, there is a problem that the potential of the circuit terminal and the potential of the input signal become unbalanced, causing the circuit to malfunction.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、かかる従来技術の問題点を解決すると
とにより、従来よりも配線幅が小さくても、電圧降下許
容範囲値の小さい回路端子を有する回路を含めて正常動
作させることができ、かつ必要に応じ所定の回路端子群
の電位関係全規制できるところの電源配線を有し、集積
度と回路動作の安定性の向上した集積回路を提供するこ
とKある。
An object of the present invention is to solve the problems of the prior art, thereby enabling normal operation of circuits including circuit terminals with small voltage drop tolerance values even if the wiring width is smaller than before. Further, it is an object of the present invention to provide an integrated circuit having a power supply wiring that can fully regulate the potential relationship of a predetermined group of circuit terminals as necessary, and which has an improved degree of integration and stability of circuit operation.

〔発明の構成〕[Structure of the invention]

本発明の集積回路は、基準電圧に対する配線の電圧降下
許容範囲値によシ回路端子を複数のグループに分け、該
グループ毎に電源配線を個別に設けたことから構成さ力
る。
The integrated circuit of the present invention is constructed by dividing the circuit terminals into a plurality of groups according to the permissible voltage drop range value of the wiring with respect to a reference voltage, and separately providing power supply wiring for each group.

〔実施例の船、明〕[Example ship, Ming]

以下、本発明の実施例について図面を参照して詳細に説
明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第2図は本発明の第1の実施例の要部を示す平面図であ
る。本実施例は第1図に示した従来例の集積回路に本発
明を適用したもので、同じものには同一符号を付しであ
る。
FIG. 2 is a plan view showing essential parts of the first embodiment of the present invention. In this embodiment, the present invention is applied to the conventional integrated circuit shown in FIG. 1, and the same components are given the same reference numerals.

本実施例は、基準となる電圧に対して回路上配線の電圧
降下許容範囲値の小さい回路端子2と、大きい回路端子
3を分けて、それぞわ個別に、電源配線4′及び4′を
電源バッド7に接続することで構成さねている。
In this embodiment, the circuit terminal 2 and the circuit terminal 3, which have a small voltage drop tolerance value of wiring on the circuit with respect to the reference voltage, are separated, and the power supply wirings 4' and 4' are connected individually. It is configured by connecting to the power supply pad 7.

次に、第1図の従来例の場合と回じ柴件、すなわち、回
路端子2及び回路端子3にはそわぞ−i′1電流iI 
及び12が流入し、配線端5′にて電流(i、+i2 
+i3 )が流出しており、回路端子2及び回路端子3
と配線端5′間の長さf:詔、配線4′及び4#の層抵
抗をρ8 、回路端子2及び3の電圧降下許容範囲値を
そわぞれに1及びK 2とし、この場合に必要とされる
最小配線幅wbl求めてみる。
Next, there is a difference between the case of the conventional example shown in FIG.
and 12 flow in, and the current (i, +i2
+i3) has leaked out, and circuit terminal 2 and circuit terminal 3
Length f between wire end 5' and wire end 5': The layer resistance of wires 4' and 4# is ρ8, and the voltage drop tolerance values of circuit terminals 2 and 3 are respectively 1 and K2, and in this case, Let's find the required minimum wiring width wbl.

回路端子2の′11i圧降下をKl内に入りるための最
小配線幅全W 2 、回1t!8端子3の電圧降下をK
z内に入ノするための最小配線幅W 4 、及び、W2
とW4間の分離幅kW3とすると、関係式%式%(3) が得ら刺る。従って、(1)式と(2)式よシ(3)式
とK 2 ’:;> K t≧0よりさらに、分離幅W
3は、W 3〈W2.Waと設定されるので、 Wb=(W2+W3+W4 )<Wl=Wa・・−・・
・・・・・・・(6) となる。
Minimum wiring width total W 2 to bring the '11i pressure drop of circuit terminal 2 into Kl, times 1t! 8 The voltage drop at terminal 3 is K
Minimum wiring width W 4 and W2 for entering inside z
Assuming that the separation width between and W4 is kW3, the relational expression % (3) is obtained. Therefore, from equations (1) and (2) to equation (3) and K 2 ':;> K t≧0, the separation width W
3 is W 3<W2. Since Wa is set, Wb=(W2+W3+W4)<Wl=Wa...
・・・・・・・・・(6)

従って、本実施例の配線4′及び4#を用いねば、電圧
降下を小さくでき、かつ配線幅は第1図の従来の配線4
に比べ、格段に小さくできる。
Therefore, by using the wires 4' and 4# of this embodiment, the voltage drop can be reduced, and the wire width is smaller than that of the conventional wire 4 in FIG.
It can be made much smaller than.

次に、数値例を挙げてよシ具体的に、第11シlの従来
例と第2図の本発明の第1の実施例について比較を行う
ことにする。
Next, by giving a numerical example, we will specifically compare the conventional example of the 11th sill with the first embodiment of the present invention shown in FIG.

前述の式に訃いて、回路端子2に流れる電流i。Based on the above equation, the current i flowing through the circuit terminal 2.

==5mA、回路端子3に流れる電流12 =50mA
1配線端6′から流出する電流i3 =195mAで、
回路端子2の電圧降下許容範囲に1=(+)5さA=4
00μm1配線の層抵抗ρ、=0゜02Ω/dとして、
その場合におけるそれぞわの最小線幅Wa及びwbをめ
る。但し分離幅W3=5μmとする。
==5mA, current flowing through circuit terminal 3 12 =50mA
Current i3 flowing out from 1 wiring end 6' = 195mA,
The voltage drop tolerance of circuit terminal 2 is 1 = (+)5 A = 4
Assuming layer resistance ρ of 00μm1 wiring, = 0゜02Ω/d,
Find the minimum line widths Wa and wb in each case. However, the separation width W3 is set to 5 μm.

(1)式よシ =400μm (2ン式よシ (3)式より (6)式より Wb=8 + 5 + 19.6=32.6 ttm従
って、水弟1の実施例の最小配線幅は従来例のものの約
8%強、すなわち、1/10以−Fと非常に小さくて良
いことが分る。
From formula (1), Wb = 400 μm (from formula (2), from formula (3) to formula (6), Wb = 8 + 5 + 19.6 = 32.6 ttm. Therefore, the minimum wiring width of the embodiment of Mizuhiro 1 It can be seen that it can be very small, about 8% or more of that of the conventional example, that is, 1/10 or more -F.

第3図<a)r、!本発明の第2の実施例の要部を示す
平面図、第3図(1)ンはその特性図である。
Figure 3<a)r,! A plan view showing the main parts of the second embodiment of the present invention, and FIG. 3(1) is a characteristic diagram thereof.

本実施例は、同様なN個の回路11.12・・・・・・
In this embodiment, N similar circuits 11, 12...
.

INからなる回路群を含み、そわらは、それぞi1基準
点からの電圧降下許容範囲値の小さい回路端子21,2
2.・・・・・・、2Nと大きい回路端子31゜32、
−・・・・・ 3 N ff:持っている回路に、本発
明を適用したものであシ、配線42は回路端子21゜2
2、・・・・・・、2Nに対する配線43と、回路端子
31.32.・・・・−・、3Nに対する配線44とに
分離されて、電源パッド41に接続されている。なお、
配線端45.46からは任意の電流が流釣出していても
かまわない。
The circuit terminals 21 and 2 each have a small voltage drop tolerance range value from the i1 reference point.
2. ......, 2N and large circuit terminals 31°32,
-... 3 Nff: The present invention is applied to the existing circuit, and the wiring 42 is connected to the circuit terminal 21゜2.
Wiring 43 for 2, . . . , 2N and circuit terminals 31, 32 . . . , 3N, and are connected to the power supply pad 41. In addition,
It does not matter if any current flows out from the wiring ends 45 and 46.

本実施例の場合も、第2図の第1の実施例の場合と同様
で、配線を分離しない従来の配線(図面省略)に比べ、
所要配線幅は、格段に小さくてよい。
The case of this embodiment is similar to the case of the first embodiment shown in FIG.
The required wiring width may be much smaller.

更に、従来の配線と本実施例の配線43の回路端子21
,22.・・・・・・、2Nの位置の、電圧降下は第3
図(bJ中の直線す及びb′に示すようになり、従来の
配線は同図中の直線a及びa′に示すように、電圧降下
は大きく、かつ、不均一な電圧降下となるのに対し、本
実施例の配線42の電圧降下は極めて小さく、かつ、均
一ガミ圧降下となっている。
Furthermore, the circuit terminal 21 of the conventional wiring and the wiring 43 of this embodiment
, 22. ......, the voltage drop at the 2N position is the third
As shown in the straight lines a and b' in the figure (bJ), the voltage drop in conventional wiring is large and uneven, as shown in the straight lines a and a' in the same figure. On the other hand, the voltage drop of the wiring 42 in this embodiment is extremely small and has a uniform voltage drop.

すなわち、本実施例によると、従来の配線よシ幅を小さ
くでき、かつ、はぼ均一の電位を所定の回路端子に与え
ることができる。
That is, according to this embodiment, the width of the conventional wiring can be reduced, and a substantially uniform potential can be applied to predetermined circuit terminals.

第4図(a)は、本発明のfg 3の実施例の要部を示
す平面図、第4図(11)、 (C)はその特性図であ
る。
FIG. 4(a) is a plan view showing a main part of an embodiment of FG3 of the present invention, and FIGS. 4(11) and 4(C) are characteristic diagrams thereof.

本実施例は、同様なN個の回路51,52.・・・・・
・、5Nからなる回路群を含み、そわらは、そわぞワ、
水準点からのtli圧降下許容範囲値の小さい回路端子
61,62.・・・・・・、6Nと、大きな回路端子7
1.72.・・・・・・、7Nを持ち、回路端子81゜
82、・・・・・・、8Nからそわぞれに信号VSI、
VS 2.・・・・・・、VSNが入力されている回路
に、本発明を適用したものであり、配線92は、回路端
子61.62.・・・・・・、6Nに対する配線93と
、回路端子71.7.2.・・・・・・、7Nに対す不
配線94とに分離されて、電源パッド91に接続さねて
いる。なお配線93は、配線92の回路端子6N部分よ
り分離さ力、配線92に重なる部分95を第1層配イウ
とし、開口部96.97そ第2層配線で形成さ力る配線
93に接続されている。
In this embodiment, N similar circuits 51, 52 .・・・・・・
・Contains a circuit group consisting of 5N, Sowara is Sowazowa,
Circuit terminals 61, 62 .with small tolerable tli pressure drop values from the benchmark.・・・・・・6N and large circuit terminal 7
1.72. ......, 7N, and the signals VSI,
VS 2. . . . The present invention is applied to a circuit to which VSN is input, and the wiring 92 is connected to the circuit terminals 61, 62, . . . ., wiring 93 for 6N and circuit terminals 71.7.2. . Note that the wiring 93 is separated from the circuit terminal 6N portion of the wiring 92, the portion 95 overlapping the wiring 92 is the first layer wiring, and the opening 96.97 is connected to the wiring 93 formed by the second layer wiring. has been done.

更に、本実施例の回路では、そh(jiの回路に入力さ
れる信号VSI、VS2.・旧・・VSNは、第4図(
a)に示すように、回路51への信号VSIを基準とし
て一定の傾斜にしたがい順次大きくなっており、回路5
1,52.・・・・・・、5Nは、それぞね回路端子6
1,62.−・・・・・、6Nの電位と、入力信号Vs
 1.Vs 2. ・、−、Vs N(D電位が、全回
路毎にそhぞわ同じ値の場合、最も正常な回路動作が可
能であるとする。
Furthermore, in the circuit of this embodiment, the signals VSI, VS2, old, and VSN input to the circuit of soh(ji) are as shown in FIG.
As shown in a), the signal VSI to the circuit 51 is gradually increased in accordance with a constant slope, and the signal VSI to the circuit 51 is gradually increased.
1,52. ......, 5N are circuit terminals 6, respectively.
1,62. -..., 6N potential and input signal Vs
1. Vs 2. -, Vs N (If the D potential is the same value for all circuits, the most normal circuit operation is possible.

ここで、第1図の従来例に示す如く、配線を分離しない
場合と、本実施例の場合とで、配線の両端95.96に
電流が流れている場合、回路端子61.62.・・・・
・・、6Nの電位は第4図(C)に示すようになる。す
なわち、本実施例の場合は、配線93は配線95を介し
て一本化され、回路端子6Nを通り電流が電源パッド9
1から流わるようになっており、その配線の単位長当り
の電圧降下を、第4図(b)に示す所定の電位勾配とな
るように配線幅を設定しであるので、第4図(C)中の
直線すに示すようになる。これに対して、配線全分離し
ない従来の配線の場合は、第4図(CJ中の直線a及び
a′に示すように、電源パッド91を中心として、そわ
から離れるに従い電圧降下は犬となる。
Here, as shown in the conventional example of FIG. 1, in the case where the wiring is not separated and in the case of this embodiment, when current flows through both ends 95, 96 of the wiring, the circuit terminals 61, 62, .・・・・・・
..., 6N potential is as shown in FIG. 4(C). That is, in the case of this embodiment, the wiring 93 is unified via the wiring 95, and the current passes through the circuit terminal 6N and reaches the power supply pad 9.
1, and the wiring width is set so that the voltage drop per unit length of the wiring becomes the predetermined potential gradient shown in Figure 4(b). C) The straight line in the middle will be as shown in the figure. On the other hand, in the case of conventional wiring that does not completely separate the wiring, as shown in Figure 4 (straight lines a and a' in CJ), the voltage drop decreases as the distance from the power supply pad 91 increases from the center. .

かくして、回路端子61.62.・・・・・・、6Nの
電位と、入力信号Vs l、Vs 2.−・・・、Vs
Nの電位の差は、従来の配線による回路では、アンバラ
ンスとなシ、誤動作を生ずる恐わがあるのに対し、本実
施例によると、極めてバランス良く形成されるので、安
定した正常動作を確保することができる。すなわち、本
実施例によると、端子電位が所定の関係金安求されると
き、そhに合せることができ、回路動作全安定化するの
に役立つ。
Thus, circuit terminals 61, 62. . . . 6N potential and input signals Vs l, Vs 2. −..., Vs
In a circuit using conventional wiring, the potential difference between N is unbalanced and may cause malfunction, but in this embodiment, it is formed in an extremely well-balanced manner, ensuring stable and normal operation. can do. That is, according to this embodiment, when the terminal potential is required to be at a predetermined level, it can be adjusted to a certain value, which is useful for completely stabilizing the circuit operation.

なお、以上の説明は、配線の電圧降下許容範囲値が、小
さい端子と、大きい端子の2種類の場合に限定したけ力
ども、更に電圧降下許容範囲値が幾つにも分ねる場合は
、その許容範囲値に合せて、A群、B群、c2;y、・
・・・・、N群のように拡俳できることは言う丑でもな
い。
Note that the above explanation is limited to the case where the voltage drop tolerance range value of the wiring is two types, small terminal and large terminal, but if the voltage drop tolerance value is further divided into several types, Group A, group B, c2; y, ・according to the allowable range value.
...It's no wonder that they can expand like the N group.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説り」したとおバ本発明によりは、基準電圧
に対する配線の電圧降下許容値により回路端子を複数の
グループに分け、このグループ毎に電源配線を個別に設
けているので、従来の電源配線よりも配線幅を非常に小
さくしても、電圧降下許容値の小さい回路端子を有する
回路を含めて正常動作させることができ、かつ必要に応
じ所定の回路端子群の′電位関係を規制できるところの
電源配線を有する集積回路が得られる。従って本発明の
集積回路は、集積度と回路動作の安定性を向上するとい
う効果を有している。
As explained in detail above, according to the present invention, circuit terminals are divided into a plurality of groups according to the permissible voltage drop value of the wiring with respect to the reference voltage, and power supply wiring is provided separately for each group, so that the conventional power supply Even if the wiring width is much smaller than the wiring, it is possible to operate normally, including circuits that have circuit terminals with a small voltage drop tolerance, and it is possible to regulate the potential relationships of a given group of circuit terminals as necessary. However, an integrated circuit having power supply wiring can be obtained. Therefore, the integrated circuit of the present invention has the effect of improving the degree of integration and stability of circuit operation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の集積回路の一例の要部を示す平面図、第
2図は本発明の第1の実施例の要部を示図、第4図(a
)は本発明の第3の実施例の要部を示す平面図、第4図
(b)及び(C)は木筆3の実施例の特性図である。 1・・・・・・回路、2.3・・・・・・回路端子% 
4,4’14′・−・・−電源配線、5.5’、6.6
’・・・・・・配線端、7・・・・・・電源パッド、1
1,12.IN・・・・・・回路、21,22.2N、
31,32.3N・・・・・・回路端子、41・・・・
・・電源パッド、42,43.44・・−・・・電源配
線、45.46・・・・・・配線端、51,52゜5N
・−・・・・回路、61,62.6N、71,72゜7
N、81,82.8N・・・・・・回路端子、91・・
・・−・電源パッド、92,93,94.95・・・−
・・電源配線、’ 96.97・・・・・・開口部、9
8.99・・・・・・配線端。 代理人 弁理士 内 原 晋、。 第 l 図 第 2 図 身請 3 βq(ρ) 第3図(b)
FIG. 1 is a plan view showing a main part of an example of a conventional integrated circuit, FIG. 2 is a plan view showing a main part of a first embodiment of the present invention, and FIG.
4(b) and (C) are characteristic diagrams of the wood brush 3 according to the embodiment. 1...Circuit, 2.3...Circuit terminal%
4,4'14' --- Power supply wiring, 5.5', 6.6
'... Wiring end, 7... Power pad, 1
1,12. IN...Circuit, 21, 22.2N,
31, 32.3N...Circuit terminal, 41...
・・Power supply pad, 42, 43.44 ・・・・Power supply wiring, 45.46 ・・・・Wiring end, 51, 52° 5N
・・・・・・Circuit, 61, 62.6N, 71, 72°7
N, 81, 82.8N...Circuit terminal, 91...
...-Power pad, 92, 93, 94.95...-
・・Power wiring, ' 96.97 ・・・Opening, 9
8.99...Wiring end. Agent: Susumu Uchihara, patent attorney. Figure l Figure 2 Figure 3 βq(ρ) Figure 3 (b)

Claims (3)

【特許請求の範囲】[Claims] (1)基準電圧に対する配線の電圧降下許容範囲値によ
り回路端子を複数のグループに分け、該グループ毎に電
源配線を個別に設けたことを特徴とする集積回路。
(1) An integrated circuit characterized in that circuit terminals are divided into a plurality of groups according to the permissible voltage drop range value of wiring with respect to a reference voltage, and power supply wiring is individually provided for each group.
(2)電圧降下許容値の小さいグループの回路端子への
電源配線が電圧降下許容値の大きいグループの回路端子
への電源配線の一部分から分離されてなる電源配線を含
む特許請求の範囲第(1]項記載の集積回路。
(2) Claim No. 1 that includes power supply wiring in which the power supply wiring to the circuit terminals of the group with a small voltage drop tolerance is separated from a part of the power supply wiring to the circuit terminals of the group with a large voltage drop tolerance. ] The integrated circuit described in the section.
(3)少くとも一つの′rル圧降下許容値の小さいグル
ープの回路端子への電源配線が、電圧降下許容値の大き
いグループの回路端子への電源配線の基準電圧となる点
よシ遠い部分から分離され、かつ前記電圧降下許容値の
大きい電源配線の一部分を多層配線によシ跨設さhるこ
とからなる特許請求の範囲第(2)項記載の集積回路。
(3) At least one part where the power supply wiring to the circuit terminal of the group with the small voltage drop tolerance is far from the point that serves as the reference voltage of the power supply wiring to the circuit terminal of the group with the large voltage drop tolerance. 2. The integrated circuit according to claim 2, wherein a portion of the power supply wiring, which is separated from the power supply wiring and has a large voltage drop tolerance, is straddled by a multilayer wiring.
JP12670483A 1983-07-12 1983-07-12 Integrated circuit Pending JPS6018936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12670483A JPS6018936A (en) 1983-07-12 1983-07-12 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12670483A JPS6018936A (en) 1983-07-12 1983-07-12 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS6018936A true JPS6018936A (en) 1985-01-31

Family

ID=14941785

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12670483A Pending JPS6018936A (en) 1983-07-12 1983-07-12 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS6018936A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420680A (en) * 1977-07-18 1979-02-16 Hitachi Ltd Large scale integrated circuit
JPS5627953A (en) * 1979-08-15 1981-03-18 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5420680A (en) * 1977-07-18 1979-02-16 Hitachi Ltd Large scale integrated circuit
JPS5627953A (en) * 1979-08-15 1981-03-18 Nec Corp Semiconductor device

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