JPS60189318A - Pulse amplifying device - Google Patents
Pulse amplifying deviceInfo
- Publication number
- JPS60189318A JPS60189318A JP4611084A JP4611084A JPS60189318A JP S60189318 A JPS60189318 A JP S60189318A JP 4611084 A JP4611084 A JP 4611084A JP 4611084 A JP4611084 A JP 4611084A JP S60189318 A JPS60189318 A JP S60189318A
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- input
- relay
- amplifying element
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明はパルス増幅装置に関するものである。[Detailed description of the invention] [Technical field of invention] The present invention relates to a pulse amplification device.
第1図は従来のパルス増幅装置を示すものであり1図に
おいて+11社人カパルス信号が入力される入力端、(
2)ね−この入力端にゲート電極か接続され。Figure 1 shows a conventional pulse amplification device.
2) Ne - Connect the gate electrode to this input terminal.
一方の主電極が接地される電界効果トランジスタからな
る増幅素子t (3a) (3b)はバイアス電源+4
)の十電位と接地との間に直列接続された一対のバイア
ス抵抗で、その接続点が上記増幅素子(2)のゲート電
極に接続されて、このゲート電極にバイアス電位を与え
るものである。(5)は主電源、(6)はこの主電源の
十電位と上記増幅素子(2)の他方の生電極との間に接
続さnだ主電源用フィルタで、インピーダンス素子(6
a)とコンデンサ(Sb)とから構成されているもので
ある。(7)は上記増幅素子(2)の他方の生電極と出
力端(8)との間に接続された直流阻止用コンデンサで
ある。The amplification element t (3a) (3b) consists of a field effect transistor whose one main electrode is grounded, and the bias power supply +4
A pair of bias resistors are connected in series between the 10 potentials of ) and the ground, and their connection point is connected to the gate electrode of the amplifying element (2) to apply a bias potential to the gate electrode. (5) is a main power supply; (6) is a filter for the main power supply connected between the ten potentials of this main power supply and the other live electrode of the amplification element (2);
a) and a capacitor (Sb). (7) is a DC blocking capacitor connected between the other live electrode of the amplifying element (2) and the output terminal (8).
この様に構成さnたパルス増幅装置においては。In the pulse amplification device configured in this way.
入力端(11に入力パルス信号が入力さnると、この人
カパルス伯号扛増幅素子121 Kより増幅されて直流
阻止用コンデンサ(7)を介して出力パルス信号として
出力端(8)から出力されるものである。When an input pulse signal is input to the input terminal (11), it is amplified by the amplifying element 121K and outputted as an output pulse signal from the output terminal (8) via the DC blocking capacitor (7). It is something that will be done.
しかるに、この様に構成されたパルス増幅装置にあって
は、l’−A級」または「AB級」などの増幅形式によ
って用いられる場合、大きいバイアス電流を常に流す必
要かおるため、必然的に大容量の主電源(51が要求さ
れ、しかも増幅素子(2)の電力損失が大きくなり、大
形の放熱器を要するという不具合が生じるものであった
。However, when a pulse amplifying device configured in this manner is used in an amplification format such as 1'-A class or AB class, it is necessary to constantly flow a large bias current. A main power source (51) with a large capacity is required, and the power loss of the amplifying element (2) becomes large, resulting in a problem that a large heat sink is required.
この発明は上記した点に鑑みてなされたものであシ、入
カパルス信号に同期して電源からの増幅素子への電力の
印加を開側1する開側j手段を設けて。The present invention has been made in view of the above-mentioned points, and includes an open side j means for opening the application of power from the power supply to the amplifying element in synchronization with the input pulse signal.
入力パルス信号が入力されたときに電源から増幅素子に
電力を印加するようにし、電源の電流容量を軽減させる
とともVC放熱器の小形化が図nるパルス増幅装置を提
案するものである。The present invention proposes a pulse amplifying device in which power is applied from a power source to an amplifying element when an input pulse signal is input, thereby reducing the current capacity of the power source and downsizing the VC heat sink.
以下にこの発明の一実施例を第2図に基づいて説明する
と1図において、(9)はリレー接点(り)及びリレー
コイル(9b)とからなるリレーで、リレーコイル(9
b)が励磁されるとリレー接点(9I!L)が閉成され
るものであり、上記リレー接点(%)は生布1源(5)
の十電位と主電源用フィルタ(6)との間に接続されて
いるものであり、リレーコイル(9b)の一端はリレー
電源OIの+電位に接続されているものである。0υは
入力パルス信号に同期した同期パルス信号が入力される
同期パルス入力端、(1zはペースがこの同期パルス入
力端に接続され、コレクタが上記リレーコイル(9b)
の他端に接続でれ、エミッタが接地さ扛るトランジスタ
で、上記同期パルス信号がペースに入力されると導通す
るものである。An embodiment of the present invention will be described below based on FIG. 2. In FIG. 1, (9) is a relay consisting of a relay contact (ri) and a relay coil (9b).
When b) is excited, the relay contact (9I!L) is closed, and the above relay contact (%) is the raw cloth 1 source (5)
, and the main power filter (6), and one end of the relay coil (9b) is connected to the + potential of the relay power source OI. 0υ is a synchronous pulse input terminal into which a synchronous pulse signal synchronized with the input pulse signal is input, (1z is a pace connected to this synchronous pulse input terminal, and a collector is connected to the above relay coil (9b)
Connected to the other end is a transistor whose emitter is grounded, and becomes conductive when the synchronization pulse signal is input to the pace.
なお、リレー(9)及びトランジスタa2により入力パ
ルス信号に同ル1して主電源(5)からの増幅素子(2
)への電圧の印加を制(Iする制御手jt’e構成する
ものである。また、入力パルス信号及び同期パルス信号
は例えは第3図←Xb)[示すような波形tしており、
その発生手段としては1例えは計算機によシ同期パルス
信号を発生させて、入力パルス信号を発生させるパルス
発生器に、上記同期パルス信号でトリガをかければ良い
ものであり、この場合。Note that the relay (9) and transistor a2 apply the same voltage to the input pulse signal to the amplifier element (2) from the main power source (5).
).The input pulse signal and the synchronous pulse signal have a waveform as shown in FIG. 3←Xb).
As a means for generating this, for example, a synchronous pulse signal may be generated by a computer, and a pulse generator that generates an input pulse signal may be triggered by the synchronous pulse signal, in this case.
同期パルス信号のパルス幅は入力パルス信号のパルス幅
よりも小さくならないようにすることが好ましいもので
ある。It is preferable that the pulse width of the synchronization pulse signal is not smaller than the pulse width of the input pulse signal.
次に、この様に構成さ扛たパルス増幅装置の動作につい
て説明する。Next, the operation of the pulse amplifying device constructed in this manner will be explained.
まず、入力パルス信号が入力端(11に印加されていな
い場合には、入力パルス信号に同期した同期パルス信号
も発生しないため、トランジスタQzハ非導通であり、
リレー(9)のリレーコイル(9b)は励磁されず、リ
レー接点(9a)は開放状態である。その結果、増幅素
子(2)Kは主電源(5)から電力の印加はなく、増幅
素子+21 Kおける電力損失はないものである。そし
て、入力パルス信号が入力端(1)に印加されると、入
力パルス信号に同期した同期パルス信号も発生するため
、トランジスタa2は導通状態となシ、リレー電諒01
−リレーコイル(9b)−トランジスタα2−接地と電
流が流れ、リレーコイル(9b)が励磁されて、リレー
接点(%)は閉成されることになる。その結果、増幅素
子(2)には主電源(5)から電力が印加されることに
なシ、入カパルス信号は増幅素子(2)によシ増幅され
て直流阻止用コンデンサ(7)を介して出力パルス信号
として出力端(8)から出力されることになるものであ
る。First, when the input pulse signal is not applied to the input terminal (11), a synchronous pulse signal synchronized with the input pulse signal is not generated, so the transistor Qz is non-conducting.
The relay coil (9b) of the relay (9) is not excited, and the relay contact (9a) is in an open state. As a result, no power is applied to the amplification element (2) K from the main power supply (5), and there is no power loss in the amplification element +21K. When the input pulse signal is applied to the input terminal (1), a synchronous pulse signal synchronized with the input pulse signal is also generated, so the transistor a2 is not in a conductive state and the relay terminal 01
Current flows between - relay coil (9b) - transistor α2 - ground, the relay coil (9b) is excited, and the relay contact (%) is closed. As a result, no power is applied to the amplifier element (2) from the main power supply (5), and the input pulse signal is amplified by the amplifier element (2) and passed through the DC blocking capacitor (7). This signal is output from the output terminal (8) as an output pulse signal.
従って、このパルス増幅装置にあっては、入力パルス信
号が入力端(1)に印加された時のみに増幅素子(2)
に主電源(5)の電圧が印加されるものであるので、主
電源(5)として大容量にする必要はなく。Therefore, in this pulse amplifying device, the amplifying element (2) is activated only when the input pulse signal is applied to the input terminal (1).
Since the voltage of the main power supply (5) is applied to the main power supply (5), there is no need for the main power supply (5) to have a large capacity.
(5)
しかも、増幅素子(2)の霜゛、力損失も少なくなるた
め。(5) Moreover, the frost and power loss of the amplifying element (2) are reduced.
放熱板も小さくでき、全体としても小形化が図れるもの
である。The heat sink can also be made smaller, and the overall size can be reduced.
なお、上記実施例においては、増幅素子(2)として電
界効果トランジスタを用いたものについて説明したが、
これに限定されるものではなく、真空管または一般に用
いられるトランジスタ等であっても同様の効果を奏する
ものである。In addition, in the above embodiment, a field effect transistor was used as the amplification element (2), but
The present invention is not limited to this, and similar effects can be achieved even with vacuum tubes, commonly used transistors, and the like.
また、上記実施例においては、リレー(9)とトランジ
スタ0′3とによシ制御手段を構成したものとしたが、
リレー(9)の変わりにアナログスイッチ等を用いても
良く、要は入力パルス信号に同期した同期パルス信号が
入力された時に増幅素子(2)に主電源(5)の電力が
供給されるようにするものであれば同様の効果を奏する
ものである。Furthermore, in the above embodiment, the control means was composed of the relay (9) and the transistor 0'3; however,
An analog switch or the like may be used instead of the relay (9), and the key is to supply power from the main power supply (5) to the amplifier element (2) when a synchronized pulse signal synchronized with the input pulse signal is input. The same effect can be achieved if the method is used.
さらに、このパルス増幅装置にあっては、A級。Furthermore, this pulse amplification device is Class A.
AB級はもちろんのことB級の増幅形式のものにも適用
できるものである。It can be applied not only to AB class but also to B class amplification type.
この発明は以上述べたように、パルス状の入力、0(6
)
信号が増幅素子によシ増幅されるパルス増幅装置におい
て、入力信号に同期して増幅素子への電源からの電圧の
印加を制御する制御手段を設けたので、入力信号が存在
するときに増幅素子に電源からの電圧が印加されるため
、′電源の電流容量を軽減でき、しかも増幅素子の電力
損失が少なく放熱器の小形化が図扛るという効果を有す
るものである。As described above, this invention has a pulse-like input, 0(6
) In a pulse amplification device in which a signal is amplified by an amplification element, a control means is provided to control the application of voltage from the power supply to the amplification element in synchronization with the input signal, so that the amplification is performed when the input signal is present. Since the voltage from the power source is applied to the element, the current capacity of the power source can be reduced, and the power loss of the amplifying element is small, making it possible to significantly reduce the size of the heat sink.
第1図は従来のパルス増幅装置を示す回路図。
第2図はこの発明の一実施例を示す回路図、第3図は入
力パルス信号及び同期パルス信号を示す時間特性図であ
る。
図において(1)は入力端、(2)は増幅素子、(5)
は主電源、(8)は出力端、(9)は制御手段のリレー
、(lυは同期パルス入力端、(+2は制御手段のトラ
ンジスタである。
なお、各図中同一符号は同−又は相当部分を示す。
代理人 大 岩 増 雄(ほか2名)
(1)FIG. 1 is a circuit diagram showing a conventional pulse amplification device. FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a time characteristic diagram showing an input pulse signal and a synchronizing pulse signal. In the figure, (1) is the input terminal, (2) is the amplification element, and (5)
is the main power supply, (8) is the output terminal, (9) is the relay of the control means, (lυ is the synchronous pulse input terminal, (+2 is the transistor of the control means. In addition, the same symbols in each figure are the same - or equivalent Parts are shown. Agent Masuo Oiwa (and 2 others) (1)
Claims (1)
て出力する増幅素子と、この増幅素子に電圧印加する電
源を有するものにおいて、上記入力信号に同期して上記
電源からの増幅素子への電圧の印加を制御する開側1手
段を備えたパルス増幅装置。In a device having an amplifying element that receives a pulsed input signal, amplifies the input signal, and outputs the amplified signal, and a power source that applies a voltage to the amplifying element, the input signal from the power source to the amplifying element is synchronized with the input signal. A pulse amplification device equipped with one open side means for controlling the application of voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611084A JPS60189318A (en) | 1984-03-07 | 1984-03-07 | Pulse amplifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611084A JPS60189318A (en) | 1984-03-07 | 1984-03-07 | Pulse amplifying device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60189318A true JPS60189318A (en) | 1985-09-26 |
Family
ID=12737850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4611084A Pending JPS60189318A (en) | 1984-03-07 | 1984-03-07 | Pulse amplifying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189318A (en) |
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