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JPS60189264A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS60189264A
JPS60189264A JP59042932A JP4293284A JPS60189264A JP S60189264 A JPS60189264 A JP S60189264A JP 59042932 A JP59042932 A JP 59042932A JP 4293284 A JP4293284 A JP 4293284A JP S60189264 A JPS60189264 A JP S60189264A
Authority
JP
Japan
Prior art keywords
silicon
semiconductor
substrate
single crystal
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59042932A
Other languages
Japanese (ja)
Inventor
Ichiro Moriyama
森山 一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59042932A priority Critical patent/JPS60189264A/en
Publication of JPS60189264A publication Critical patent/JPS60189264A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

Landscapes

  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an SOI structural MIS semiconductor device using especially a seed by a method wherein a substrate is used as one of wirings by connecting the substrate to the source or the drain of a transistor to be held in the same electric potential therewith, or a single crystal of semiconductor is formed on the substrate exposing a part thereof, and moreover a single crystal thin film is formed using the single crystal thereof as a seed crystal. CONSTITUTION:A silicon oxide film 10 is formed on a silicon substrate 9 similarly as usual, a hole is opened at a part thereof, and the silicon substrate is exposed to form a seed region. Then, after the substrate is washed, a silicon film is grown on the whole surface, and moreover, the surface is polished to flatten the surface as to leave the silicon film on the silicon oxide film 10. Then the silicon is molten using annealing technique, recrystallized from the seed, and a silicon single crystal thin film 13 containing no impurity is formed. Then, the silicon single crystal thin film 13 is patterned to form a silicon island as to make the seed region to exist under the thin film thereof. After then, impurity ions are implanted with a high accelerating voltage as to dope only the seed region 11 without using a mas to the silicon single crystal of the seed region 11.

Description

【発明の詳細な説明】 本発明はMIS型半導体装置の構造及び製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure and manufacturing method of a MIS type semiconductor device.

絶縁体上に設けられた半導体薄膜に形成したMIS型半
導体装置、いわゆるSOI(8emi−conduct
or on In5ulator )構造のMis型半
導体装置は従来のMIS型半導体装置に比較して接合容
量及び配線容量が小さく素子間の分離が簡便かつ完全で
あることから大規模集積回路(LSI)に適した半導体
装置として注目されている。
MIS type semiconductor devices formed on semiconductor thin films provided on insulators, so-called SOI (8 emi-conduct
MIS-type semiconductor devices with a (or on inverter) structure have smaller junction capacitance and wiring capacitance than conventional MIS-type semiconductor devices, and isolation between elements is simple and complete, making them suitable for large-scale integrated circuits (LSI). It is attracting attention as a semiconductor device.

第1図の(alは従来のMID)ランジスタ、(b)は
80I構造のM工Sトランジスタの模式的断面図である
。ここで1は半導体基板、2は絶縁膜、3はゲート電極
、4は配線金属、5は層間絶縁膜、6は半導体薄膜に対
応する。しかしながらSOI構造のMIS)ランジスタ
において、層間絶縁膜上によい結晶性の半導体薄膜を均
一にしかも人面積につくることは非常に困難であり大き
な問題であった。この問題を解決する一つの方法として
、半導体基板1を種結晶(シード)として用い半導体薄
膜6を成長させる方法がある。
FIG. 1 (al is a conventional MID) transistor, and FIG. 1 (b) is a schematic cross-sectional view of an 80I structure M-S transistor. Here, 1 corresponds to a semiconductor substrate, 2 an insulating film, 3 a gate electrode, 4 a wiring metal, 5 an interlayer insulating film, and 6 a semiconductor thin film. However, in an MIS transistor having an SOI structure, it is very difficult to form a semiconductor thin film of good crystallinity on an interlayer insulating film uniformly and in a large area, which is a big problem. One method for solving this problem is to grow the semiconductor thin film 6 using the semiconductor substrate 1 as a seed crystal.

第2図の(aJ〜(d)はシードを用いた80I構造の
製造方法の主要工程を示した模式的断面である。
FIG. 2 (aJ to (d)) are schematic cross-sections showing the main steps of a method for manufacturing an 80I structure using seeds.

まず(a)図に示すように半導体基板1の上に絶縁膜5
を形成しその一部に穴をあけてシード領域を形成する。
First, an insulating film 5 is placed on a semiconductor substrate 1 as shown in FIG.
A seed region is formed by forming a hole in a part of the hole.

次にfb1図fこ示ずように、その全面に多結晶あるい
は非晶質の半導体薄膜7をCVD法等により堆積する。
Next, as shown in Figure fb1, a polycrystalline or amorphous semiconductor thin film 7 is deposited on the entire surface by CVD or the like.

次に(C)図に示すように、これをレーザーアニールま
たは電子ビームアニール等のアニール技術を用いて溶融
しシードから再結晶化させ単結晶の半導体薄膜6を形成
する。次に(d)図に示すように、半導体装置の活性層
となるべき半導体薄膜6の一部分を分離して完了する。
Next, as shown in Figure (C), this is melted using an annealing technique such as laser annealing or electron beam annealing and recrystallized from the seed to form a single crystal semiconductor thin film 6. Next, as shown in FIG. 3(d), a portion of the semiconductor thin film 6 which is to become the active layer of the semiconductor device is separated and completed.

しかしながら上記方法は半導体薄膜の結晶性を向上させ
ることはできるが新たにシード領域を設ける必要がある
ため集積度を大幅に低ドさせる原因となる。
However, although the above method can improve the crystallinity of the semiconductor thin film, it is necessary to newly provide a seed region, which causes a significant reduction in the degree of integration.

また、続く工程においてシード領域に不必要な不純物が
導入されないように保護する必要があるため工程数が増
加するという問題が生じ実用上充分な方法ではなかった
Furthermore, since it is necessary to protect the seed region from introducing unnecessary impurities in subsequent steps, there is a problem that the number of steps increases, and this method is not sufficient in practice.

また、集積回路のLSI化にともない配線のレイアウト
の最適化も半導体装置の構造の最適化と同様に重要な問
題の一つである。一般に配線レイアウトは次の基本的規
則に制約される。(1) 異なる目的の配線(例えば入
力信号線と出力信号線)は接触してはならない。(2)
配線層数、配線の幅、配線間の間隔には製造プロセスで
規定される下限値がある。(3)スルーホールの形、数
、位置により配線領域が制約される。従って配線のレイ
アウトは上記規則にのっとり最適化をおこなう必要があ
るために非常に困難な作業となっていた。近年。
Furthermore, with the shift to LSI integrated circuits, optimizing the layout of interconnections is one of the important issues as well as optimizing the structure of semiconductor devices. In general, wiring layout is constrained by the following basic rules. (1) Wiring for different purposes (for example, input signal lines and output signal lines) must not touch. (2)
The number of wiring layers, the width of wiring, and the spacing between wiring have lower limits determined by the manufacturing process. (3) The wiring area is restricted by the shape, number, and position of the through holes. Therefore, the wiring layout has to be optimized in accordance with the above rules, making it a very difficult task. recent years.

LSI化による配線の複雑化に対処して2層あるいは3
層の多層配線が一般しつつある。しかしながら、多層配
線を用いてもスルーホールによる配線領域の制限はLS
Iが大規模になれば増々ふぇるものであり、充分な技術
ではなかった。この問題は前記SOI構造のMIS I
−ランジスタを含む半導体装置においても同様であり、
重要な問題となっていた。
2 or 3 layers to cope with the complexity of wiring due to LSI
Multilayer wiring is becoming common. However, even if multilayer wiring is used, the wiring area is limited by through holes.
As I became larger, it became more and more difficult, and the technology was not sufficient. This problem is solved by the MIS I of the SOI structure.
- The same applies to semiconductor devices including transistors,
It had become an important issue.

本発明は上記欠点を除去したMIS型半導体装置、特に
シードを用いた80I構造のMIS型半導体装置の構造
及びその実用的な製造方法を提供することを目的とする
SUMMARY OF THE INVENTION An object of the present invention is to provide a MIS type semiconductor device which eliminates the above-mentioned drawbacks, particularly an 80I structure MIS type semiconductor device using a seed, and a practical manufacturing method thereof.

本発明によれば、低抵抗の半導体基板上に絶縁膜を介し
設けられた半導体薄膜に形成されるMI8トランジスタ
を含む半導体装置において、このトランジスタのソース
またはドレインと半導体基板とを接続し同電位に保つこ
とにより、半導体基板を半導体装置の配線の一つとして
用いることを特徴とする半導体装置を得る。
According to the present invention, in a semiconductor device including an MI8 transistor formed in a semiconductor thin film provided on a low-resistance semiconductor substrate via an insulating film, the source or drain of this transistor and the semiconductor substrate are connected to have the same potential. By holding the semiconductor substrate, a semiconductor device characterized in that the semiconductor substrate is used as one of the wirings of the semiconductor device is obtained.

さらに、不純物半導体基板上にその一部分が露出するよ
うに絶縁膜を形成し、しかる後前記半導体基板中の不純
物がほとんど拡散しない程度の低温でその全面に上記半
導体原子をエピタキシャル成長させることにより少くな
くとも一部露出した上記半導体基板上にほとんど不純物
を含まない半導体の単結晶を形成し、更にそれを種結晶
として絶縁膜上にほとんど不純物を含まない半導体の単
結晶薄膜を形成することを特徴とする半導体装置の製造
方法を得る。
Furthermore, an insulating film is formed on the impurity semiconductor substrate so that a portion thereof is exposed, and then the semiconductor atoms are epitaxially grown on the entire surface at a low temperature such that impurities in the semiconductor substrate hardly diffuse. It is characterized by forming a semiconductor single crystal containing almost no impurities on the partially exposed semiconductor substrate, and using this as a seed crystal to form a semiconductor single crystal thin film containing almost no impurities on the insulating film. A method for manufacturing a semiconductor device is obtained.

本発明による80I構造のMIS型半導体装置の模式的
断面図を第3図に示す。ここで2.3゜4.5.6は第
1図と同等物であり、8は低抵抗の不純物半導体基板で
ある。本発明(1)の特徴は次の2点に集約される。一
つはシード領域を半導体装置(図中の半導体薄膜6)の
下に設けた点であり、もう一つは半導体基板8を半導体
装置の配線として積極的に用いた点である。前者の場合
、シード領域が半導体薄膜8に覆われた形となるため集
積度はシードを用いない80I構造のMIS型半導体装
置と同様であり、またシード領域を保護する必要がない
ので工程数が短縮され、しかもシードが半導体装置の活
性層に近いのでより結晶性のよい活性層を形成できると
いう利点がある。一方後者の場合、半導体基板8を半導
体装置のソースまたはドレインの配線、具体的には電源
線として用いることができるので、半導体装置の表面に
ソースまたはドレインの配線を必要としない。従って表
面の配線のレイアウトにおいて配線1本およびそれに対
応するスルーホールが減少したことになり配線の自由度
が大幅に増大し設計も非常に容易になり高集積化できる
という利点がある。このように本発明ζこよれば高集積
で結晶性がよく、しかも配線の自由度が大きいSOI構
造のMIS型半導体装置が得られる。
FIG. 3 shows a schematic cross-sectional view of an MIS type semiconductor device having an 80I structure according to the present invention. Here, 2.3°4.5.6 is equivalent to that in FIG. 1, and 8 is a low resistance impurity semiconductor substrate. The features of the present invention (1) can be summarized in the following two points. One is that the seed region is provided under the semiconductor device (semiconductor thin film 6 in the figure), and the other is that the semiconductor substrate 8 is actively used as wiring for the semiconductor device. In the former case, the seed region is covered with the semiconductor thin film 8, so the degree of integration is the same as that of an 80I structure MIS semiconductor device that does not use a seed, and the number of steps is reduced because there is no need to protect the seed region. Moreover, since the seed is close to the active layer of the semiconductor device, there is an advantage that an active layer with better crystallinity can be formed. On the other hand, in the latter case, the semiconductor substrate 8 can be used as a source or drain wiring of the semiconductor device, specifically, as a power supply line, so there is no need for source or drain wiring on the surface of the semiconductor device. Therefore, in the layout of the wiring on the surface, one wiring and the corresponding through hole are reduced, which greatly increases the degree of freedom in wiring, which greatly simplifies the design and has the advantage of being highly integrated. As described above, according to the present invention, a MIS type semiconductor device having a highly integrated SOI structure with good crystallinity and a large degree of freedom in wiring can be obtained.

次にその製造方法について述べる。本発明の構造を実現
しようとするならば、従来の構造を得るために開発され
た方法(第2図)は適当ではない。
Next, the manufacturing method will be described. If the structure of the invention is to be realized, the method developed for obtaining the conventional structure (FIG. 2) is not suitable.

というのは、従来の工程で本構造を実現するためにはシ
ードとして低抵抗すなわち高濃度の不純物を含んだ半導
体基板を用い、第2図の(b)に示すように、その表面
に多結晶の半導体薄膜を堆積させ、次lこ(C)に示す
ようIこ、これをレーザーアニールまたは電子ビームア
ニール等のアニール技術を用い溶融しシードから再結晶
化させなければならない。
This is because, in order to realize this structure using conventional processes, a semiconductor substrate with low resistance or high concentration of impurities is used as a seed, and as shown in Figure 2(b), a polycrystalline layer is formed on the surface of the semiconductor substrate. A semiconductor thin film is deposited, and then it must be melted and recrystallized from a seed using an annealing technique such as laser annealing or electron beam annealing, as shown in (C).

しかしながら、半導体装置の活性層となる半導体薄膜は
半導体装置の設計上真性半導体であることが必要なのに
対しシードは高濃度の不純物半導体基板であるために、
シードである半導体基板の融点が半導体薄膜の融点より
低下し再結晶化はシードからではなく、むしろ半導体薄
膜から始まることになり、また半導体薄膜中に半導体基
板から不純物が拡散するという問題が生じるからである
However, the semiconductor thin film that becomes the active layer of the semiconductor device must be an intrinsic semiconductor due to the design of the semiconductor device, whereas the seed is a highly concentrated impurity semiconductor substrate.
This is because the melting point of the semiconductor substrate, which is a seed, is lower than the melting point of the semiconductor thin film, and recrystallization begins not from the seed but rather from the semiconductor thin film, and there is also the problem that impurities from the semiconductor substrate diffuse into the semiconductor thin film. It is.

以下に本発明の構造を実現するためlこ工夫した本発明
の製造方法についてシリコン基板を用いた80I構造の
NMO8またはPMO8トランジスタに対する実施例を
もとに詳細に説明する。第4囚のfa)〜(d)は本発
明lこよる製造方法の主要工程を示した模式的断面図で
ある。ここで9は高濃度に不純物を含んだ低抵抗の単結
晶シリコン基板、 10はシリコン酸化膜、11はシー
ド領域のシリコン単結晶、12はシリコン多結晶薄膜、
13はシリコン単結晶薄膜に対応する。尚、シリコン基
板9は上部に”::8MO8トランジスタを形成する時
は例えばAsを111Jr−パントとしたN形シリコン
基板(不純物濃度骨1刈O町ヱー3.ρご1刈0−30
・α)、上部にPMOSトランジスタを形成する時は例
えばボロンをドーパントとするP形シリコン基板(不純
物濃度tt1.l’lI3.。
The manufacturing method of the present invention, which has been devised in order to realize the structure of the present invention, will be described in detail below based on an example of an 80I structure NMO8 or PMO8 transistor using a silicon substrate. Part 4, fa) to (d), are schematic cross-sectional views showing the main steps of the manufacturing method according to the present invention. Here, 9 is a low-resistance single crystal silicon substrate containing impurities at a high concentration, 10 is a silicon oxide film, 11 is a silicon single crystal in a seed region, 12 is a silicon polycrystalline thin film,
13 corresponds to a silicon single crystal thin film. In addition, when forming a "::8 MO8 transistor on the upper part of the silicon substrate 9, for example, an N-type silicon substrate with As 111Jr-punto (impurity concentration bone 1 0-3.ρ 1 0-30) is used.
・α) When forming a PMOS transistor on the upper part, a P-type silicon substrate doped with boron, for example (impurity concentration tt1.l'lI3.

上にシリコン酸化膜10をCVD法により1.0μm形
成しそので部に穴をあけシリコン基板を露出さBE)に
より基板温度600℃、成長速度1^ン5eCIlで2
μ7n厚のシリコン膜を全面に成長させ、さらに表面を
研摩2(メカノケミカルポリッシング〕してシリコン酸
化膜10上に0.5μmのシリコン膜が残るように平坦
化する。基板温度が600℃という低温であるためシー
ド領域にはほとんど不純4M含まないシリコン単結晶1
1が形成され一方シリ、−1示すようにこれをレーザー
アニールまたは電子ビームアニール等のアニール技術を
用い溶融yB:1=コン単結晶薄膜13をパターンニン
グして下にシード領域が存在するようにシリコン島を形
成する。
A silicon oxide film 10 with a thickness of 1.0 μm was formed on the film by CVD, and a hole was made in the film to expose the silicon substrate.
A silicon film with a thickness of 7 nm is grown over the entire surface, and the surface is further polished 2 (mechanochemical polishing) to flatten it so that a 0.5 μm silicon film remains on the silicon oxide film 10.The substrate temperature is as low as 600°C. Therefore, the seed region contains silicon single crystal 1 containing almost no impurity 4M.
1 is formed and silicon, -1 is melted using an annealing technique such as laser annealing or electron beam annealing as shown in FIG. Forms silicon islands.

そのあとシード領域11のシリコン単結晶に不純物(基
板がN形のとき、例えばリンをドーズ量lX1016c
IrL′、基板がP形のとき、例えばボロンをドーズ量
I X 10”cm−2) をマスクなしで、シード領
域11にのみドープされるように高加速電圧でイオン注
入して本発明の製造工程の一例が完了する。
After that, the silicon single crystal of the seed region 11 is doped with an impurity (for example, phosphorus at a dose of lX1016c when the substrate is N type).
IrL', when the substrate is P-type, the present invention is manufactured by implanting, for example, boron at a dose of I x 10"cm-2) without a mask at a high acceleration voltage so that only the seed region 11 is doped. An example process is completed.

ここに例示した本発明の製造方法によnば、シードとな
る半導体基板がN形やP形lこ関係なく真性の半導体薄
膜を形成することができ、しかも目合わせ工程は従来方
法と同じであり、比較的簡単に本発明による前記構造を
実現できる点で画期的なものである。
According to the manufacturing method of the present invention illustrated here, an intrinsic semiconductor thin film can be formed regardless of whether the semiconductor substrate serving as a seed is N type or P type, and the alignment process is the same as in the conventional method. This is revolutionary in that the structure according to the present invention can be realized relatively easily.

以上、シリコン基板を用いたSO1構造の!NMO8お
よびPMOSトランジスタの製造方法を例にとり説明し
てきたが他の半導体基板(ガリウム等)でも実施できる
ことは明らかであり、また0MO8構成の回路について
もNMO8またはPMO81−ランジスタのいずれか一
方の配線を基板と接続すればよいので本発明は有効であ
る。
Above is the SO1 structure using silicon substrate! Although the method for manufacturing NMO8 and PMOS transistors has been explained as an example, it is clear that the method can be implemented using other semiconductor substrates (such as gallium), and also for circuits with 0MO8 configuration, the wiring of either the NMO8 or PMO81-transistor can be connected to the substrate. The present invention is effective because it is only necessary to connect the

【図面の簡単な説明】[Brief explanation of drawings]

第1図のfatは従来のMIS型半導体装置の模式的断
面図、(blは従来のSOI構造のMIS型半導体装置
の模式的断面図である。第2図(a) 、 (b) 、
 tc+ 。 (dlは従来のSOI構造の製造方法を説明する図で主
要工程における基板断面を順次示す図である。 1第3図は本発明によるSOI構造のMIS型半導体装
置の模式的断面図である。第4図1al 、 tbl 
、 (C) 。 (d)は本発明によるSOI構造の製造方法を説明する
図で主要工程ζこおける基板の断面を順次示す図である
。 図中の1は半導体基板%2は絶縁膜、3はゲート電極、
4は配線金属、5は眉間絶縁膜、6は半導体薄膜、7は
半導体多結晶薄膜、8は低抵抗の不純物半導体基板、9
は低抵抗のシリコン基板、10ハシリコン酸化膜、11
はシード領域のシリコン単結晶、12はシリコン多結晶
薄膜、13はシリコン単結晶薄膜である。 乎 1 回 亭 2 図 (a) (b) (c) (d)
In FIG. 1, fat is a schematic cross-sectional view of a conventional MIS type semiconductor device, (bl is a schematic cross-sectional view of a conventional MIS type semiconductor device with SOI structure. Figures 2 (a), (b),
tc+. (dl is a diagram illustrating a conventional SOI structure manufacturing method and sequentially shows substrate cross sections in main steps. 1. FIG. 3 is a schematic sectional view of an MIS type semiconductor device with an SOI structure according to the present invention. Figure 4 1al, tbl
, (C). (d) is a diagram illustrating a method for manufacturing an SOI structure according to the present invention, and is a diagram sequentially showing cross sections of a substrate in main steps ζ. In the figure, 1 is the semiconductor substrate, 2 is the insulating film, 3 is the gate electrode,
4 is a wiring metal, 5 is an insulating film between eyebrows, 6 is a semiconductor thin film, 7 is a semiconductor polycrystalline thin film, 8 is a low resistance impurity semiconductor substrate, 9
is a low-resistance silicon substrate, 10 is a silicon oxide film, and 11 is a silicon oxide film.
12 is a silicon single crystal thin film in the seed region, 12 is a silicon polycrystalline thin film, and 13 is a silicon single crystal thin film.乎 1. 2 Figures (a) (b) (c) (d)

Claims (2)

【特許請求の範囲】[Claims] (1) 低抵抗の半導体基板上に絶縁膜を介して設けら
れた半導体薄膜に形成されるMIS1−ランジスタを含
む半導体装置において、このトランジスタのソースまた
はドレインと半導体基板とを接続し同電位に保つことに
より、半導体基板を半導体装置の配線の一つとして用い
ることを特徴とする半導体装置。
(1) In a semiconductor device including a MIS1 transistor formed in a semiconductor thin film provided on a low-resistance semiconductor substrate via an insulating film, the source or drain of this transistor and the semiconductor substrate are connected and kept at the same potential. A semiconductor device characterized in that the semiconductor substrate is used as one of the wirings of the semiconductor device.
(2)不純物半導体基板上にその一部分が露出するよう
に絶縁膜を形成し、しかる後前記半導体基板中の不純物
がほとんど拡散しない程度の低温でその全面に上記半導
体原子をエピタキシャル成長させることにより少くすく
とも一部露出した上記半導体基板上にほとんど不純物を
含まない半導体の単結晶を形成し、更にこれを種結晶と
して絶縁膜上にほとんど不純物を含まない半導体の単結
晶薄膜を形成することを特徴とする半導体装置の製造方
法。
(2) Forming an insulating film on the impurity semiconductor substrate so that a portion of the impurity is exposed, and then epitaxially growing the semiconductor atoms on the entire surface at a low temperature such that the impurities in the semiconductor substrate hardly diffuse. A semiconductor single crystal containing almost no impurities is formed on the partially exposed semiconductor substrate, and this is used as a seed crystal to form a semiconductor single crystal thin film containing almost no impurities on the insulating film. A method for manufacturing a semiconductor device.
JP59042932A 1984-03-08 1984-03-08 Semiconductor device and manufacture thereof Pending JPS60189264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59042932A JPS60189264A (en) 1984-03-08 1984-03-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59042932A JPS60189264A (en) 1984-03-08 1984-03-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS60189264A true JPS60189264A (en) 1985-09-26

Family

ID=12649784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59042932A Pending JPS60189264A (en) 1984-03-08 1984-03-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS60189264A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766627A (en) * 1980-10-13 1982-04-22 Toshiba Corp Manufacture of semiconductor device
JPS5893270A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS58175821A (en) * 1982-04-08 1983-10-15 Toshiba Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766627A (en) * 1980-10-13 1982-04-22 Toshiba Corp Manufacture of semiconductor device
JPS5893270A (en) * 1981-11-30 1983-06-02 Toshiba Corp Manufacture of semiconductor device
JPS58175821A (en) * 1982-04-08 1983-10-15 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode

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