JPS60181834A - Decimal arithmetic processor - Google Patents

Abstract

PURPOSE:To increase a decimal arithmetic speed by using the lower two-digit unit out of the decimal data stored in a main memory. CONSTITUTION:The lower two digits of the arithmetic subject data which are used as augends are loaded to a register R1; while the lower two digits of the arithmetic subject data which are used as addends are loaded to a register R2. An addition (R1)+(R2)+(F/F) is carried out by an adder 53 and loaded in common to registers R3 and R4. The fixed value 6616 is added to the contents of the R4 to obtain an addition result, and an exclusive OR is obtained between said addition result and the fixed 11016 to obtain an intermediate result Q1. Then a multiplier 60 multiplies a division result Q1divided by 1016 of a divider 59 by the fixed value 66 to obtain an intermediate result Q2. This Q2 is added to the contents (R3) of the register R3, and the result of this addition is loaded to a shift register SR. The contents of the register SR are transferred to a CPU10 or a main memory 20 via an output bus 43.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a decimal performance processing device that applies a new data format of 10-adic data.

[Technical background of the invention and its problems]

Conventionally, decimal data applied in a decimal arithmetic processing device, for example, an office arithmetic processing device, has been expressed in the data format shown in FIG. The data in Figure 1 is 2 bytes (16
This shows an example of (bit) data, where D and -D represent numerical data, and S represents code data. Numerical data Di and code data S have a byte (4 bit) configuration. The three-digit data D1D and D3 are absolute value data, and their signs are indicated by sign data S. The code data S is “11
00', that is, C1, (the subscript 16 indicates hexadecimal representation) indicates positive (including zero), and "1101", that is, D16
indicates negative.

In this way, the lO-decimal data applied in conventional arithmetic processing devices requires a code digit for the code data S, and an area for this is required in the memory (main memory, external memory m). I was 13 years old.Since the four arithmetic operations using this kind of 10-adic data are based on operations on absolute value data, operations on data with opposite signs had the disadvantage of requiring sign conversion processing before and after the operation. For example, the procedure for adding -8 and 2 is: ■ Reading data (-8) from main memory Reading data (+2) from main memory ■ Complement conversion (sign conversion) for -8 ■ Step ■ Addition of converted data and 2■
Complement conversion of the addition data obtained in step ■ (this converted data becomes the result) ■ Storing the result obtained in step ■ in main memory,
As shown in steps ① and ②, two-complement conversion (code conversion) processing was required. For this reason, conventional office arithmetic processing devices (decimal arithmetic processing devices) have the disadvantage that arithmetic speed decreases due to complement conversion processing. It also had to be equipped with a conversion function for complement conversion.

[Purpose of the invention]

This proposal was made in view of the above circumstances, and its purpose is to provide a decimal arithmetic processing device that can efficiently use memory space to store decimal data and speed up decimal arithmetic operations. It's about doing.

[Summary of the invention]

In this invention, one digit consists of 4 bits, and the most significant digit is a hexadecimal value rOJ ~ "8" and a decimal value "0" ~ "8".
'', the hexadecimal value "9" is used as a numeric/sign shared data digit to indicate negative sign numeric data in complement representation, and the remaining digits are used as numeric data digits. Complement representation data format lo decimal A main memory is provided in which various types of data are stored. The arithmetic means successively outputs first and second IO-adic data to be calculated from among the IO-adic data stored in the main memory during the IO-adic calculation,
Calculations between these data are performed in units of two digits starting from the lower digit.

In this two-digit operation, the two-digit data to be calculated is i
Then, the arithmetic means calculates a two-digit data j by adding the carry output in the preceding two-digit unit calculation with h and i, and uses this data j to calculate [((j +6
616)■(h■1))ANDIIOI. ]÷1o,
, X 61. By performing the calculation −1− j, two-digit addition data is obtained.

[Embodiments of the invention]

FIG. 2 shows the configuration of an office arithmetic processing device 4 according to an embodiment of the present invention. In the figure, IO is a CPU which controls the entire device and also performs normal instruction processing, and 20 is a main memory. The main memory 20 contains, for example, an office calculation instruction +(μ
Below, programs including BPH order +), various decimal data, etc. are stored. FIG. 3 shows the data format of decimal data applied in this embodiment. The format shown in FIG. 3 is a 2-byte (16-bit) data platform. In the figure, the most significant digit /8 indicates numerical/code shared data, and the remaining digits D2 to D4 indicate numerical data. Specifically, D1/S is O+a ('0000') ~ 81
．． If l ('1000"), the decimal value "0" ~ "
8" is shown with a positive sign. Same (D1/8 is
If 9+e (“1001”), the negative sign lO in complement representation
Indicates hex value data. The new data format shown in FIG. 3 is called a complement representation data format. Table 2 shows the data representation capability of decimal data of the complement representation data formula shown in FIG.

As is clear from Table 1, the complement representation data format decimal data (2 bytes) in Figure 3 ranges from -1000 to +89.
99 numerical expressions are possible. On the other hand, the numerical representation ability of the conventional format decimal data (2 bytes) in Figure 1 is -9
99 to +999, which is significantly inferior to decimal data in the complement representation data format.

Referring again to FIG. 2, 30 is a business processing unit (hereinafter referred to as BPHU) that executes BPH instructions. The B PHU 30 includes an arithmetic control section 3I that controls the entire unit according to instructions from the CPUzo, and an arithmetic processing logic that performs office arithmetic processing under the control of the arithmetic control section 3I. 4I is a control bus for transferring control information from CPUzO, 42 is an input bus, and 43 is an output bus. BPHU3° is coupled to CPU10 via these buses 41-43.

FIG. 4 shows the internal configuration of the arithmetic processing logic 32. In the figure, FLr, F+, and t are registers that hold data on the input bus 42, and 5Z and 52 are multiplexers (hereinafter referred to as MPX). MPXsr is the output data from register R1, fixed value r6616J("
01100110"), a flip-flop 54 to be described later.
Either the output data from the register R3 or the output data from the register R3 is selectively output. Also, MPXsz
selectively outputs any one of output data from register R2, output data from register R4 (described later), or output data from multiplier 6o.

53 is a 2-digit (1 byte) adder that adds each selected output data from MPX5Z and 52; 54 is a flip-flop that holds the carry signal from adder 53; Tsubu' (hereinafter referred to as
(referred to as F/F).

R13 and TL4 are registers that hold output data from the adder 53, and SR is also a shift register. Output data from shift register 8FL is guided to output bus 43.

55 is an MPX (multiplexer) for selectively outputting one of the output data from registers RZ, R, (; 56;
is an MPX (multiplexer) that selectively outputs either one of the output data from register R2 or registers R.5 to be described later. 57 is MPX55. Exclusive OR circuit (hereinafter referred to as EX-OR) that calculates exclusive OR of each selected output data from s e, R5 is EX-011
A register that holds output data from L57, 58 is I
Output data from D X -ORs 7 and fixed value r11
016J<“100010000”) This is an AND gate (hereinafter referred to as AND) that performs a logical product with 016J<“100010000”). 5
9 is the output data from ANDs & 1ffi constant value rlO
+aJ ('ooootooooo") is the divider, and 60 is the output data from the divider 59 with a fixed value r6J (
"000000110").

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart shown in FIG. Assume that the BPH instruction placed in the main memory 2θ is now taken into the CPUrO. C.P.
U10 transfers information necessary for executing the instruction, such as the instruction code, data size, and operand address, from the attributes of the BPH instruction to the BPH 030 via the controller bus 4I.

The calculation control unit 3Z in the BPHUso is connected to the control bus 4.
According to the information (operand address, etc.) transferred from Z, the lO-adic data to be calculated is taken from the main memory 20 to the calculation processing logic 32 via the human power bus 42. At this time, the data to be calculated is taken into the calculation processing logic 32 in units of two digits starting from the lower digits. In this example, assuming that the BPH instruction specifies addition, the lower two digits of the operation target data, which will be the summand, are first loaded into the register Rz as the summand data A (step 8z). Next, the lower two digits of the data to be operated on as the addend are loaded into register R2 as addend data B (step 82).
.

Next, the contents of registers FLI, R, 2 and F/F
Adding the output bits from 54 and register RJ
, a process of loading it into FL4 (step S3) is performed. This step S3 is performed, for example, as follows. First, the output bit from the F/F 54 is selected by the MPX 57, and the output data from the register R2 is selected by the MPX 52. Thus, the adder 53 performs addition between the selected output data from the MPXs 5z and 52, that is, (F/F)+(R2)3. The addition result of adder 53 is loaded into register R4. Next, MPX51 selects the output data from register I, and MPX521 selects the output data from register R4. Thus, the adder 53 performs addition between each selected output data from MPX5I, s2, that is, (H, I) + (R4). The hO calculation result (R, I) + (R4) of the adder 63, that is, (R, z) + (11, 2) + (F/F) is stored in the register R,
Commonly loaded to s, R,4. In addition, F/F5
4 (F/F) indicates the carry output from the adder 53 in the previous two-digit operation. In the case of the first calculation as in this example, it is (F/F)-2'O'.

When step S3 is completed, register RZ.

A process (step S4) is performed in which the contents of R2 are exclusive-ORed and the result is loaded into register R5. The specific processing contents in step S4 are as follows. First, the MPX55 selects the output data from the register R,1, and the MPX56 selects the output data from the register R2. However,
EX-OFLs 7 performs exclusive OR between each selected output data from MPXss and se.

Output data from EX-0 几57, i.e. (几7)
+(R,,?) is loaded into register R75.

When step S4 is completed, the addition result obtained by adding the fixed value r66t6j to the contents of register R4 and register R
Take the exclusive OR with the contents of 5 and set the result and the fixed value r
A process of calculating the logical product with llO+aJ (step S5) is performed. The specific processing contents in step S5 are as follows. First, pass MPX51 to a fixed value [
6616J is selected, and MPX5. ? The output data from register R4 is selected by. Thus, the adder 53 performs addition between the selected output data from the MPXs 5Z and 52, that is, 661g'' (FL4).The addition result 661.+(R4) of the adder 53 is added to the register R, , MPX55 to EX-OR, 57. This EX-OR57 is also supplied with output data from register R5 via MPX56. An exclusive OR is taken between the selected output data. Next, A
The ND58 outputs the output data from the EX-OR57, that is, ((R・4)+661,1■(R5)) and the fixed value "11
01. ” and an intermediate result Qt is obtained.

When step S5 is completed, the output data from AND5B is divided by the fixed value [10saJ, and this result is added to the fixed value "6
6'' (step 86) is performed. That is, in step S6, the divider 59 first calculates AND S
Processing is performed to divide the output data from 8 by a fixed value l016. Next, the multiplier 6o multiplies the division result Q1÷10.6 of the divider 59 by a fixed value "66" to obtain an intermediate result Q2.

When step S6 is completed, the multiplication result Q2 of the multiplier 60 is
and the contents of register R3 (R3), and the result is loaded into shift register SR (step 87).

That is, in step S7, the MPX5Z first selects the output data from the registers R,s, and the MPX5Z selects the output data from the registers R,s.
52 selects the multiplication result of multiplier 60. Then, the adder 53 performs addition between the selected output data from the MPXs 51 and 52, that is, (R3)+Q,2. The addition result (1 byte) of the adder 53 is loaded into the upper two digits (1 byte) of the shift register SR. Note that when loading the addition result, the shift register 81
The contents of 'L have been shifted right by two places. Also, in this step S7, the carry output from the adder 53 is F/
It is held in F54.

When the processing of steps 81 to 87 is completed, the addition processing of the next two-digit data is performed in the same manner. By repeating on μ, the result of addition between the designated data to be operated on is held in the shift register SR in the form of complement representation data format IO base data. The contents of the shift register SEL are sent to the CPU 7 (or main memory 20) via the output bus 43.
will be forwarded to.

A specific example of processing on μ is where the summand is "08" and the addend is 7'lS
r02J) 4'S combination (7) addition I'1. (08+02
=10), the fi addend is r-08J', and the addition (-08+0z-06) when the addend is "02" is shown below.

(The summand is "08", that is, A=08., the addend is "08".
2'', that is, B=02s, in the case of I, steps SI to S7
Each conclusion is as follows.

87...0000 1000S2...
・・・ 0000 0010S3・・・・・・0 '0O
QO1010S4...0 0000.1010
S5......ooooi too.

S6...ooooooit.

S7...0 0001 0000 step S
7, l1otaJ, n-chi "10" is set.

■ The summand is l'-08'', that is, A=92. , , the addend is "02", that is, B=Q 21. If , step 5
The results for r-87 are as follows.

SI・・・・・・ 1001 0010S2・・・・
... oooo oot.

S3...0 1001 0100S4...
・・・・Otool 0000S5・・・・・・・o
ooooooooo.

Be------000000000S7...
...0 1001 0100 r94 by step S7
+eJ, hit "-6".

In addition, in the above embodiment, the addition operation was explained, but
It can also be applied to subtraction operations. In this case, it is necessary to perform preprocessing to reduce either the minuend or the subtrahend from [9"+6.j, and to set up a carry in advance. Also,
The present invention can also be applied to multiplication, division, comparison, complement conversion, etc., and can be applied to all decimal arithmetic processing devices.

〔Effect of the invention〕

As detailed above, according to the present invention, the following effects can be achieved.

■ It is possible to apply io-decimal data in a new data format with complement representation where the most significant digit is a numeric/sign shared data digit.
Numerical representation capability is improved by about an order of magnitude compared to the prior art, and memory area can be used efficiently to store lO-adic data.

■ The calculation processing speed is high because it can process ζ times between two digits.

■ Since opposite-sign calculations are less direct, the complement conversion (sign conversion) processing before and after the performance, which was previously necessary, is no longer necessary, further increasing the calculation processing speed and eliminating the need for complement conversion functions. I can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the data format of conventional decimal data, FIG. 2 is a diagram showing the overall configuration of an office arithmetic processing device according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing the data format of applied decimal data, FIG. 4 is a diagram showing the internal configuration of the arithmetic processing logic shown in FIG. 2, and FIG. 5 is a flowchart for explaining the operation. IO...CPU...? (7...main memory, 30...
- Business operation unit) (BPHU), 32... Arithmetic processing logic, 53... Adder, 54... Flip-flop (F/F), RzN'FLs... Register. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 6 Figure 3 IKS Figure 4

Claims (1)

[Claims] One digit consists of 4 bits, and the most significant digit is the hexadecimal value "
0" to "8" indicate positive sign numerical data with decimal values "0" to "8," and hexadecimal value "91 is used as a numerical/sign shared data digit to indicate negative sign numerical data in complement representation.
The main memory stores various types of decimal data in the complement representation data format in which the remaining digits are used as numerical data digits, and the main memory stores the decimal data stored in this main memo. It is equipped with an arithmetic means for reading out the second decimal data and performing an arithmetic operation between these data in units of two digits starting from the F digit. , the carry output in the preceding two-digit unit operation is added to h and i, and 2
A means for calculating digit data j, and )+j to obtain two-digit addition data.