JPS601809B2 - Demand power monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power demand monitoring device, and particularly to an improvement in its alarm device section.

In power trading, large consumers of 50 W or more make power demand contracts with electric power companies and use maximum power demand meters for trading to measure the monthly maximum power demand and provide it for trading.

At consumers, in order to prevent excessive power consumption with high penalties, various power demand monitoring devices are used to constantly monitor the power consumption so that it does not exceed the contracted value with the electric power company. 2. Description of the Related Art Conventional power demand monitoring devices have been designed to alert a monitor by selectively setting off one of several types of alarms corresponding to each alarm condition. For example, a power demand monitoring device having a multi-stage alarm device that generates a plurality of external contact outputs so as to sound a buzzer in the first stage alarm and ring a bell in the second stage alarm, etc. It is. However, with this kind of equipment, it is necessary to install as many alarms as there are alarm levels, so
In particular, devices that issue alarms with a large number of stages are expensive, and securing space for installing the alarms has been a problem.
The present invention has been made in view of the above points, and solves the problems in the conventional devices described above by adopting a method in which the alarm pattern of a single alarm device is made different depending on the number of alarm stages. be. The present invention will be explained in detail below based on the drawings. FIG. 1 is a circuit diagram showing an alarm unit of a power demand monitoring device as an embodiment of the present invention. In FIG. 1, 11, 12, ..., ln are the first flip-flop circuit 21, the second flip-flop circuit 22,
..., n number of n-th flip-flop circuits 2n (n≧2
) of the respective clock input terminals of the flip-flop circuits (
These are alarm signal input terminals connected to the C terminal), and are configured so that alarm signals consisting of voltage pulses corresponding to different predetermined conditions are input from the monitoring unit (not shown) of the power demand monitoring device. ing. The n flip-flop circuits in this example are D-type flip-flop circuits,
Each of those data input terminals (D terminal) is connected to the logic circuit power supply (
(not shown), each set terminal (S terminal) is grounded, and each reset terminal (P terminal) is connected to the positive terminal of the logic circuit power supply via a reset switch 3 and grounded via a resistor 4. has been done. Said first, second,...
..., n-th respective flip-flop circuits 21, 22,...
. . , 2n, n AND circuits 51, 52 respectively corresponding to
,...,5n are provided. The first AND circuit 61 is of an (n+1) input type (a type that takes n11 inputs), and has the first flip-flop connected to its first input terminal. The Q output of the flip-flop circuit 21 is inputted, and the Q outputs of the second flip-flop circuit 22 to the n-th flip-flop circuit 2n are respectively inputted to the second to nth input terminals in this order. and the (n+1)th input terminal AI receives a first alarm corresponding to the first alarm issuing pattern that notifies that the demand power has reached a value that matches the first alarm condition in this power demand monitoring device. Alarm pattern signal is input. The second AND circuit 52 is of n-input type (n
The Q output of the second flip-flop circuit 22 is input to the first input terminal, and the Q output of the second flip-flop circuit 22 is input to the second to (n-1) input terminals, respectively. The respective Q outputs of the flip-flop circuits are input in this order, and a second alarm pattern signal corresponding to the second alarm issuing pattern is input to the n-th input terminal A2. In the same machine, the n AND circuits 51, 52
, . . . , 5n, the Q output of the flip-flop circuit to which the AND circuit corresponds is generally input to the first input terminal, and the final input terminals AI, A2, .
...One alarm pattern signal corresponding to the order of the AND circuit is inputted to each An, and the next order of the flip-flop circuit corresponding to the AND circuit is input to the input terminals other than the first and final input terminals. The Q outputs of each of the flip-flop circuits below the flip-flop circuit are respectively inputted. Therefore, the first AND circuit is (n+1) input type, the second AND circuit is n input type, and the third AND circuit is (n+1) input type.
n-1) Input type, . . . The n-th AND circuit is of a two-input type. In the above description, explanations have been given that apply to the case of nZ3 as in the example shown in FIG. It is configured with a two-input AND circuit similar to the n-th AND circuit 5n in FIG. 1, in which the Q output of the flip-flop circuit is input and the second alarm pattern is input to the second input terminal. Of course it will. The outputs of the first, second, . . . , n-th AND circuits are all input to an OR circuit 6. On the output side of the OR circuit 6, an input resistor 3 and an NPN transistor 9 are connected to drive a buzzer 7 as an alarm.
An alarm drive circuit consisting of the following is added. The operations of the first, second, . . . , n-th D-type flip-flop circuits are shown in the truth table (Table 1) below. Examples of the first, second and n-th alarm pattern signals inputted to the alarm pattern signal input terminals AI, A2 and An of the AND circuits 51, 52 and 5n are shown in FIG.
This is shown by a signal waveform diagram of a2 and an. In FIG. 2, the horizontal axis represents time and the vertical axis represents voltage. [Table 1]
However, Q and Q as output values indicate that the values immediately before them are held.

× indicates that any value may be used.

The apparatus of the present invention constructed as described above operates as follows.

That is, at the start of the timed operation, an alarm signal is sent from the monitoring section of the device to each of the first, second, ..., n-th alarm signal input terminals 11, 12, ..., ln. Since no input is made to any of the flip-flop circuits 21, 22, . . . once the reset switch 8 is closed for a short time,
..., 2M are all in a reset state, and their Q outputs are all at the "L" level. Therefore, each AND circuit 51
, 52, . . . , 5n are all at the "L" level, so the output of the OR circuit 6 is also at the "L" level, and the buzzer 7 does not generate an alarm. As the timed operation progresses, when the power demand value reaches the first stage alarm condition, a positive voltage alarm signal is input from the monitoring section to the first alarm signal input terminal 11. Therefore, the Q output of the first flip-flop circuit 21 changes to the "H" level, but each of the other flip-flop circuits below the second one maintains the previous state, so their respective Q outputs become "H". ' level. Therefore, the first AND circuit 51 becomes conductive, and the first alarm pattern signal consisting of a square wave as shown in FIG. 2 al input from the first alarm pattern signal input terminal AI is output. Appears in the output.
Therefore, by this first alarm pattern signal, the OR circuit 6
The transistor 9 is driven through the alarm signal, and the buzzer 7 emits an alarm sound in an alarm pattern based on the first alarm pattern signal. When further time passes and the power demand value matches the second-stage alarm condition, a positive voltage alarm signal is input from the monitoring section to the second alarm signal input terminal 12. Therefore, the Q output of the second flip-flop circuit 22 changes to "H" level (that is, the Q output changes to "L"). For this reason, the gate of the first AND circuit 51 is closed and the gate of the second AND circuit 52 is conductive, so that the alarm pattern signal input from the input terminal A2 of the second AND circuit 52 is A second alarm pattern signal consisting of a square wave as shown in FIG. 2 appears at the output.
Therefore, by this second alarm pattern signal, the OR circuit 6
The transistor 9 is driven through the alarm signal, and the buzzer 7 emits an alarm sound in an alarm pattern based on the second alarm pattern signal. By repeating the above process until the demand power value matches the alarm condition of the n-th stage, the alarm pattern signal is input from the alarm pattern signal input terminal An of the n-th OR circuit 5n in exactly the same manner as described above. The buzzer 7 emits an alarm sound according to an alarm pattern based on the n-th alarm pattern signal as shown in FIG. 2 an. Furthermore, when multiple alarm signals are input from the monitoring unit at the same time, the alarm signal input to the second alarm signal input terminal is given priority over the alarm signal input to the first alarm signal input terminal, and The alarm signal input to the third alarm terminal is given priority over the alarm signal input to the second alarm signal input terminal, and so on.
Priority is given to the operation of the band circuit based on the alarm signal input to the alarm signal input terminal of the later order. Therefore, an alarm is issued based on the alarm signal that is input to the terminal in the last order among the plurality of alarm input terminals to which alarm signals are input at the same time. This means that the Q output (at the "L" level at that point) of the flip-flop circuit to which the highest priority alarm signal is input via the alarm input terminal as described above is
This is because the signal is configured to be inputted as a "prohibition" signal to all AND circuits provided corresponding to flip-flop circuits that are placed ahead of the flip-flop circuit. Further, when the time limit of the device (for example, 30 minutes) is reached, the reset switch 3 is closed automatically or manually, and the first, second, . . .・, nth flip-flop circuit 21, 22
, . . . , 2n are all reset and the device returns to its initial state. Furthermore, even if the device is in a timed operation, it is of course possible for the supervisor to stop the alarm by closing the reset switch 3 when an alarm is issued. Since the device of the present invention operates as described above, the supervisor can easily distinguish the type of alarm without error by the buzzer sound that is emitted in a pattern corresponding to the alarm stage, and moreover, it is extremely simple as described above. Since different types of alarms can be issued using a single alarm device, the alarm system is inexpensive and can be made sufficiently compact.

Further, since the alarms input to the alarm signal input terminals of the later order are given priority, it is possible to appropriately order the issuing pattern according to the urgency of the alarms. In the above description, an example has been described in which a buzzer is used as an alarm, but a bell, an indicator light, or the like may be used instead of the buzzer.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the alarm unit of the power demand monitoring device of the present invention, and FIG. 2 a1, a2 and an are waveform diagrams of alarm pattern signals input to the circuit of FIG. 1. 21, 22, 2n are flip-flop circuits, 51, 52
, 5n are AND circuits, and 6 is an OR circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. One alarm signal corresponding to the order of the first to nth (n≧2) alarm signals corresponding to predetermined conditions is input to the clock input terminal, and the data input terminal are n first to nth flip-flop circuits connected to a logic circuit power supply, and n first to nth AND circuits provided corresponding to each of the first to nth flip-flop circuits. Each AND circuit has the Q output of the flip-flop circuit corresponding to each rank as its first input, and the Q output of each flip-flop circuit of the rank below the corresponding flip-flop circuit as its first input and the final input. For each input except the input, one of the first to nth alarm pattern signals corresponding to each of the n types of alarm patterns from the first to nth alarm pattern signals corresponding to its rank is added to each final signal. and an OR circuit that receives each output of the first to n-th AND circuits as input, and the output of the OR circuit causes the alarm to emit in a predetermined alarm pattern depending on the type of alarm. A power demand monitoring device designed to notify you. 2. The power demand monitoring device according to claim 1, wherein the first to nth flip-flop circuits are D-type flip-flop circuits.