JPS60180478A - Inverter device - Google Patents

Abstract

PURPOSE:To stably operate always via an arbitrary power factor irrespective of a variation in a load by employing a selfextinguishing type switching element and always monitoring the power factor of the load and feeding back. CONSTITUTION:When a power factor decreases in the state that an inverter is operated in a leading power factor, the average voltage value of a phase difference signal output from an OR element 41 at the leading power factor time increases. Since an integrator 23 is negatively fed back, the output voltage signal of the integrator 23 decreases, the frequency of a pulse train output from a voltage control oscillator 24 and the switching frequency of the inverter also decrease to increases the switching period, thereby suppressing the variation in the power factor. A phase difference signal from an inverting amplifier 43 is output as a negative voltage in the state operated at the delay power factor, but the power factor is controlled constantly by comparing with the voltage signal of a power factor setter 44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inverter device for an induction heating device that is operated with a constant power factor.

[Prior art]

A conventional high frequency inverter device of this type is shown in FIG. In the figure, 1 is a DC power supply, 2 is a DC reactor for current smoothing, 3 to 6 are thyristor elements for switching, 7 is a matching capacitor for a heating coil,
8 is a heating coil for heating the material to be heated; 9 to 12 are saturable reactors for suppressing rush current of the thyristor element; 1
3 is a transformer for detecting the reverse voltage time of Cyrisk, 14 is a transformer for detecting the output voltage of the inverter device, 15 to 1
7 is a voltage level comparison circuit (hereinafter referred to as a converter)
, 18 is a frequency-voltage converter (hereinafter referred to as F-Y converter), 19 is a variable resistor, and 20.21 is a logical AND (
22 is a logical OR element, 23 is an integrator, 24 is a voltage controlled oscillator that generates a pulse train signal with a frequency proportional to the input chamber pressure, 25 is a Norms signal to the input T terminal 26 is a circuit for igniting the thyristor element 4.50, and 27 is the thyristor element 3.6.
This is a 0-ignition circuit.

The conventional high-frequency inverter device is constructed as described above, and under normal operating conditions, the operation chart of each part in FIG. 1 is as shown in FIG. 2. The operation of the conventional inverter device will be explained using FIG. The output voltage of the inverter device shown in FIG. 1, that is, the voltage across the parallel circuit formed by the matching capacitor 7 and the heating coil 8, becomes a sine wave as shown in FIG. 2(a).

The thyristors 3 and 6 and the thyristors 4 and 5 shown in FIG. 1 perform switching operations in pairs. Assume that the thyristors 4 and 5 are made conductive at time t in FIG. 2 while the thyristors 3 and 6 are currently conductive.

At this time, the thyristors 3 and 6 are all in a conducting state, and the voltage shown in FIG. 2(a), which is the voltage of the matching capacitor 7, is applied as a reverse voltage to the thyristors 3 and 6, respectively, Meng extinguishes. The period during which all thyristors 3 to 6 are conducting is called a commutation period, and during the commutation period, the primary side (13a) of the transformer 13 is short-circuited, resulting in zero voltage, as shown in FIG. 2(b). Thus, the detected voltage waveform of the transformer 13 is zero during the commutation period Tu. In addition, Fig. 2 (b
The period 'll'opp shown in ) is a period in which a reverse voltage is applied to the thyristor, and it is a well-known fact that the inverter device will fail in commutation unless this reverse voltage period Topp is maintained for a certain period of time or more. Next, Cyrisk 4.
At time t in FIG. 2 while thyristor 5 is conducting, thyristor 3
, 6 are made conductive, a phenomenon similar to that described above occurs. Therefore, the voltage detected by the transformer 13 is as shown in FIG. 2(b).
As shown in the figure, the voltage becomes a waveform of zero during the commutation period Tu. The voltage waveform detected by the transformer 13 is converted into a logic level signal of only positive voltage by the comparator 15 (FIG. 2(d)), and is converted into a logic level signal of only negative voltage (FIG. 2(e)) by the rake 16. )) respectively. Output signal of the comparator 15 (second
Figure (d)) shows the signal of the flip-flop 250 output Q (Figure 2 (h)) which is the firing signal of the thyristor 4°5.
A logical product is taken by the ND element 20, and the output signal of the comparator 16 (FIG. 2(e)) is sent to the thyristor 3.6.
The signal of the output Q of the flip-flop 25 (FIG. 2(i)), which is a 0 firing signal, is ANDed by the AND element 21. The signals of the AND elements 20 and 21 are converted to the OR element 2.
2, the waveform shown in FIG. 2(f) is obtained. The output signal of the OR element 22 is a signal derived only from the reverse voltage period TOFF. On the other hand, the output voltage of the inno-electronic device is detected by the transformer 14 (Fig. 2(a)
)), the signal is converted to a logic level by the comparator 17 as shown in FIG. 2(C).

Further, it is converted by a frequency-voltage converter 18 into a voltage signal proportional to the output frequency of the inverter device, and the voltage is stepped down by a variable resistor 19. The output signal of the zero-temperature element 22 and the signal of the variable resistor 19 are input to an integrator 23 as the difference between the two signals, as shown in FIG. A pulse train having a frequency proportional to the output voltage of the integrator is generated by the voltage controlled oscillator 24 (FIG. 2(g)), and the pulse signal .

is input to the input terminal T of the flip-flop 25, and the logic level is inverted as shown in FIGS. 2(h) and (i).

The signals of the outputs Q and Q are amplified by the thyristor firing gate circuits 26 and 27 to alternately switch the thyristors. Here, the reverse voltage period TOFF of the thyristor is kept constant by the operation described below. Since the signal from the variable resistor 19 has a magnitude proportional to the output frequency f of the inverter, the voltage of the signal is expressed as −f (k is steering) 1, while the output signal from the OR element 22 is As shown in FIG. 2(f), within the half period of the inverter's output voltage waveform, only the reverse voltage period TOFF has a positive voltage value, so the average voltage of the above output signal is ToFF/T
(t is a constant). Here, according to the relational expression of T-E,
The average voltage of the output signal of the OR element 22 is 2·L −T
It is expressed as opp-f. Here, the output frequency f of the inverter is determined by the voltage controlled oscillator 24, that is, the output voltage signal of the integrator 23 determines the output frequency f of the inverter. If the difference between the input signals of the integrator 23 is not zero, the integrator 23 integrates the input signal and increases or decreases the output voltage, thereby changing the output frequency f of the inverter. The difference between -f and the OR element 22 is zero, that is, the voltage of the signal of the variable resistor 19 is
The output frequency f of the inverter is determined so that the average voltage of the output signal 2·t·1°OFF −f becomes equal. That is, −f and 2・t − are applied to the two signal voltages marked #.
The values of TOFF-f are controlled to be equal. Here, since t is a constant, the output frequency f is controlled so that the reverse voltage time TOFF of the thyristor is constant. Furthermore, if it is desired to set the reverse voltage period TOFF to a desired value, i'arp can be changed by adjusting the variable resistor 19 to change the value of the constant. With such a control method, a certain period of time is always ensured for the reverse voltage time at which the risk of inverting occurs, and the inverter device can be operated without commutation failure.

Since the conventional inverter device is configured as described above, it must be operated with a leading power factor, resulting in an increase in the required apparent power, a large capacity capacitor, and an increase in the number of voltage detection transformers. However, when the resonant frequency fluctuates in a short period of time, the reverse voltage time of the thyristor element cannot be ensured, leading to commutation failure.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional inverter device as described above, and an object of the present invention is to provide an inverter device that uses a self-extinguishing type switching element and can be operated at an arbitrary power factor. It is said that

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In the figure, 1, 2, 7, 8, 14, and 23 to 25 indicate the same components as those with the same reference numerals in FIG. 3b to 6b are switching transistor elements constituting an inverse conversion section, 45 is a current transformer, and 46 is a converter (for example, composed of only a resistor) that converts the current signal of the current transformer 45 into a voltage signal. .

31 and 32 are comparators, 33 and 34 are logical inverting elements, 35 to 40 are logical AND elements, 41 and 42 are logical OR elements, 43 is an inverting amplifier with a gain of 11 times, 44 is a variable resistor, etc. Power factor setter by 26aldmJ
Element 4b of the above transistor.

5b is a base drive circuit for conducting, 27a is a base drive circuit for conducting the transistor elements 3b and 6'b, 47.48 is a monostable multivibrator,
49.50 is a logical inversion element.

The embodiment of the present invention has the above configuration, and then t
The operation of the present invention will be explained using the operation diagram during operation of the inverter device shown in Fig. 444. First, the inverter device of the present invention can be regarded as a current source inverter, and its output voltage waveform is a sine wave shown in Figure 41) and Figure 4).
The result is a trapezoidal wave as shown in . The above waveforms are similar to the conventional device shown in FIG. 2, where the phase difference between the output voltage and current determines the operating power factor of the inverter device, and FIG. 4 shows the case of a leading power factor. Each output voltage waveform is detected by the transformer 14 and then shaped by the comparator 31, as shown in FIG.
As shown in C), a rectangular wave at the logic circuit level is output (second voltage level comparison circuit). On the other hand, the output current waveform is detected by the current transformer 45, converted to a voltage level by the converter 46, and the comparator 32 outputs a rectangular wave at the logic circuit level as shown in FIG. voltage level comparison circuit). The portion of the detection circuit IA surrounded by the dotted line in FIG. 3 is a circuit that detects the phase difference between the output voltage and the output current. Next, the inversion element 34°33
By inverting the output signals of comparators 31 and 32, respectively, the waveforms in FIGS. 4(C) and 4(d) are converted to 18
A waveform shifted by 0° is obtained. When the output signal of the inverting element 33 and the output signal of the comparator 31 are logically multiplied by the AND element 35, a pulse train having a time width corresponding to the phase difference between the output voltage and the output current is generated, as shown in FIG. It appears only during the period when the output voltage is positive. On the other hand, when the output signal of the inverting element 34 and the output signal of the comparator 32 are logically multiplied by the AND element 36, the result is shown in FIG. 4(f).
As shown in , the output voltage appears only during the positive period of the above pulse train. Here, transistor elements 3 to 1
The point in time when 6 switches, that is, the point in time when the conductive element switches is the point in time when the output current is about to flow in the opposite direction, so it is Sl, Sl + J + S4 shown in FIG. Even if the conductive element is switched at this point, it takes time for the output current to completely reverse, so the waveform is
As shown in Figure (b), it is a trapezoidal wave. The base signals for the transistor elements 3 to 6 are shown in FIG. 2(k),
As shown in (4), since this is a signal that switches at time points S and -S, the output Q signal of the 7-lip flop 25 (see FIG.
))) Yo or Q signal (Fig. 4 (4) is Fig. 4 (e)
, tl) (The waveform is slightly advanced from the D pulse train. Here, in order to judge the leading power factor and the lagging power factor, a monostable multivibrator 47, 48 is installed and the time width of the generated pulse is changed by the inverter. is selected to be half of the output period of , that is, approximately half of the time width of the Q and Q signals.

When the Q signal is passed through the monostable multivibrator 47, the waveform becomes as shown in FIG. 4), and when the Q signal is passed through the monostable multivibrator 48, the waveform becomes as shown in FIG. 4(n). Here, the case of leading power factor operation in the apparatus of the present invention, that is, the case of the operation chart as shown in FIG. 4 will be described. First, the output signal of the AND element 35 (FIG. 4(e)
) and the output signal of the monostable multivibrator 47 (Fig. 4-) are logically multiplied by the AND element 37, and the output signal of the AND element 36 (Fig. 4 (f)) and the output of the monostable multivibrator 48 are obtained. The signal (FIG. 4(h)) is logically multiplied by an AND element 38. As a result, as shown in FIG. 4(g), the output signal of the AND element 35 (FIG. 4(e)) appears as it is at the output of the AND element 37, and the AND element 38
As shown in FIG. 4(h), the output signal of the AND element 36 (FIG. 4(f)) appears as it is at the output.

Thereafter, the respective output signals are logically summed by the OR element 41 to generate a pulse train having a time width corresponding to the phase difference between the output voltage and the output current of the inverter device, as shown in FIG. 4(i). Here, when the same heating coil is used, the output cycle of the inverter device changes by only about 30% depending on the condition of the heated material, so the time width in which the monostable multi-vibration break occurs is constant. You can also set it to a value. On the other hand, the output signals of the monostable multivibrators 47 and 48 are respectively inverted by inverting elements 49 and 50 (Fig. 4 (1') and (q)), and the above AND
Even if the AND terminals 39 and 40 are logically multiplied with the elements 35 and 36, the output of the AND terminals 39 and 40 becomes zero, so the detection signal of the phase difference detection circuit 1a surrounded by the inner dotted line in FIG. 3 at the lagging power factor is zero.

However, as shown in FIG. 5, when the inverter is operated with a lagging power factor, the output signal of the OR element 41 becomes zero, contrary to the case of the leading power factor described above, and the output signal of the OR element 41 becomes zero.
The second output signal is a pulse train having a time width corresponding to the phase difference between the output voltage and the output current of the inverter device. That is, the phase difference detection circuit 1a surrounded by the inner dotted line in FIG.
is a circuit for detecting the degree of leading power factor, and the phase difference detection circuit 1b, which is similarly surrounded by a dotted line, is a circuit for detecting the degree of lagging power factor. Here, the lagging power factor detection signal, that is, O
If the output signal of the R element 42 is inverted by the inverting amplifier 43 having a gain of -1 and converted into a negative voltage signal, the output signal of the OR element 41 becomes a positive voltage as the power factor of the inverter increases. As the pulse width increases 9 and the power factor lags, the output signal of the inverting amplifier 43 becomes a negative voltage and the pulse width increases.

When the power factor is 1, that is, when the phase difference between the output voltage waveform and the output current waveform of the inverter device is zero, the output signals of the two output signals are naturally zero. The phase difference signal detected in this way is input to the integrator 23 by adding it to the voltage signal of the power factor setting device 44 constituted by a variable resistor. The integration time constant of the integrator 23 is set much larger than the switching period of the inverter device in consideration of the stability of the control system, and the integration time constant is set much larger than the period of the pulse train of the phase difference signal. much larger,
The pulse train input to the integrator may be expressed by its average voltage value. Therefore, the output voltage signal of the integrator 23, that is, the input voltage signal of the voltage controlled oscillator 24, has a substantially constant value in a short period of time, and a pulse train signal having a frequency proportional to the voltage signal appears at the output of the voltage controlled oscillator. (Fig. 4 (j)), the logic levels of the outputs Q and Q of the 7 lip-flop 25 are inverted every time one pulse of the above signal is input (Fig. 4 (k), (4). is amplified by base drive circuits 26a and 27a,
A base current is passed through the transistor elements 3b to 6b, and the transistor elements 3b, 6b and 4b, 5b are made into pairs and alternately conductive to supply alternating current power to the matching capacitor 7 and heating coil 8, which are loads.

Here, the operating power factor of the inverter device described above is kept constant at a desired value by the operation described below.

Suppose that the inverter is operated with a leading power factor as shown in Figure 4, and for some reason the phase difference between the output voltage and the output current becomes large, that is, the power factor decreases. , the average voltage value of the phase difference signal output from the OR element 41 at the time of a leading power factor increases. At this time, since negative feedback is applied to the integrator 23, the output voltage signal of the integrator 23 decreases, and the frequency of the pulse train outputted from the voltage controlled oscillator 24 and the switching frequency of the inverter device also decrease. This increases the switching period. The above switching period is S shown in Fig. 4.
, ~S4, and as this interval increases, the output current waveform shown in FIG. 4) becomes temporally different from the output current waveform shown in FIG. This will cause the phase difference between the two to decrease. On the other hand, if the phase difference between the output voltage and the output current were to decrease due to some reason in the above-mentioned operating condition, an operation opposite to the above phenomenon would occur, and the third output voltage would eventually increase the phase difference between the two.
The circuit shown in the figure works. That is, the integrator 2 is
When the input voltage of 3 becomes zero, that is, the OR element 41
When the phase difference signal that is output more frequently matches the absolute value of the voltage signal of the power factor setting device 44, the output voltage of the integrator 23 becomes constant, and the switching frequency of the inverter device also becomes constant. If the time width of the pulse of the phase difference signal is δ (seconds) and the switching period is T (seconds), then the average voltage value of the phase difference signal is proportional to δ/T. Therefore, the fact that δ/T is a constant value means that the time width of the phase difference with respect to the switching period is constant regardless of the switching period, that is, the switching frequency of the inverter device, and this means that the power factor is constant. No.

As described above, when the inverter device of the present invention is operated with a lagging power factor as shown in FIG. 5, the phase difference signal from the inverting amplifier 43 is outputted as a negative voltage value. By comparing it with the voltage signal from the power factor setter 44, the power factor is controlled to be constant as in the case of the leading power factor described above. In addition, by adjusting the power factor setter 44, when the voltage signal is a negative value, the power factor is set to a leading power factor, and when the voltage signal is a positive value, the power factor is set to a lagging power factor. In the case of zero, the power factor is limited to 1, and the power factor value can be set freely in this way.

Note that when the inverter device of the present invention is operated only with a leading power factor or a lagging power factor, the phase difference detection circuit at the leading power factor shown in FIG. 3 (FIG. 3 (la)) or the lagging power factor There is no need to say that any of the time phase difference detection circuits (Fig. 3 (lb)'') are unnecessary.

In the above embodiment, the output voltage and output current of the inverter device are detected as a means for monitoring the operating power factor of the inverter device, but by detecting only the output voltage and processing it in the control circuit, the same You can expect good results.

FIG. 6 shows another embodiment of the invention. In the figure, 1 to 8,
Reference numerals 14, 19, 20, 25, and 31 indicate the same components as those with the same reference numerals in FIG. In FIG. 6, 18a is a frequency-voltage converter (hereinafter referred to as an F-V converter);
2 is a capacitor, 53 is a resistor for charging the capacitor, 54 is a semiconductor switch element for discharging the charge of the capacitor, 55 is a comparator, 44a is a power factor setter composed of a variable resistor, 57 is a logic inversion element, 58.59 is A
ND element, 60 is an OR element, and 61 is a changeover switch.

FIG. 7 shows an operation chart of the embodiment of FIG. 6, and the operation of the embodiment of FIG. 6 will be explained using this diagram.

Since the main circuit configuration of the inverter device according to the other embodiment is the same as that of the embodiment shown in FIG.
The output current waveforms shown in FIG. 7(a) and FIG. 7(b) are similar to those of FIG. 4 or 5(a) and (b), respectively. Similar to the embodiment of FIG. 3, the transformer 14. The comparator 31 shapes the output voltage into a logic circuit level waveform as shown in FIG. 7(C). The frequency of the square wave train of the above waveform is the same as the output frequency of the inverter device.

Therefore, the above waveform is converted by the F-V converter 18a into a voltage proportional to the output frequency of the inverter device (FIG. 7(d)). The circuit IC indicated by the dotted line in FIG. 6 is a voltage controlled oscillator. The above voltage charges the condenser 52 through the resistor 53, and the capacitor 5
2' voltage (the potential at point B in Figure 6 is the power factor setter 44a).
At the moment when the voltage signal level of the comparator 55 exceeds the voltage signal level, the logical level of the blade signal of the comparator 55 changes from 'L' (Low Level) to H' (High Level), and the flip 7
Output Q of 0 tube 25, inverts the logic level of 6, and outputs the third
Similar to the embodiment shown in the figure, the switching operation of the transistor elements is performed through base drive circuits 19 and 20. Now, when the changeover switch 61 is in the state shown in FIG.
)), the output Q signal of the flip-flop 25, and
The output signal of the comparator 31 is passed through the inverting element 57, and the inverted signal is logically multiplied by the AND element 5a (FIG. 7(J)).
) and the output signals of the above two AND elements are logically summed using an OR element (No. i is shown in FIG. 7(k)). 84
) to the period 'H1 until the cutting voltage becomes zero next time. If this signal causes the capacitor 52 to be discharged with a short time constant through the switch element 54, the sixth
As shown in FIG. 7(e), the potential at 543 points in the figure starts charging from the time when the output voltage is zero, and the power factor setter 4
When the voltage signal level 4a is reached, the battery immediately discharges and the potential becomes zero, and then charging starts from the time the output voltage reaches zero, resulting in a periodic triangular wave train. Further, the cutting signal of the comparator 55 becomes a pulse train shown in FIG. 7(f).

Here, the Z' voltage VF generated by the F-V converter 18a, the resistance value of the resistor 53 as R(b), the capacitance of the capacitor 52 as C(Pl), and the time constant CR as the output voltage. If the waveform is selected to be larger than the half period of the waveform, the above triangular wave can be regarded as a nearly linear waveform, and the potential VB at point 54a in Fig. 6 is expressed by the following formula after t (seconds) after the start of charging. Approximately expressed as

Note that since VF is a value proportional to the frequency f of the inverter device, the above equation, however, is VF=β·f (β is a constant). The above VB reaches the voltage signal VR of the power factor setter 44a (VB-VR
) (TB in FIG. 7) is expressed by the above equation and the following equation.

As is clear from FIG. 7, the time Tδ for the half cycle of the output voltage waveform of the inverter device until the T voltage becomes zero is expressed by the following equation.

If the above formula is transformed, it becomes the following formula.

The above equation shows that the ratio of Tδ to T, that is, the ratio at which the output current waveform (in Figure 7) advances with respect to the half cycle of the output voltage, that is, the power factor is It shows that it is always constant regardless of the power factor.To set the power factor to the desired value, just adjust the VRO power factor setter j4a.Adjust the power factor setter 4.4a above. If the voltage signal is increased by increasing the voltage signal, as is clear from Fig. 7(e), the switching time will be delayed and the power factor can be adjusted to 1.Even if VR is increased from the point where the power factor is 1, the output voltage will not change. When the voltage reaches zero, a signal is output that makes the switch element 54 conductive, so the capacitor 52 is discharged and the limit is reached at the point where the power factor is 1.Meanwhile, the switch 61 is switched in the opposite direction to that shown in Fig. 6 to change the set voltage of VR. If the switching time point is set to the first half of the half cycle of the output voltage as shown in Fig. 8, this becomes a lagging power factor, which can be freely adjusted within this range. Since detection is not required, the circuit configuration is simple and economical.

In the above embodiment, one comparison voltage of the comparator 55, that is, the power factor setting device 44a is used for setting the power factor, but this can be changed by making the fixed closing resistor 53 variable.
A method of changing the charging time constant at point B in the figure (corresponding to C in equation (1) above), i.e., in Figure 7(e) or 8.
How to change the slope of the triangular wave in figure (e), or Ii”
- A method of changing the gain (I) of the V converter 18a (corresponding to β described above) (this method is also shown in FIG. 7(e) or FIG. 8(
(e) will change the slope of the triangular wave), but the above (1)
) As is clear from the equation, the power factor is kept constant and can be set freely by the variable elements mentioned above.

In addition, all the above-mentioned embodiments are cases where a current-source inverter device is used, but all the above-mentioned embodiments can also be applied when a voltage-source inverter device is used. In other words, a voltage source inverter generally has a waveform that is opposite to that of a current source inverter, and the output voltage waveform is a trapezoidal wave and the output current waveform is a sine wave, but in all of the above embodiments, both waveforms are square waves. Since the data is formatted and input to the control circuit, the operation explanation as described above can be applied as is, and similar effects can be expected. Furthermore, although all of the above embodiments show transistors as the switching elements 3 to 6 of the main circuit, it goes without saying that any element having a self-extinguishing ability such as a GTO thyristor can be applied.

〔Effect of the invention〕

As described above, according to the present invention, since the self-extinguishing switching element is used and the power factor of the load is constantly monitored and fed back, the inverter device can be operated at any power factor regardless of load fluctuations. Very stable operation is now possible, and by operating at a power factor of 1, the apparent power supplied to the inverter device and the capacity of the matching capacitor of the heating coil can be made extremely small. This has the effect of providing an inverter device that can be made smaller and the cost can be significantly reduced.

[Brief explanation of the drawing]

Figure 1 is an electric circuit diagram showing a conventional inverter device, Figure 2 is an electric circuit diagram showing a conventional inverter device.
The figure is an operational diagram of the inverter device shown in FIG. 1 above, FIG. 3 is an electric circuit diagram showing an embodiment of the inverter device of the present invention, and FIG. 4 is a diagram of the inverter device shown in FIG. 3 above during leading power factor operation. FIG. 5 is a diagram of the operation of the inverter shown in FIG. 3 during delayed power factor operation, FIG. 6 is an electric circuit diagram showing another embodiment of the inverter of the present invention, and FIG. 7 is the diagram of the operation of the inverter shown in FIG. FIG. 6 is an operational diagram of the inverter device during leading power factor operation, and FIG. 8 is an operational diagram of the inverter device of FIG. 6 during lagging power factor operation. 1... DC power supply device - 2... DC reactor, 3-6... Cyrisk element, 3b-6b... Transistor element 1 7... Matching capacitor, 8... Heating coil, 9-12 ...Saturable reactor, 13...Transformer 1 14...Transformer, 15-17...Voltage level comparison circuit, 18.18a.
... Frequency-voltage converter, 19... Variable resistor, 20.21... AND element, 22... OR element, 23... Integrator, 24... Voltage controlled oscillator, 25...・Flip-flop, 26.27... Ignition circuit, 26a, 27a... Pace drive circuit, 31.32...
- Comparator, 33.34... Inverting element, 35-40... AND element, 41.42... OR element, 43... Inverting amplifier, 44.44a... Power factor setter, 45. ··Current transformer. 46... Converter, 47.48... Monostable multi-bi break, 49.5
0...Logical inversion element, 52...Capacitor, 53...Charging resistor, 54...Semiconductor switch element, 55...Comparator, 58.59...AND element, 60...・OR element, 61... selector switch. Note that the same reference numerals in the figures indicate the same or equivalent parts. Patent Applicant: Mitsubishi Electric Co., Ltd. Agent, Patent Attorney: Kiminobu Kato, 7pq.J 4 Figure 5 Figure 6 Figure 6 r2 Figure 7 Figure 8 Procedural amendment document (spontaneous) f. 3. Person making the amendment Representative Hitoshi Katayama Dept. 4 Agent Postal code 105 Address Nishi-Shinbashi 1-chome IN 4 M, Minato-ku, Tokyo 10-5
, Number of inventions increased by amendment 1 7. Contents of amendment (1) The scope of claims will be amended as shown in the attached sheet. (21 Specification is amended as follows. 8. Tatami surface stating the scope of claims after amendment of the list of attached documents. Scope of claims after amendment of one or more copies. (1) The material to be heated from the DC power supply There is an inverse conversion section with a bridge configuration using a self-extinguishing switching element that supplies father current power to the load circuit connected to the heating coil that performs induction heating and a matching capacitor, and the voltage waveform in the above inverse conversion section is detected by the transformer. a first voltage level comparator circuit that converts the output voltage waveform into a rectangular wave synchronized with the output voltage waveform, and a current detector detects the output DC waveform of the inverse converter and converts the output voltage waveform into a rectangular wave synchronized with the output voltage waveform. a second voltage level comparison circuit that converts the
a phase difference detection circuit that generates a first pulse train having a time width according to a phase difference VC between a square wave generated by the waveform wr and a rectangular wave generated by the second voltage level comparison circuit; an integrator that adds and integrates the constant voltage generated by the voltage setting device and the first pulse train; and a drive circuit that amplifies the output signal of a flip-flop that inverts the voltage level of the blade signal in synchronization with the second pulse tally and makes the self-extinguishing switching element conductive.1- Inverter device. Patent No. 8, which is characterized in that when the +210,000 factor is slower than when the FC must have a power factor with the sign of the voltage value of the detection signal of the phase difference between the cutting voltage and the output peeking current, the power factor is reversed. The inverter device according to item 1. 131 top current power supply device to a load tower consisting of a relothermal coil and a matching capacitor for inductively heating the material to be heated; A first anti-pressure level comparison circuit which detects the output voltage waveform of the converter and converts it into an FC rectangular wave in synchronization with the voltage waveform, and which is proportional to the frequency of the rectangular wave. The heavy pressure 2 The growing circumference V
If the voltage +1 voltage of the charging circuit that is photoelectrically generated by the output TJ'W voltage of the number-voltage converter exceeds a certain voltage that is generated by the setting device, it will turn off. The voltage level comparator circuit of Sou 2 that generates the response signal. After the above pulse signal is generated, a sequence of pulse signals generated by the above-mentioned light emission circuit and the above-mentioned second Ichikawa level comparison circuit for a period of 1 in which the output voltage reaches its full potential. and a drive circuit that amplifies the output signal of a flip-flop that inverts the voltage level of the blade signal in synchronization with the inverter and makes the self-extinguishing switching element conductive.

Claims (3)

[Claims] (1) An inverse conversion section with a bridge configuration using a self-extinguishing switching element that supplies AC power from a DC power supply device to a load circuit consisting of a heating coil that inductively heats a material to be heated and a matching capacitor; a first voltage level comparison circuit that detects the output voltage waveform of the output voltage waveform using a transformer and converts it into a rectangular wave synchronized with the output voltage waveform; and a current detector that detects the output current waveform of the inverse conversion section. a second voltage level comparison circuit that converts the output current waveform into a rectangular wave synchronized with the output current waveform; a rectangular wave generated by the first voltage level comparison circuit; and a rectangular wave generated by the second voltage level comparison circuit. a phase difference detection circuit that generates a first pulse train having a time width corresponding to the phase difference of; and a voltage generated by an integrator that adds and integrates the constant voltage generated by the voltage setting device and the first pulse train. the second with a frequency proportional to
a voltage-controlled oscillator that generates a pulse train; and a drive circuit that amplifies the output signal of a flip-flop that inverts the voltage level of the output signal in synchronization with the second pulse train to make the self-extinguishing switching element conductive. An inverter device comprising: (2) A patent claim characterized in that when the power factor lags, the sign of the voltage value of the detection signal of the phase difference between the output voltage and the output current is inverted compared to when the power factor leads. The inverter device according to item 1. (3) An inverse conversion section with a bridge configuration using a self-extinguishing switching element that supplies AC power from the DC power supply to a load circuit consisting of a heating coil that inductively heats the material to be heated and a matching capacitor, and the above conversion section. a first voltage level comparator circuit that detects the output voltage waveform of the output voltage using a transformer and converts it into a rectangular wave synchronized with the output pressure waveform; and a frequency-voltage circuit that generates a voltage proportional to the frequency of the rectangular wave. a second voltage level comparison circuit that generates a pulse signal when the charging voltage of the charging circuit charged by the output voltage of the converter exceeds a certain voltage generated by the voltage setting device; a discharging circuit that discharges the charging circuit for a period until the value of the output voltage becomes zero;
and a drive circuit that inverts the voltage level of the output signal in synchronization with the train of pulse signals generated by the voltage level comparator circuit and amplifies the output signal of the flip-flop to make the self-extinguishing switching element conductive. An in-game device according to claim 1, characterized in that: