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JPS60178626A - Formation of resist pattern and resist treater - Google Patents

Formation of resist pattern and resist treater

Info

Publication number
JPS60178626A
JPS60178626A JP3358584A JP3358584A JPS60178626A JP S60178626 A JPS60178626 A JP S60178626A JP 3358584 A JP3358584 A JP 3358584A JP 3358584 A JP3358584 A JP 3358584A JP S60178626 A JPS60178626 A JP S60178626A
Authority
JP
Japan
Prior art keywords
resist
temperature
cooling
substrate
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3358584A
Other languages
Japanese (ja)
Other versions
JPH0746676B2 (en
Inventor
Kei Kirita
桐田 慶
Toshiaki Shinozaki
篠崎 俊昭
Yoshihide Kato
加藤 芳秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59033585A priority Critical patent/JPH0746676B2/en
Publication of JPS60178626A publication Critical patent/JPS60178626A/en
Publication of JPH0746676B2 publication Critical patent/JPH0746676B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/38Treatment before imagewise removal, e.g. prebaking

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a pattern having high accuracy efficiently and rapidly by baking a resist film at a temperature Tb higher than a glass transition temperature Tg before development treatment after exposure, uniformly cooling the resist film to a fixed intermediate cooling temperature Tm once and equally cooling it quickly to a final cooling temperature Tc. CONSTITUTION:A resist is applied on a substrate to be treated. Said resist film is pre-baked, and cooled as it is. The resist film is exposed by electron rays under predetermined conditions, and baking before development and controlled uniform cooling treatment are executed by using a resist treater. A baking temperature Tb is selected within a range of 200 deg.C from a glass transition temperature Tg of 133 deg.C. The temperature of the resist film is lowered equally to an arbitrary intermediate cooling temperature Tm (Tm<=Tb). The temperature is further lowered rapidly and uniformly to a final cooling temperature Tc. A temperature such as 25 deg.C is selected as the final cooling temperature Tc.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は、レジスI・の感度を制御して高精度のレジス
トパターンを形成する方法及びそれを実現するためのレ
ジスト処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming a highly accurate resist pattern by controlling the sensitivity of a resist I, and a resist processing apparatus for realizing the method.

[発明の技術的背景とその問題点] 超LSIをはじめとして、半導体素子の集積密度が高ま
るにつれて、微細にして且つ高精度のパターン形成技術
が要求されている。このため、最先端分野では、ロイン
チロマスク或いは5インチ径ウェハの場合、パターンの
基板面内平均寸法値に対する1法誤差として例えば3σ
<0.1[μm]が要求されている。また、量産ライン
では、パターン形成プロセスの迅速性も必須であり、レ
ジストの感度としては高いものが望まれている。しかし
、従来高感度のレジストは解像性が劣るために所定のパ
ターン寸法精度を得ることが困難であり、逆に高解像性
を有するレジストは低感度であるために量産ラインにお
いてパターン形成の高スループッ1−化が図れない等の
問題があった。
[Technical Background of the Invention and Problems Therewith] As the integration density of semiconductor elements, including VLSIs, increases, finer and more precise pattern forming techniques are required. For this reason, in the cutting-edge field, in the case of a thin chiro mask or a 5-inch diameter wafer, for example, 3σ is one method error for the average dimension value of the pattern in the substrate plane.
<0.1 [μm] is required. Furthermore, in a mass production line, speed of the pattern formation process is essential, and high sensitivity of the resist is desired. However, conventionally high-sensitivity resists have poor resolution, making it difficult to obtain desired pattern dimensional accuracy; conversely, high-resolution resists have low sensitivity, making it difficult to form patterns on mass production lines. There were problems such as the inability to achieve high throughput.

第1図は従来技術によるレジスi〜パターン形成プo 
tスを示すフローヂャートである。まず、被処理基板上
に周知の回転塗布法により所定の膜厚にレジメl−を塗
15する。次に、塗布i8媒の除去並びにレジストと基
板との密着性を向上させるために、オーブン等を用いレ
ジストに応じた所定の温度(Tb >でレジストのベー
ク(プリベーク)を行なう。この後、オーブンから取り
出されたレジスト嗅付被処理基板を大気中で支持台にて
自然放冷することにより、室温まで20〜30分か(ブ
て冷fJI iる。冷五〇を完了したレジスト膜に対し
て、レジストの種類に応じた所定の照射41(ii光邑
)で所定波長域の電磁波、例えば紫外光あるいは所定エ
ネルギーの粒子線、例えば電子線などを選択的に照剣す
る。その後、yAV!A・リンス処理工程を経て所望の
レジストパターンが形成されることになる。
FIG. 1 shows resist i to pattern forming process o according to the prior art.
2 is a flowchart showing ts. First, a regimen 15 is applied to a predetermined thickness on a substrate to be processed by a well-known spin coating method. Next, in order to remove the coating i8 medium and improve the adhesion between the resist and the substrate, the resist is baked (prebaked) using an oven or the like at a predetermined temperature (Tb >) depending on the resist. The resist-scented processed substrate taken out from the substrate is allowed to cool naturally on a support stand in the atmosphere for 20 to 30 minutes to room temperature. Then, electromagnetic waves in a predetermined wavelength range, such as ultraviolet light, or particle beams with a predetermined energy, such as electron beams, are selectively illuminated using a predetermined irradiation 41 (ii) depending on the type of resist.After that, yAV! A. A desired resist pattern is formed through the rinsing process.

ところC1上述した自然放冷中の被処理基板上のレジス
ト膜について、ある時点における膜面全体の温度分布を
赤外線放射温度計によって本発明者等が調べたところ、
第2図に示すような結果が得られた。なお、この場合の
自然冷却に先立つベーク時の温度T 11は〜160 
[℃]であった。第2図において、レジスト膜付被処理
基板21の中央部上方(A点)では温度が高く(冷却の
され方が遅り)、中心領域(B点)を紅で下方(0点)
に進むにつれて温度が低く(冷却のされ方が速く)なっ
ている。なお、図中の各曲線は等混線である。
However, when the present inventors investigated the temperature distribution of the entire film surface at a certain point in time using an infrared radiation thermometer regarding the resist film on the substrate to be processed during natural cooling described above in C1, we found that
The results shown in FIG. 2 were obtained. In this case, the temperature T 11 during baking prior to natural cooling is ~160
It was [°C]. In FIG. 2, the temperature is high (cooling is slow) at the upper center of the substrate 21 to be processed with a resist film (point A), and the center region (point B) is shown in red below (point 0).
As the temperature progresses, the temperature becomes lower (cooling speed becomes faster). Note that each curve in the figure is an equicross line.

第3図は第2図のA、B、C各点における時間に対する
温度変化を示したもので、曲線31.32゜33は夫々
A、B、C点に対応する冷却特性である。A点とB点の
最大温度差は15[’C]程度、A点と0点の最大温度
差は30 [℃]程度であった。これらの温度測定はレ
ジスト膜上の被測定部分に熱電対を接触させて行なった
。このような温度分布く冷却速度むら)が生じる原因と
しては、自然放冷中波処理基板が支持台等の上に立てら
れているために、熱放散による雰囲気の自然対流が基板
面に沿って上向きに起こり易いこと及び基板下方部が支
持台により熱を奪われ易いこと等が考えられる。また、
本発明者等は上記レジスト膜付被処理基板の冷却時の湿
度分布と照射・現像処理後のレジストパターンの寸法精
度との関係について着目し、第2図の)B度測定点A、
B、C領域における形成パターンの寸法を測定したとこ
ろ、本来例えば2[μm1の同一寸法であるべきパター
ンにB点において0.1[μTrL]、0点において0
.2[μγyL]程度の誤差が生じており、レジスト膜
付基板の冷却時の温度分布と形成されるレジストパター
ンの寸法分布とが、レジストの感度分布を通して完全に
対応していることを確認した。
FIG. 3 shows temperature changes over time at points A, B, and C in FIG. 2, and curves 31, 32, and 33 are cooling characteristics corresponding to points A, B, and C, respectively. The maximum temperature difference between point A and point B was about 15 [°C], and the maximum temperature difference between point A and point 0 was about 30 [°C]. These temperature measurements were performed by bringing a thermocouple into contact with the portion to be measured on the resist film. The reason for this (temperature distribution and cooling rate unevenness) is that the natural convection of the atmosphere due to heat dissipation occurs along the substrate surface because the naturally cooled medium-wave processed substrate is placed on a support stand etc. Possible reasons include that it tends to occur upwards and that heat is easily removed from the lower part of the substrate by the support. Also,
The present inventors focused on the relationship between the humidity distribution during cooling of the resist film-coated substrate to be processed and the dimensional accuracy of the resist pattern after irradiation and development processing, and found that
When we measured the dimensions of the pattern formed in areas B and C, we found that the pattern, which should originally have the same dimensions of, for example, 2 [μm1], had a size of 0.1 [μTrL] at point B and 0 at point 0.
.. An error of about 2 [μγyL] occurred, and it was confirmed that the temperature distribution during cooling of the resist film-coated substrate and the size distribution of the formed resist pattern completely corresponded through the sensitivity distribution of the resist.

したがって、パターン寸法むらのない高精度のレジスト
パターンを得るには、レジストベーク後基板面内で温度
分布を生じせしめない様な均一・な冷却が不可欠である
ことが判った。
Therefore, it has been found that in order to obtain a highly accurate resist pattern with uniform pattern dimensions, uniform cooling that does not cause temperature distribution within the substrate surface after resist baking is essential.

一方、発明者等がベーク後のレジスト膜のih fJ]
過程とレジス]・の感度との関係に看目し、種々実験・
研究を重ねた結果、レジストを該レジストのガラス転移
温#T−刀以−上の一所定の−4一度TトでJ9i9時
間レジスト!IIをベークした後、該レジスト膜の温度
をまずTbから任意の中間冷却温度Tmまで下げ、次い
でTmから例えば至温以下の任意の最終冷却温度Tcま
で急速冷却させる(Tb≧TI〉TO)ことによって、
レジストの感度を完全に且つ再現性良く制御できること
を見い出した。さらに、これら冷却過程を制御して形成
したレジストパターンの解像性は何れも、レジスト本来
のパターン解像性に比べて、いささかも劣化していない
ことも判った。加えて、上記Tb→Tm→TCのレジス
ト脱冷却を基板面上全体に亙って均一に行なうことによ
り寸法精度の極めて高いレジストパターンを形成できる
ことも判明した。
On the other hand, the inventors et al.
In view of the relationship between the process and the sensitivity of [regis], various experiments and
As a result of repeated research, the resist was heated to a temperature of -4T above the glass transition temperature of the resist for J9i9 hours! After baking II, the temperature of the resist film is first lowered from Tb to an arbitrary intermediate cooling temperature Tm, and then rapidly cooled from Tm to an arbitrary final cooling temperature Tc, for example, below the lowest temperature (Tb≧TI>TO). By,
It has been found that the sensitivity of the resist can be completely controlled with good reproducibility. Furthermore, it has been found that the resolution of resist patterns formed by controlling these cooling processes is not at all degraded compared to the original pattern resolution of the resist. In addition, it has been found that a resist pattern with extremely high dimensional accuracy can be formed by performing the resist decooling of Tb→Tm→TC uniformly over the entire substrate surface.

また、本発明者等は更に鋭意研究を重ねた結果、露光後
で現像処理の前に制御されたレジストのベーク・冷却プ
ロセスを施すことによっても、上記した場合と同様の高
精度レジストパターンが得られることを見い出した。即
ち、パターン露光後で現像処理の前にガラス転移温度T
o以上の温度Tbでじλ上膜−をベーク、〈以下現像前
ベークと称す)した後、該レジスト膜の温度をまずTb
から任意の中間冷却温度Tmまで下げ、然る後Tl11
から最終冷却湿度TCまで急速冷却させれば(Tll≧
Tm >Tc ) 、レジストの感度を任意の値に再現
性良く制御でき、しかも寸法精度の高い、レジストパタ
ーンを形成できることが判った。
In addition, as a result of further intensive research, the present inventors have found that a high-precision resist pattern similar to that described above can also be obtained by performing a controlled resist baking and cooling process after exposure and before development. I found out that it can be done. That is, after pattern exposure and before development processing, the glass transition temperature T
After baking the resist film (hereinafter referred to as pre-development baking) at a temperature Tb equal to or higher than o, the temperature of the resist film is first lowered to Tb.
to an arbitrary intermediate cooling temperature Tm, and then Tl11
If it is rapidly cooled from to the final cooling humidity TC (Tll≧
Tm > Tc ), it was found that the sensitivity of the resist could be controlled to any value with good reproducibility, and a resist pattern with high dimensional accuracy could be formed.

[発明の目的コ 本発明の目的は、解像性を劣化させることなく、レジス
トの電”磁波若しくは粒子線照射に対する感度を任意に
制御し、高精度のレジス]・パターンを効率良く且つ迅
速に形成し得るレジストパターン形成方法及びそれを実
現するためのレジスト処理装置を提供することにある。
[Objective of the Invention] The object of the present invention is to arbitrarily control the sensitivity of the resist to electromagnetic waves or particle beam irradiation without deteriorating the resolution, and to create a highly accurate resist pattern. An object of the present invention is to provide a resist pattern forming method that can be formed and a resist processing apparatus for realizing the method.

[発明の概要] 本発明の骨子は、露光後で現像処理の前に、レジスト膜
をガラス転移温度Ti1以上の温KTbでベークした後
、一旦所定の中間冷却温度Tmまで均一に冷却し、さら
に前記中間冷却温度Tl11から最終冷却)温度TCま
で急速に均一冷却することにある。
[Summary of the Invention] The gist of the present invention is that after exposure and before development, the resist film is baked at a temperature KTb higher than the glass transition temperature Ti1, and then uniformly cooled to a predetermined intermediate cooling temperature Tm, and then The objective is to rapidly and uniformly cool the intermediate cooling temperature Tl11 to the final cooling temperature TC.

即ち本発明は、被処理基板上のレジスト膜を塗布形成し
、プリベークした後、所定波長のmR1波或いは所定エ
ネルギーの粒子線を上記レジスト膜に選択的に照射して
該レジスト膜を露光し、現像処理を施すことによりレジ
ストパターンを形成する方法において、前記露光後で前
記現像処理の前に前記レジスト本来を該レジストのガラ
ス転移温度Tg以上の所定温度1−bにてベーク(以下
現像前べ−りと称す)し、次いで前記レジスト膜を前記
温度Tbから任意の中間温度TIまで均一に冷却し、し
かるのち前記中間温度TIから最終冷却温度Toまで急
速且つ均一に冷却するようにした方法である。
That is, the present invention applies and forms a resist film on a substrate to be processed, prebakes it, and then selectively irradiates the resist film with an mR1 wave of a predetermined wavelength or a particle beam of a predetermined energy to expose the resist film, In a method of forming a resist pattern by performing a development process, after the exposure and before the development process, the resist itself is baked at a predetermined temperature 1-b higher than the glass transition temperature Tg of the resist (hereinafter referred to as a pre-development base). The resist film is then cooled uniformly from the temperature Tb to an arbitrary intermediate temperature TI, and then rapidly and uniformly cooled from the intermediate temperature TI to the final cooling temperature To. be.

本発明にJ:るレジストパターン形成方法の概要を第4
図に示す。、まず、被処理基板上にレジスト膜を塗布形
成する。次いで、このレジスト前をプリベークし通常の
冷却を行なう。次に該レジスト膜に対して所定のパター
ン露光を行なう。然る優、上記レジスト膜を該レジスト
のガラス転移温度To以上の所定温度Tbでベーク(現
像前ベーク)する。現像前ベーク後、該レジスト感度の
温度(即ちレジスト膜付被処理基板の温度)をベーク温
度Tbから任意の中間冷却温度Tn+ (Tb≧T+a
)へ下げる第1の冷却を行なう。次いで、前記中間冷却
温度Tl11から最終冷却温度Tcへ急速且つ均一に下
げる第2の冷却を行なう、この場合、上記第2の冷却時
における温度差Tm−Tcを任意に選択することによっ
て、最終的に得られるレジスト感度を任意の値に制御す
ることができる。また、レジスト膜付基板全体にわたる
濃度分布を均一に保持するために、ベーク及び冷却処理
は該基板を移動さけず同一場所にて行なう。然る優、斯
かる現像前ベーク・冷却プロセスを経たレジスト感度に
対し現像・リンスを施すことによって所定のレジストパ
ターンを形成する。
The outline of the resist pattern forming method according to the present invention is explained in the fourth section.
As shown in the figure. First, a resist film is coated and formed on a substrate to be processed. Next, the resist is prebaked and cooled normally. Next, the resist film is exposed to light in a predetermined pattern. However, the resist film is baked (pre-development bake) at a predetermined temperature Tb that is higher than the glass transition temperature To of the resist. After pre-development baking, the temperature of the resist sensitivity (that is, the temperature of the substrate to be processed with the resist film) is changed from the baking temperature Tb to an arbitrary intermediate cooling temperature Tn+ (Tb≧T+a
). Next, a second cooling is performed to rapidly and uniformly lower the intermediate cooling temperature Tl11 to the final cooling temperature Tc. In this case, by arbitrarily selecting the temperature difference Tm - Tc during the second cooling, the final cooling temperature is The resist sensitivity obtained can be controlled to any value. Furthermore, in order to maintain a uniform concentration distribution over the entire substrate with a resist film, the baking and cooling treatments are performed at the same location without moving the substrate. However, a predetermined resist pattern is formed by developing and rinsing the resist having undergone the pre-development baking and cooling process.

また本発明は、被処理基板上に塗布されたレジストIQ
をベークしたのち冷却するレジスト処理装置おいて、上
記基板を支持する基板支持具と、この支持具の上方も設
けられ該支持具に支持された基板上に赤外線を照射或い
は熱風を吹き付けて基板上のレジスト膜を該レジストの
ガラス転移温度Tg以上の温度にてベークするベータ機
構と、上記支持具の上方に設けられ該支持具に支持され
た基板上に冷風を吹き付けて基板上のレジスト膜を冷却
する冷却機構とを具備し、上記レジスト膜のベーク及び
冷却を該レジスト膜付基板を移動することなく温度を制
御しながら均一に連続して行うようにしたものである。
The present invention also provides a resist IQ coated on a substrate to be processed.
A resist processing apparatus that bakes and then cools the substrate includes a substrate support that supports the substrate, and is also provided above the support, and irradiates the substrate supported by the support with infrared rays or blows hot air onto the substrate. a beta mechanism for baking the resist film at a temperature equal to or higher than the glass transition temperature Tg of the resist; and a beta mechanism for baking the resist film at a temperature equal to or higher than the glass transition temperature Tg of the resist; A cooling mechanism is provided to uniformly and continuously perform baking and cooling of the resist film while controlling the temperature without moving the resist film coated substrate.

[発明の効果] 本発明によれば、電磁波若しくは粒子線照射に対するレ
ジストの感度を、その解像性を劣下させることなく任意
に設定することができる。例えば低感度のレジストを用
いる場合でも、本発明の方法により解像性を劣下させる
ことなく高感度化できるので、電磁波若しくは粒子線に
よる照射処理時間等を短縮し、レジストパターン形成の
処理時間の大幅な短縮化をはかり得る。また、レジスト
のベーク及び冷却は被処理基板を移動させることなく行
なうので、これらの処理を連続的に且つ迅速に進めるこ
とができる。しかも、ベーク→冷却工程中に被処理基板
を移動させる必要がないので、外部からの不要な熱接触
を招くことなくベーク→冷却へのプロセス処理が均一に
進められる結果、被処理基板上の塗布リンス1へに冷却
むら、すなわら感度むらが生じるのを未然に防止するこ
とができる。したがって、得られるレジストパターンの
寸法均一性は極めて高いものとなる。
[Effects of the Invention] According to the present invention, the sensitivity of a resist to electromagnetic waves or particle beam irradiation can be arbitrarily set without deteriorating its resolution. For example, even when using a low-sensitivity resist, the method of the present invention can increase the sensitivity without deteriorating the resolution, thereby shortening the irradiation time with electromagnetic waves or particle beams, and reducing the processing time for resist pattern formation. It is possible to significantly shorten the time. Furthermore, since resist baking and cooling are performed without moving the substrate to be processed, these processes can be carried out continuously and quickly. Moreover, since there is no need to move the substrate during the baking->cooling process, the baking->cooling process can proceed uniformly without causing unnecessary thermal contact from the outside, resulting in coating on the substrate. It is possible to prevent uneven cooling, that is, uneven sensitivity, from occurring in the rinse 1. Therefore, the resulting resist pattern has extremely high dimensional uniformity.

また、本発明の効果は露光時及び露光前のレジストの熱
履歴には無関係に得られるので、露光時にレジストの温
度上昇が生じても構わないし、従来のプリベーク・冷却
プロセス条件を特に変更する必要もない。さらに、レジ
スト感度を任意の餡に制御できるので、露光装置のリン
スト適用範囲即ち利用し得るレジストの種類を拡大する
ことができる。加えて、露光時のレジストに対する電磁
波や粒子線の照射量が適正でなかったり、照射口を間違
えて露光した場合でも、現像前ベータと上記制御された
冷却を行なうことにより、露光後でもレジストの感度を
制御し、高開度パターンを得るだめのプロセス上の修正
を施すことができる。
Furthermore, since the effects of the present invention can be obtained regardless of the thermal history of the resist during and before exposure, it is not a problem even if the temperature of the resist increases during exposure, and it is not necessary to particularly change the conventional pre-bake/cooling process conditions. Nor. Furthermore, since the resist sensitivity can be controlled to an arbitrary level, the range of rinsing of the exposure apparatus, that is, the types of usable resists can be expanded. In addition, even if the amount of electromagnetic waves or particle beams irradiated to the resist during exposure is not appropriate, or if the irradiation port is exposed incorrectly, by performing the pre-development beta and the above-mentioned controlled cooling, the resist will remain intact even after exposure. Sensitivity can be controlled and process modifications can be made to obtain high opening patterns.

[発明の実施例] 〈実施例〉 本発明ではポリ(2,2,2−トリフルオロエチル−α
−クロロアクリレート)よりなるポジ型電子線感応レジ
ストを用いた場合のレジストパターン形成方法について
述べる。まず、上記レジストを周知の回転塗布法により
被処理基板上に塗布する。塗布膜厚は、例えばQ、3〜
1[μm]程度でよいが、ここでは0.8Eμm]とし
た。被処理基板としては、半導体ウェハやガラス基板等
積々あるが、ここでは金属膜付ガラス基板を用いlこ 
[Example of the invention] <Example> In the present invention, poly(2,2,2-trifluoroethyl-α
A method for forming a resist pattern using a positive electron beam sensitive resist made of (chloroacrylate) will be described. First, the resist described above is applied onto a substrate to be processed by a well-known spin coating method. The coating film thickness is, for example, Q, 3~
It may be about 1 [μm], but here it was set to 0.8Eμm]. There are many substrates to be processed, such as semiconductor wafers and glass substrates, but here we use a glass substrate with a metal film.
.

次に、前レジスト膜をプリベークし、自然放冷した。プ
リベーク温度は160 [’C:]であり、ブリベータ
時間は30分であった。自然放冷時におけるレジスI−
膜全体にわたる濃度分布については特別な注意は払わな
かった。即ち、レジスト膜付基板全体にわたる意図的な
均一冷却は行なわなかった。次いで、前記レジスト膜に
対して所定の条件で電子線露光を行なった。然る後、後
述するようなレジスト処理装置を用いて前記レジスト膜
の現像前ベークと制御された均一冷却処理を行なった。
Next, the pre-resist film was prebaked and allowed to cool naturally. The pre-bake temperature was 160 ['C:] and the pre-bake time was 30 minutes. Regis I- during natural cooling
No special attention was paid to the concentration distribution across the membrane. That is, intentional uniform cooling over the entire resist film coated substrate was not performed. Next, the resist film was subjected to electron beam exposure under predetermined conditions. Thereafter, the resist film was subjected to pre-development baking and controlled uniform cooling using a resist processing apparatus as described below.

ベーク温度Tbは、上記レジストのガラス転移温度T(
1〜133[℃]から200 [”CIの範囲で選択し
てよいが、ここでは180[’C]とした。現像前ベー
クは約10分間行なった。ブリベーク工程でレジストの
溶剤は十分に取り除かれているので、該現像前ベーク時
間をあまり長くする必要はない。本実施例では取り敢え
ず10分間とした。次いで、該レジスト膜付基板の温度
(即ちレジスト膜の温度)を任意の中間冷却温度Tll
1(TIll≦Tb)まで均一に下げた。さらに該基板
の温度を該中間冷却温度TIから最終冷g温度Tcまで
急速且つ均一に下げた。本実施例では中間冷却温度(急
速冷却開始温度)Tmは該リンストのガラス転移温度T
o (〜133℃)を挾んだ、180〜40 [’C]
の範囲で10[’C]ずつ変化させた。また、Jll終
冷却温度TOとしてvlM(25℃)を選んだ。第5図
は中間冷却温度即ら急速冷却開始温度T+++が、例え
ば150[℃]の場合の上記レジスト膜付被処理基板の
冷却時の温度変化Tb−+Tl→TCを示したもので、
被処理基板上のレジスト面で第2図に示したA、B、C
領域と略同等の3領域における温度変化を測定した結果
であ゛る。上記A、B、C各領域の温度変化に対応する
特性が夫々曲線51.52.53で、第3図の従来法の
場合の冷却特性に比べ全体にわたって(Tb −+Tc
 )均一な冷却がなされ、特にT+a−+Tcの冷却領
域では均−且つ急速な冷却が行なわれていることがよく
判る。このような均一(Tb −+Ti −+Tc )
 テ急速(Tm −+Tc )な冷却は他の任意のTs
についても同様に認められた。
The bake temperature Tb is the glass transition temperature T(
The temperature may be selected within the range of 1 to 133[°C] to 200['C], but here it was set to 180['C].The pre-development bake was performed for about 10 minutes.The resist solvent was sufficiently removed in the pre-baking process. Therefore, there is no need to make the pre-development baking time too long.In this example, it was set to 10 minutes.Next, the temperature of the resist film-coated substrate (that is, the temperature of the resist film) was set to an arbitrary intermediate cooling temperature. Tll
1 (TIll≦Tb). Further, the temperature of the substrate was rapidly and uniformly lowered from the intermediate cooling temperature TI to the final cooling temperature Tc. In this example, the intermediate cooling temperature (rapid cooling start temperature) Tm is the glass transition temperature T of the lint.
o (~133℃), 180~40 ['C]
The temperature was varied by 10 ['C] within the range of . In addition, vlM (25°C) was selected as the Jll final cooling temperature TO. FIG. 5 shows the temperature change Tb-+Tl→TC during cooling of the resist film-coated substrate when the intermediate cooling temperature, that is, the rapid cooling start temperature T+++ is, for example, 150 [° C.].
A, B, and C shown in FIG. 2 on the resist surface on the substrate to be processed.
These are the results of measuring temperature changes in three regions that are approximately the same. The characteristics corresponding to temperature changes in each region of A, B, and C are curves 51, 52, and 53, respectively, and compared to the cooling characteristics of the conventional method shown in FIG.
) It is clearly seen that uniform cooling is achieved, particularly in the T+a-+Tc cooling region, uniform and rapid cooling is achieved. Such uniformity (Tb −+Ti −+Tc)
Te rapid cooling (Tm −+Tc) is achieved by any other Ts
The same was also recognized.

なお、被処理基板上々のTmからTcまでの冷却時間は
、本実施例の場合何れも10秒以下であった。中間冷却
温度即ち急速冷却開始温度TIの値を種々変えた場合の
上記ベーク、冷却プロセス(TI)−180℃−+7m
+ −+Tc−25℃)を経た夫々のレジスト試料につ
いて電子線に対する感度(所定現像条件下でレジスト膜
の膜厚残存率がゼロとなる場合の電子線照射量)を調べ
た結果、第6図(a)に示す特性が得られた。第6図(
a >の特性は、上記レジスト膜に20[keV]の電
子線を照射後、前記夫々の現像前ベーク、冷却プロセス
を施し、然る後室温でメチルイソブチルケトン(MIB
K):イソプロビルアルコール(IPA)=7:3現像
液で10分間の現像処理、次いでIPA液にて30秒間
のリンス処理を施こして得られたものである。第6図(
a)に見られるように、Tb−+l”n+→Tcのレジ
スト冷却過程で、中間冷却温度即ち急速冷却開始温度T
Iが該レジストのガラス転移温度Tg (〜133℃)
と略等しくなる温度領域でレジスト感度に幅広い変化が
あられれる。Tb≧TI >To 領域では高いレジス
ト感度が19られ、TIがTbに近づくにつれて感度が
高くなり、最大レジスト感度として〜1.2X10.[
C/cj]が得られる。T(+ >TI >Tc(−2
5℃)領域では、急速冷却開始m1Tllが下降するに
つれてリンスI・感度が低くなり、従来の自然放冷の場
合の感度〜8X10” IC,/cd]に近づく。
Note that the cooling time from Tm to Tc of the substrate to be processed was 10 seconds or less in all cases of this example. The above baking and cooling process (TI) -180°C - +7m when the value of the intermediate cooling temperature, that is, the rapid cooling start temperature TI, is varied.
The sensitivity to electron beams (the amount of electron beam irradiation when the remaining thickness of the resist film becomes zero under the specified development conditions) of each resist sample after undergoing a test (+ - + Tc - 25°C) was investigated, and the results are shown in Figure 6. The characteristics shown in (a) were obtained. Figure 6 (
The characteristics of a> are obtained by irradiating the resist film with an electron beam of 20 [keV], then performing the above-mentioned pre-development baking and cooling processes, and then applying methyl isobutyl ketone (MIB) at room temperature.
K): It was obtained by developing with isopropyl alcohol (IPA) = 7:3 developer for 10 minutes, and then rinsing with IPA solution for 30 seconds. Figure 6 (
As seen in a), in the resist cooling process from Tb−+l”n+→Tc, the intermediate cooling temperature, that is, the rapid cooling start temperature T
I is the glass transition temperature Tg of the resist (~133°C)
There can be a wide range of changes in resist sensitivity in the temperature range that is approximately equal to . In the Tb≧TI >To region, high resist sensitivity is 19, and as TI approaches Tb, the sensitivity increases, and the maximum resist sensitivity is ~1.2X10. [
C/cj] is obtained. T(+ >TI >Tc(-2
5° C.), as the rapid cooling start m1Tll decreases, the rinse I/sensitivity decreases and approaches the sensitivity of conventional natural cooling ~8X10'' IC,/cd].

一方、上記レジストを〜0.8Eμl]の厚さに塗布し
たレジスト膜付基板(金属膜付6インチロガラス基板)
を用意し、上記と同様のプリベーク、自然放冷を行なっ
た後、該レジスト膜付基板の周辺部分を除く全面へ20
[keV]電子線描画装置を用いて、上記夫々の感度に
対応する照射量で選択的パターン露光を行ない、前記夫
々の感度に対応する現像前ベーク(Tb=180℃)と
Tll→Ti −)TO(Tc−25℃)の冷却処理を
施し、然る後室温におけるMIBK/IPA(−773
)現像、IPAリンス処理を行なってレジストパターン
を形成した。これらレジンドパターンは清浄であり、パ
ターンの解像性はすべて良好であった。また、例えば線
幅0.5〜2.0[μFFL]の範囲のシストパターン
の寸法精度を測定評価した結果、いずれの場合のレジス
トパターンもすべて高精度で、基板面内の寸法変動誤差
3σ〈0.1[μTrL]を十分に満足するものであっ
た。
On the other hand, a substrate with a resist film (a 6-inch glass substrate with a metal film) coated with the above resist to a thickness of ~0.8Eμl
After pre-baking and natural cooling in the same manner as above, apply 20 minutes to the entire surface of the resist film coated substrate except for the peripheral area.
[keV] Selective pattern exposure is performed using an electron beam lithography device at a dose corresponding to each of the above sensitivities, and pre-development bake (Tb = 180° C.) and Tll→Ti −) corresponding to each of the above sensitivities are performed. TO (Tc-25°C) was cooled, then MIBK/IPA (-773°C) at room temperature.
) Development and IPA rinsing were performed to form a resist pattern. These resin patterns were clean and all had good pattern resolution. Furthermore, as a result of measuring and evaluating the dimensional accuracy of cyst patterns in the range of line widths from 0.5 to 2.0 [μFFL], the resist patterns in all cases were all highly accurate, with a dimensional variation error of 3σ within the substrate surface. The value of 0.1 [μTrL] was sufficiently satisfied.

〈実施例2〉 本実施例ではレジストとしてポリメチルメタクリレート
を用いた。基本的な工程は実施例1の場合と略同様であ
る。リンスト塗布後のプリベークは160[’C]で3
0分間行ない、プリベーク後自然放冷によってレジスト
膜付基板の冷却を行なった。電子線露光は加速電圧20
[keV]にて行なった。露光後のレジスト膜に対し現
像前ベークと、本発明の冷却プロセスを施した。現像前
べ−り時のベーク温度Tbは、本レジストのガラス転移
温II T U〜110ビC]を越える170[”C]
に設定した。ベーク特開は10分間とした。前記現像前
ベーク後、ベーク温度’1=170[’c]から種々の
中間冷却温度Tmを経て最終冷fJI濃度Tc=25[
℃]に至るリンスi・冷却を行なった。
<Example 2> In this example, polymethyl methacrylate was used as a resist. The basic steps are substantially the same as in Example 1. Pre-bake after rinsing application is 3 at 160['C]
After prebaking, the resist film coated substrate was cooled by natural cooling. Electron beam exposure has an accelerating voltage of 20
[keV]. After exposure, the resist film was subjected to a pre-development bake and a cooling process of the present invention. The baking temperature Tb at the time of baking before development is 170 ["C] which exceeds the glass transition temperature II T U ~ 110 C] of this resist.
It was set to The baking time was 10 minutes. After the pre-development baking, the final cooled fJI concentration Tc=25['c] is passed through various intermediate cooling temperatures Tm from the bake temperature '1=170['c].
℃] was rinsed and cooled.

中間冷却温度即ち急速冷却開始温度Tll1は170〜
40[℃]の範囲で10[℃]ずつ変化させた。
The intermediate cooling temperature, that is, the rapid cooling start temperature Tll1 is 170~
The temperature was changed in steps of 10 [°C] within a range of 40 [°C].

夫々のTmからTc (=25℃)までの冷却時間は本
実施例の場合についても〜10秒以下であった。上記種
々の冷却プロセスを軽だレジスト膜に室温にて13分間
のMIBK現像、30秒間のIPAリンスを行なって、
夫々の感度特性を調べた。
The cooling time from each Tm to Tc (=25°C) was ~10 seconds or less in this example as well. After the various cooling processes described above, the resist film was developed with MIBK for 13 minutes at room temperature, and rinsed with IPA for 30 seconds.
The sensitivity characteristics of each were investigated.

第6図(b)は中間冷却温度、即ち、急速冷却開始温度
Tl1lに対するレジスト感度の変化を現わしたもので
ある。本実施例においても、急速冷却開始温度T’n+
がレジストのガラス転移温度Tl1l−110[’C]
に略等しくなる領域で広い範囲の感度変化が現われる。
FIG. 6(b) shows the change in resist sensitivity with respect to the intermediate cooling temperature, that is, the rapid cooling start temperature Tl1l. Also in this embodiment, the rapid cooling start temperature T'n+
is the glass transition temperature of the resist Tl1l-110['C]
A wide range of sensitivity changes appears in the region approximately equal to .

Tb≧Tl1l >Tgf!h域ではTll1を高くす
る程レジスト感度は高くなり〜2×10−’[C/cd
]もの感度に達する。Tg〉Tm >Tc (−25℃
)領域では、Tmを下げる程レジスト感度は低くなり、
従来の自然放冷の場合の感度〜lX10−6 [C/m
lに近づく。
Tb≧Tl1l >Tgf! In the h region, the higher Tll1 is, the higher the resist sensitivity is ~2×10-'[C/cd
] Reach the sensitivity of things. Tg>Tm>Tc (-25℃
) region, the lower the Tm, the lower the resist sensitivity becomes.
Sensitivity in the case of conventional natural cooling ~ lX10-6 [C/m
approach l.

一方、上記したレジストを〜0.8[μm]の厚さに塗
布したレジス]〜膜付基板(金属膜付6インチロガラス
基板を用意し、上記と同様のプリベーク、自然放冷、露
光(電子線照射量は上記夫々の電子線感度に対応)、現
像前ベーク、Tb→Tm−ITC冷却プロセス(上記夫
々の感度に対応する冷却プロセス)、現像、リンスなど
の処理を施し、レジストパターンを形成した。その結果
、すべての基板上全体にわたりレジストパターンの解像
性は良好であった。また、本実施例においても、線幅0
.5〜2.0[μm゛]の範囲のレジストパターンの寸
法精度を測定評価した結果、何れの場合のレジストパタ
ーンも高精度で、基板面内の寸法変動誤差はすべて3σ
<0.1 [μm]であった。
On the other hand, a resist coated with the above-mentioned resist to a thickness of ~0.8 [μm] ~ a substrate with a film (a 6-inch glass substrate with a metal film) was prepared, and prebaked, naturally cooled, and exposed ( The resist pattern is formed by performing treatments such as (electron beam irradiation amount corresponds to each electron beam sensitivity above), pre-development bake, Tb→Tm-ITC cooling process (cooling process corresponding to each sensitivity above), development, and rinsing. As a result, the resolution of the resist pattern was good over all the substrates.Also, in this example, the line width was 0.
.. As a result of measuring and evaluating the dimensional accuracy of resist patterns in the range of 5 to 2.0 [μm゛], the resist patterns in all cases were highly accurate, and all dimensional fluctuation errors within the substrate plane were 3σ.
<0.1 [μm].

なお、本発明の主眼は、露光後の被処理基板上のレジス
ト膜を現像前ベーク、急速均一冷却することにより、レ
ジスト処理の高速化やレジストパターンの高精度化をは
かることもさることながら、特に、現像前ベーク温度T
bから最終冷却温度TOにベーク後のリンスト躾を冷却
(る過程で任意の中間冷却温度T+++ (Tb≧Tl
1l >Tc )を設け、T鶴を急速冷fJl開始温度
としてリンストi!付基板をR11?′9iI!I温度
Tcへ急速冷却させることにより、レジストの感度を任
意に11 IIIすることにある。したがって、本発明
の方法を用いれば、例えば種々のレジスト照射(露光)
装置の性能に適合覆るように、レジストの感度を任意に
且つ均一に設定づることができる。
The main purpose of the present invention is to bake the resist film on the substrate to be processed after exposure and quickly and uniformly cool it before development, thereby increasing the speed of resist processing and increasing the precision of the resist pattern. In particular, the pre-development bake temperature T
b to the final cooling temperature TO (in the process of cooling the rinst bastard after baking to the final cooling temperature TO, an arbitrary intermediate cooling temperature T+++ (Tb≧Tl
1l > Tc), and set Tsuru as the rapid cooling fJl starting temperature and rinse i! Is the attached board R11? '9iI! The purpose is to arbitrarily increase the sensitivity of the resist by rapidly cooling it to the I temperature Tc. Therefore, if the method of the present invention is used, for example, various resist irradiation (exposure)
The sensitivity of the resist can be set arbitrarily and uniformly to suit the performance of the apparatus.

上記実施例では2種類のレジストに関してのリンストパ
ターン形成例について述べたが、レジストの種類や更に
はリンス]へ膜が被着される基板材料、レジストの溶媒
(上記実施例のリンスI〜の溶媒としては通常メチルセ
ロソルブアセテートが用いられている)、現像及びリン
ス方法、ベーク温度TI)等についても上述した実施例
に限定される 。
In the above example, an example of rinsing pattern formation regarding two types of resists was described. Methyl cellosolve acetate is usually used as the solvent), development and rinsing methods, baking temperature TI), etc. are also limited to the examples described above.

ものではなく、公知の種々の材料、レジスト溶媒、現像
、リンス方法、ベーク温度Tbについても本発明の諸効
果が達成されることを確認している。
However, it has been confirmed that the effects of the present invention can be achieved using various known materials, resist solvents, development and rinsing methods, and baking temperatures Tb.

また、上記実施例においても述べたように、本発明者等
の研究結果によると、レジストのベーク温度Tb及び中
間冷却温度(急速冷却開始温r!I)Tmが該レジスト
ガラス転移温度Tl1以上である場合には、Toより低
い最終冷fJ+温度Tcまでレジストを急速冷却させる
(Tb271027g>Tc)ことによって、レジスト
感度の大幅な向上化が達成できることが確認されている
。さらに、該冷媒の温1[TOが、I+以下の領域で、
低ければ低い程レジスト急速冷却後のレジスト感度は増
々高まることも確認されている。したがって、Tb≧T
m≧T(1>Tcの関係を満たす範囲で、中間冷却温度
、即ち急速冷却開始温度Tl11とレジスト冷却用液体
冷媒の温度Toとを任意の値に選べば、リンストの高感
度化の範囲を更に拡大することができる。TRI−)T
Oの急速冷却に要する時間は本実施例の如く〜10秒以
内であれば本発明の効果を略達成することができるが、
さらに短くづればする程急速冷却の効果を十分に引き出
すことができる。
Furthermore, as described in the above examples, according to the research results of the present inventors, the bake temperature Tb and intermediate cooling temperature (rapid cooling start temperature r!I) Tm of the resist are equal to or higher than the resist glass transition temperature Tl1. It has been confirmed that in some cases, a significant improvement in resist sensitivity can be achieved by rapidly cooling the resist to a final cooling fJ+temperature Tc lower than To (Tb271027g>Tc). Furthermore, in a region where the temperature 1[TO of the refrigerant is below I+,
It has also been confirmed that the lower the resistance, the more the resist sensitivity after resist rapid cooling increases. Therefore, Tb≧T
If the intercooling temperature, that is, the rapid cooling start temperature Tl11, and the temperature To of the liquid coolant for resist cooling are selected to arbitrary values within the range that satisfies the relationship m≧T (1>Tc), the range of high sensitivity of the rinsing can be adjusted. It can be further expanded.TRI-)T
If the time required for rapid cooling of O is within ~10 seconds as in this example, the effects of the present invention can be substantially achieved; however,
Furthermore, the shorter the length, the more the effect of rapid cooling can be fully brought out.

また、レジスト照射(露光)方法については、上記した
電子線以外に光線、X線、イオンビーム等の所定波長域
の電磁波や所定エネルギーの粒子線等を用いても本発明
の効果が得られる。
Furthermore, as for the resist irradiation (exposure) method, the effects of the present invention can be obtained by using, in addition to the above-described electron beam, electromagnetic waves in a predetermined wavelength range such as light beams, X-rays, and ion beams, or particle beams with a predetermined energy.

〈実施例3〉 次に、本発明の方法を実施するのに適合する装置の一例
につい−C第7図を参照して説明する。第7図の装置は
レジスト膜(若しくはレジスト膜付被処理基板)をガラ
ス転移温r!L1J、上の温度でぺ一りし、ベーク後の
レジスト膜を該レジスト膜の温度を制御しながら均一に
冷却乃至急速冷却するための全自動処理装置である。ま
ず、露光済みのレジスト膜付被処理基板71aが、予め
カセット72aに収納されており、所定の搬送シーケン
スの下に、ベルトコンベア73aによって所定位置へ順
次搬送される。次に、前記レジスI−膜付基板71aは
、回転・上下動機構を有する真空チャック搬送器74a
によってベーク・冷却器75の基板支持具76上へ移さ
れる。ここにおいてレジスト膜付被処理基板71bには
所定のベーク・冷却処理が施されるが、本発明の効果を
引き出すためのレジスト処理装置のポイントはこのベー
ク・冷却器75の構造にある。すなわち、本発明のレジ
スト処理装置は、少なくともレジスト膜付被処理基板7
1bを移動することなく、同一場所でべ一り→冷却処理
を他の部分からの不要な熱接触なく均一制御しながら連
続的に実行する機能を有していなければならない。
<Embodiment 3> Next, an example of an apparatus suitable for carrying out the method of the present invention will be described with reference to FIG. 7. The apparatus shown in FIG. 7 converts the resist film (or the substrate coated with the resist film) to the glass transition temperature r! L1J is a fully automatic processing device for uniformly cooling or rapidly cooling a resist film after baking at a temperature above L1J while controlling the temperature of the resist film. First, an exposed resist film-coated substrate 71a is stored in a cassette 72a in advance, and is sequentially transported to a predetermined position by a belt conveyor 73a according to a predetermined transport sequence. Next, the resist I-film coated substrate 71a is transferred to a vacuum chuck conveyor 74a having a rotation and vertical movement mechanism.
is transferred onto the substrate support 76 of the bake/cooler 75. Here, the substrate to be processed with the resist film 71b is subjected to a predetermined baking and cooling process, and the key point of the resist processing apparatus for bringing out the effects of the present invention is the structure of this baking/cooling device 75. That is, the resist processing apparatus of the present invention includes at least the substrate 7 to be processed with a resist film.
It must have the ability to continuously perform the process of flattening and cooling at the same location without moving the 1b, uniformly controlling it and without unnecessary thermal contact from other parts.

第8図は前記機能を持たせたベーク・冷却器の一例でそ
の構造は次のようになっている。すなわち、本例ではレ
ジスト膜付被処理基板81が支持具82上に載置された
状態で、平面状の加熱・冷fJ] vA83が該基板8
1のレジスト塗布面と平行対面するように所定の間隔で
配置されている。平面状加熱・冷却+1183は加熱源
(ベーク機構)84と冷却源(冷却機構)85とを交互
に配列した構造になっている。レジスト塗布面から見た
平面状加熱・冷却源83の具体例を第9図及び第10図
に示した。第9図に示す例は、小孔91を所定の間隔で
画一的に多数設けた清浄材料例えば石英から成る管を、
小孔群がすべてレジスト面に対向するように、平面状に
複数個配列したものである。
FIG. 8 shows an example of a bake/cooler equipped with the above function, and its structure is as follows. That is, in this example, with the resist film-coated substrate 81 placed on the support 82, the planar heating/cooling fJ]vA83 is applied to the substrate 8.
They are arranged at predetermined intervals so as to face parallel to the resist coated surface of No. 1. The planar heating/cooling +1183 has a structure in which a heating source (bake mechanism) 84 and a cooling source (cooling mechanism) 85 are arranged alternately. A specific example of the planar heating/cooling source 83 viewed from the resist coated surface is shown in FIGS. 9 and 10. The example shown in FIG. 9 is a tube made of a cleaning material such as quartz, in which a large number of small holes 91 are uniformly provided at predetermined intervals.
A plurality of small hole groups are arranged in a plane so that all of them face the resist surface.

この場合、清浄な加熱ガス(熱風)を噴出させる情(熟
思導入管)92と、清浄な冷却ガス(冷Jul)を噴出
させる管(冷風導入管)93とを交互に配列しであるの
で所望の効果を生ぜしめるように操作することができる
。第10図に示す例は、第9図に示す例と同様に、小孔
を所定間隔で画一的に多数設けた清浄材料例えば石英か
ら成る管101と、ヒーターを内包した例えば石英から
成る管102とを交互に複数個平面状に配列したもので
ある。この場合、後者を加熱源、前者を第9図に示す例
と同様にして冷却源として使用する。上記機能を持たせ
たベーク・冷却器の他の例を第11図に示す。本例では
、レジスト膜付被処理基板111が支持具112上に載
置された状態で、開口端を略平面状に配置させた管群が
ら成る加熱・冷却m113を該基板111のレジスト塗
布面と平行対面する態様で所定の間隔にて配置している
In this case, the pipes 92 for spouting clean heating gas (hot air) and the pipes 93 for spouting clean cooling gas (cold air) are arranged alternately, so that it can be arranged as desired. can be manipulated to produce the effect of The example shown in FIG. 10 is similar to the example shown in FIG. 9, and includes a tube 101 made of a cleaning material, such as quartz, in which a large number of small holes are uniformly provided at predetermined intervals, and a tube made of, for example, quartz, containing a heater. 102 are arranged alternately in a plane. In this case, the latter is used as a heating source, and the former is used as a cooling source in the same manner as in the example shown in FIG. Another example of a baking/cooling device having the above function is shown in FIG. In this example, with the substrate 111 to be processed with a resist film placed on the support 112, a heating/cooling m113 consisting of a group of tubes whose open ends are arranged in a substantially planar manner is connected to the resist-coated surface of the substrate 111. They are arranged at predetermined intervals so as to face each other in parallel.

この場合、加熱・冷却[113は加熱源用管114と冷
却源用管115とを交互に配列した構造になっている。
In this case, the heating/cooling unit 113 has a structure in which heating source tubes 114 and cooling source tubes 115 are alternately arranged.

レジスト塗布面から見た平面状加熱・冷却器113の一
具体例を第12図に示した。第12図に示す例は、加熱
源用開口(熱風吹出口)121と冷却源用開口(冷風吹
出口)122とを交互にマトリクス状に配列したもので
ある。なお、これら第11図及び第12図に示した例で
は、加熱源用管には加熱ガスを導入し、冷却源用管には
冷却用ガスを導入して、夫々の開口部から加熱ガス、冷
却ガスを噴出させること、によって、所定のべ−り・冷
却処理を行なうことができる。また、ベータ処理に関し
ては上記加熱源用管に赤外線を導入して、開口部からレ
ジスト面へ赤外線を照制させる方法を採ってもよい。
FIG. 12 shows a specific example of the planar heating/cooling device 113 viewed from the resist coated surface. In the example shown in FIG. 12, heating source openings (hot air outlets) 121 and cooling source openings (cold air outlets) 122 are arranged alternately in a matrix. In the examples shown in FIGS. 11 and 12, heating gas is introduced into the heating source tube, cooling gas is introduced into the cooling source tube, and the heating gas, By blowing out the cooling gas, a predetermined baking and cooling process can be performed. Further, regarding the beta process, a method may be adopted in which infrared rays are introduced into the heat source tube and the infrared rays are directed from the opening to the resist surface.

さて、本発明の効果を生せしめるには上述した第8図乃
至第12図に示す例の如きベータ・冷却器を第7図のベ
ーク・冷却器77として使用づる。
Now, in order to produce the effects of the present invention, a beta cooler such as the examples shown in FIGS. 8 to 12 described above is used as the bake cooler 77 in FIG. 7.

ベータ温度Tl)(Tb≧To)、中間冷却温度(急速
冷却開始温度)Ta、@終冷却温度TOなどの設定やT
b→Tn+の第1冷却プロセス、−rm→TCの第2冷
却プロセスなどの制御は、加熱ガスや冷却ガスの温度、
噴出口からのガス流量、赤外Pi!11、ヒータ一温度
、平面状ベーク・冷却器と被処理基板との間隔などをパ
ラメータとした、予めプログラムされた所定のシーケン
スに従って行なえばよい。また、本発明ではベーク後の
レジストの冷却を被処理基板上にて均一に行なうことも
重要なポイントなので、これを乱すような不要な熱接触
は極力避けなければならない。このために被処理基板7
1bの支持具76としては例えばテフロン(デュポン社
商品名)の如き熱伝導率の小さい材料を使用することが
望ましく、さらには該基板と該支持具との接触はできる
だけ点接触状態にする方が望ましい。このようにして所
定のべ−り・冷却処理を終えた被処理基板7Toは、次
に回転・上下動機構を有する真空チャック搬送器74b
によって、ベルトコンベア73b上の所定位置へ移され
る。そしてベーク・冷却流レジスト膜付被処理基板71
cは、所定のシーケンスの下に、ベルトコンベア731
)によってカセット72bに順次収納され、本装置の工
程は完了する。
Settings such as beta temperature Tl) (Tb≧To), intermediate cooling temperature (rapid cooling start temperature) Ta, @final cooling temperature TO, etc.
Control of the first cooling process of b→Tn+, the second cooling process of -rm→TC, etc. is performed by controlling the temperature of the heating gas and cooling gas,
Gas flow rate from the nozzle, infrared Pi! 11. The processing may be carried out according to a pre-programmed sequence using parameters such as the temperature of the heater and the distance between the planar bake/cooler and the substrate to be processed. Furthermore, in the present invention, it is important to uniformly cool the resist after baking on the substrate to be processed, so unnecessary thermal contact that would disturb this must be avoided as much as possible. For this purpose, the substrate to be processed 7
It is preferable to use a material with low thermal conductivity, such as Teflon (trade name of DuPont), as the support 76 of 1b, and furthermore, it is better to make the contact between the substrate and the support as point-contact as possible. desirable. The substrate to be processed 7To, which has been subjected to the predetermined baking and cooling process in this way, is then transferred to a vacuum chuck carrier 74b having a rotation and vertical movement mechanism.
is moved to a predetermined position on the belt conveyor 73b. Then, a substrate 71 to be processed with a baking/cooling flow resist film
c is a belt conveyor 731 under a predetermined sequence.
) are sequentially stored in the cassette 72b, and the process of this apparatus is completed.

なお、本装置は枚葉式の処理方法を採用しているので、
状況によってはベーク・冷却部分における処理時間が長
くなって、高スループツ1〜化がはかれない場合も生じ
る。このような場合には、該ベータ・冷却器を例えばサ
ークル状若しくは並列状に複数個配置し、適正な遅延時
間を設定して、サークル的若しくは並列的にベーク・冷
却処理を行なうことにより、装置全体としての高スルー
プツト化をはかることが可能である。さらには、べ一り
・冷却器を所定許容範囲内で大型化し、バッチ処理方式
にすることもできる。平面状ベーク・冷却器は、レジス
ト面に対するベーク・冷却の均一性を強化するために、
通常はそのベータ・冷却面領域を平行対面しているリン
スト面領域よりも余裕をもって広くしておく方が望まし
い。また、上記均一性なども含めて所定の効果を得るた
めに、上記平面状ベーク・冷却器の加PjA[と冷却源
との配置は状況に応じて変化されても良い。上記リンス
I・処理H置の平面状ベーク・冷却器は被処理基板上の
レジスト面(表面)に対面する形態になつ−Cいるが、
レジスミ−面とは反対側の被処理基板面(11面)に所
定の間隔にて平行対面する形態で平面状ベーク・冷却器
をさらに追加してもよい。
Please note that this device uses a single-wafer processing method, so
Depending on the situation, the processing time in the baking and cooling portions may become longer, making it impossible to achieve a high throughput. In such a case, the equipment can be improved by arranging a plurality of beta coolers, for example, in a circle or in parallel, setting an appropriate delay time, and performing the baking and cooling process in a circle or in parallel. It is possible to increase the overall throughput. Furthermore, it is also possible to increase the size of the container/cooler within a predetermined allowable range and adopt a batch processing method. The planar bake/cooler is designed to enhance the uniformity of baking/cooling on the resist surface.
Normally, it is desirable to make the beta/cooling surface area wider than the linst surface area facing parallel to each other. Further, in order to obtain a predetermined effect including the above-mentioned uniformity, the arrangement of the heating PjA of the planar bake/cooler and the cooling source may be changed depending on the situation. The planar baking/cooling device in the rinsing I/processing H position is configured to face the resist surface (surface) on the substrate to be processed.
A planar baking/cooling device may be further added in such a manner that it faces the surface of the substrate to be processed (11th surface) opposite to the resistive surface in parallel at a predetermined interval.

上記装置の大きな特徴を追記すると、ベーク・冷IJ1
処理が、従来の大型オーブン、広い冷却エリアに代わっ
て、曝め゛【小型化された単−SAMで可能になったこ
と、?1処理基板の搬送移動が自動的にしかも狭いスペ
ースで行なわれるのでレジスト付基板へのダストの付着
が大幅に低減し製品歩留りが向上すること等があげられ
る。
To add the major features of the above equipment, the bake/cold IJ1
Processing is now possible with a miniaturized single-SAM instead of the traditional large oven and large cooling area. Since the transport and movement of one processed substrate is carried out automatically and in a narrow space, the adhesion of dust to the resist-coated substrate is greatly reduced and the product yield is improved.

尚、斯かるレジスト処理装置はあらゆる露光装置に組み
込むことができる。
Incidentally, such a resist processing apparatus can be incorporated into any exposure apparatus.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のレジストパターン形成工程を概略的に示
す流れ作業図、第2図は従来工程におけるレジストベー
ク後の被処理基板の各点のII度変化の様子を等温曲線
で示す模式図、第3図は前記温度変化の様子を時間対温
度曲線で示す特性図。 第4図は本発明によるリンストパターン形成工程を概略
的に示す流れ作業図、第5図は本発明におけるレジス]
〜冷却時の基板2gi度変化を示す特性図、第6図(a
 ) (b )は本発明の方法によって得られるレジス
ト感度に関する特性図、第7図は本発明の方法実施に適
合するレジスト処理装置の一例を示す概略構成図、第8
図〜第12図はそれぞれ上記装置の要部構成を拡大して
示す図である。 71a 〜71cm@処理基板、72a〜72b・・・
カセッ1−173a〜73b・・・ベルトコンベア、7
4a〜74b・・・真空チャック搬送器、75・・・べ
−り・冷却器、76・・・基板支持具、81・・・被処
理基板、82・・・基板支持具、83・・・加熱・冷却
源、84・・・加熱源、85・・・冷却源、91・・・
小孔、92・・・加熱管、93・・・冷却管、101・
・・冷却管、102・・・ヒーター内包加熱管、111
・・・被処理基板、112・・・基板支持具、113・
・・加熱・冷却源、114・・・加熱源用管、115・
・・冷却源用管、121・・・加熱源用開口、122・
・・冷却源用開口。 出願人代理人 弁理士 鈴江武彦 第6図 (a) (b) 急速岸支Y開俤温人’rm(”c) −第7図 第8図 第9図 第101°4 第11図 第12rg4
FIG. 1 is a flowchart schematically showing a conventional resist pattern forming process, and FIG. 2 is a schematic diagram showing an isothermal curve showing how each point on the substrate to be processed changes by degrees after resist baking in the conventional process. FIG. 3 is a characteristic diagram showing the state of the temperature change as a time versus temperature curve. FIG. 4 is a flowchart schematically showing the rinsing pattern forming process according to the present invention, and FIG. 5 is a resist pattern forming process according to the present invention]
~Characteristics diagram showing the 2gi degree change of the substrate during cooling, Figure 6 (a
) (b) is a characteristic diagram regarding the resist sensitivity obtained by the method of the present invention, FIG. 7 is a schematic configuration diagram showing an example of a resist processing apparatus suitable for carrying out the method of the present invention, and FIG.
1 to 12 are enlarged views showing the main structure of the above-mentioned apparatus. 71a ~ 71cm@processed substrate, 72a ~ 72b...
Cassette 1-173a to 73b...belt conveyor, 7
4a to 74b... Vacuum chuck carrier, 75... Bale/cooler, 76... Substrate supporter, 81... Substrate to be processed, 82... Substrate supporter, 83... heating/cooling source, 84... heating source, 85... cooling source, 91...
Small hole, 92... Heating tube, 93... Cooling tube, 101.
... Cooling pipe, 102 ... Heating pipe with built-in heater, 111
...Substrate to be processed, 112...Substrate support, 113.
...Heating/cooling source, 114...Heating source tube, 115.
...Cooling source pipe, 121...Heating source opening, 122.
...Opening for cooling source. Applicant's agent Patent attorney Takehiko Suzue Figure 6 (a) (b) Rapid shore support Y Kaito Onjin'rm (''c) - Figure 7 Figure 8 Figure 9 Figure 101°4 Figure 11 Figure 12rg4

Claims (7)

【特許請求の範囲】[Claims] (1) 被9!l Ig; m板上にレジス1へ膜を塗
fli形成し、プリベークした1殺、所定波長の電磁波
或いは所定」−ネルキーの粒子線を上記−レジストIQ
に選択的に照Q4シて該レジスト膜を露光し、現像処理
を流すことによりレジス1へパターンを形成づる方法に
おいて、前記露光(9で前記現像処理の前に前記し・シ
スト膜を該レジメ1−のガラス転移温度T 0以上の所
定)8度−1−bにてベークし、次いて前記レジスト膜
を前記濃度T bから任意の中間温度Tl+まで均一に
冷却し、しかるのち前記レジスト+taを中間)温度T
l11から最柊冷N]温度Tcまで急速且つ均一に冷却
−4ることを11黴とりるレジストパターン形成り法。
(1) Covered by 9! l Ig; Apply a film to the resist 1 on the m plate, pre-bake it, and apply electromagnetic waves of a predetermined wavelength or a predetermined Nerky particle beam to the above-resist IQ.
In the method of forming a pattern on the resist 1 by selectively exposing the resist film to light Q4 and performing a development process, The resist film is baked at a predetermined glass transition temperature T (predetermined value T0 or higher) of 8 degrees -1-b, and then the resist film is uniformly cooled from the concentration Tb to an arbitrary intermediate temperature Tl+, and then the resist film is (intermediate) temperature T
11 A resist pattern forming method that removes mold by rapidly and uniformly cooling the temperature Tc from 11 to 11.
(2) 前記各2FA度−ro 、T11.’rm 、
Tcは、」11≧1−i≧■す>TCなる1IFl係を
満たづCとを特徴とする特許請求の範囲第1項記載のレ
ジストパターン形成方法。
(2) Each of the above 2FA degree-ro, T11. 'rm,
2. The resist pattern forming method according to claim 1, wherein Tc satisfies the relation 1IFl such that 11≧1−i≧■su>TC.
(3) 上記レジスト膜の露光後の現像前ベーク及びそ
れに続く冷却は、該レジスト膜付被処理基板を移動する
ことなく同一場所にて行なうことを特徴とする特許請求
の範囲第1項又は第2項記載のレジスI・パターン形成
方法。
(3) Pre-development baking and subsequent cooling of the resist film after exposure are performed at the same location without moving the resist film-coated substrate. The method for forming a resist I pattern according to item 2.
(4) 被処理基板上に塗布されたレジスト膜をべ−り
したのち冷fJIするレジスト処理装置において、前記
基板を支持する基板支持具と、この支持具の上りに設置
ノられ該支持具に支持された基板上に赤外線を照11J
或いは熱風を吹き付けて基板上のレジスト膜を該レジス
トのガラス転移温度Tg以上の温度でベークJるベーク
機構と、上記支持具の上方に設けられ該支持具に支持さ
れた基板上に冷風を吹き付けて基板上のレジスト幌を冷
却する冷却機構とを具備し、上記レジスト膜のベーク及
び冷却を連続して行うことを特徴とするレジスト処理装
置。
(4) In a resist processing apparatus that performs cold FJI after baking a resist film coated on a substrate to be processed, there is a substrate support that supports the substrate, and a substrate that is installed on the top of the support and that is attached to the support. Illuminating infrared light onto the supported substrate 11J
Alternatively, a baking mechanism that blows hot air to bake the resist film on the substrate at a temperature equal to or higher than the glass transition temperature Tg of the resist, and a baking mechanism that is provided above the support and blows cold air onto the substrate supported by the support. 1. A resist processing apparatus comprising: a cooling mechanism for cooling a resist hood on a substrate, and continuously baking and cooling the resist film.
(5) 前記ベーク1i1411は直線状のヒータから
なり、前記冷却機構は下方に複数の冷風吹出孔を有する
直線状の冷風導入管からなり、且つ上記ヒータ及び冷f
fl導入管を前記支持具に支持された基板表面と対向す
る面内で交互に平行配置してなることを特徴とする特許
請求の範囲第4項記載のレジスト処理VR@。
(5) The bake 1i 1411 is composed of a linear heater, the cooling mechanism is composed of a linear cold air introduction pipe having a plurality of cold air blowing holes below, and the heater and the cold f
5. The resist processing VR@ according to claim 4, wherein the fl introduction tubes are alternately arranged in parallel in a plane facing the surface of the substrate supported by the support.
(6) 前記ベーク機構は下方に複数の熱風吹出孔を有
する直線状の熱風導入管からなり、前記冷却111#l
は下方に複数の冷風吹出孔を有する直線状の冷風導入管
からなり、且つ上記熱IN!導入管及び冷風導入管を前
記支持具に支持された基板表面と対向する面内で交互に
平行配置してなることを特徴とする特許請求の範囲第4
項記載のレジスト処理装置。
(6) The baking mechanism consists of a straight hot air introduction pipe having a plurality of hot air blowing holes at the bottom, and
consists of a straight cold air introduction pipe having a plurality of cold air blowing holes at the bottom, and the above-mentioned heat IN! Claim 4, characterized in that the introduction pipes and the cold air introduction pipes are alternately arranged in parallel within a plane facing the surface of the substrate supported by the support.
The resist processing apparatus described in .
(7) 前記ベーク機構は複数の熱風吹出口からなり、
前記冷却機構は複数の冷風吹出口からなり、且つ上記熱
風吹出口及び冷風吹出口を前記支持具に支持された基板
表面と対向する面内でマトリクス状にそれぞれ交互に配
列してなることを特徴とする特許請求の範囲第4項記載
のレジスト処理装置。
(7) The baking mechanism includes a plurality of hot air outlets,
The cooling mechanism includes a plurality of cold air outlets, and the hot air outlets and the cold air outlets are arranged alternately in a matrix in a plane facing the surface of the substrate supported by the support. A resist processing apparatus according to claim 4.
JP59033585A 1984-02-24 1984-02-24 Resist pattern formation method Expired - Lifetime JPH0746676B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59033585A JPH0746676B2 (en) 1984-02-24 1984-02-24 Resist pattern formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59033585A JPH0746676B2 (en) 1984-02-24 1984-02-24 Resist pattern formation method

Publications (2)

Publication Number Publication Date
JPS60178626A true JPS60178626A (en) 1985-09-12
JPH0746676B2 JPH0746676B2 (en) 1995-05-17

Family

ID=12390592

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0746676B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS646836A (en) * 1987-06-30 1989-01-11 Japan Res Dev Corp Optical force sensor
JPH0255360A (en) * 1988-08-22 1990-02-23 Tokyo Electron Ltd Regist processor
WO2001084243A1 (en) * 2000-05-01 2001-11-08 Advanced Micro Devices, Inc. Use of rta furnace for photoresist baking

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176936A (en) * 1982-04-09 1983-10-17 Fujitsu Ltd Substrate cooling method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58176936A (en) * 1982-04-09 1983-10-17 Fujitsu Ltd Substrate cooling method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS646836A (en) * 1987-06-30 1989-01-11 Japan Res Dev Corp Optical force sensor
JPH0255360A (en) * 1988-08-22 1990-02-23 Tokyo Electron Ltd Regist processor
WO2001084243A1 (en) * 2000-05-01 2001-11-08 Advanced Micro Devices, Inc. Use of rta furnace for photoresist baking

Also Published As

Publication number Publication date
JPH0746676B2 (en) 1995-05-17

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