JPS6017486A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a display control circuit for performing multi-window display.

<Prior art> When one display device is used as n screens (windows), conventionally the screen is divided as shown in Figure 1(a), or the window is divided as shown in Figure 1(b). A method of overlapping is known.

However, in conventional display circuits, the contents of the image information memory must be the same as the display screen, and in order to change the division position or turn the overlapping upside down, the image information memory must be the same as the display screen. It had to be rewritten and took a very long time.

<Object of the Invention> The present invention has been made for the purpose of solving the above-mentioned conventional problems, and it is possible to convert any area of the image information memory as shown in FIG. 2(a) into the area shown in FIG. This allows the display to be superimposed on any position on the display screen, and the priority order of superimposition can be changed freely and instantaneously using a program. In addition, operations such as moving or changing the size of a window, or changing the image information in the window to another area of the image information memory can be performed instantaneously using a program.

<Embodiment> As shown in FIG. 3, a conventional display circuit includes an address counter 1, an image information memory 2, and a display timing circuit 3.
, consists of horizontal and vertical timing circuits 4 (5 is a display, 6 is a pass line), and the contents of the image information memory indicated in order by the address counter are displayed on the display under timing control. It's structured. In this way, since the address counter only indicates the image information memory in order, as shown in FIG.
In order to display a display screen like the one shown in b), the contents of the image information memory had to be the same as the display screen.

In the present invention, as shown in FIG. 2, the image information memory does not need to be the same as the display screen, and parts of the image information memory can be displayed by superimposing them.

The present invention is realized by placing an address conversion circuit 7 between the conventional address counter I and the image information memory 2 as shown in FIG. That is, instead of sequentially indicating the image information memory as in the conventional technique, the address indicating the image information memory is arbitrarily converted to indicate and display an arbitrary location in the image information memory.

If this address conversion circuit is depicted in a little more detail, it will be as shown in FIG. Here, the mechanism of address conversion will be explained with reference to Fig. 6 ((a) shows the contents of the image information memory, and (b)
) indicates the display screen). In conventional display circuits, if the display start address is SAD, then SAD
The portion corresponding to the display screen (the portion above the dotted line in the sixth drawing image information memory) is displayed as is.

Therefore, in order to display the display screen of FIG. 6(b), the area A should be placed in the area B.

In other words, all you have to do is change the address that indicates B to A. Now, assume that the start address of area B is a, and the start address of area A is a'. Also, let a−a=α. Here, when the address counter starts from SAD and reaches a, if we add the bias value α, a + α = a', and the contents of area A are displayed in area B, resulting in the display screen shown in Figure 6. . However, with this alone, there is no boundary information indicating the extent of area A, so the display screen only displays area A and one screen around it.

Therefore, in order to determine the boundary, the column address counter 11, column map RAM+2, row address counter 13, row map RAM+4, priority register 15, and window selection circuit 16 shown in FIG. 5 are provided. The column address counter 11 is a counter that counts in the horizontal direction of the display screen using the display clock DISPCLOCK as a counter clock signal and the horizontal and vertical BLANK signals as reset signals. On the other hand, the row address counter I3 is a counter that counts the vertical direction of the display screen using the horizontal and vertical BLANK signals as clock signals and the vertical synchronization signal (VSYNC) as a reset signal. Also, column map RAM +2, row map RAM14
The two RAMs in each window wO-w as shown in Figure 7.
This is a screen boundary memory that stores the boundaries of 3 divided horizontally and vertically. The window selection circuit I6 is shown in FIG.

21.22 T flip-flops are column-row map RA
Data from M Row MAP Data, Column
n MAPData becomes 1 and output Q until the next 1 comes
is set to be 1. The next 23 AND gates are the part where the outputs of 81 and 82 are both 1, that is, the 7th
It is set to 1 in each window area in the figure.

When there are four windows, four sets of 21 to 23 are required. When passing through the above circuit, multiple windows may overlap in some parts. Here, 24 priority circuits determine the top and bottom of the stack according to the priority orders specified by the 15 priority registers. After passing through the priority circuit, at most one window is selected at a certain moment, and the bias register +7Q to +173 corresponding to the selected window number 5Q-s3 is selected by the multiplexer 18, and the bias value that is the stored content is selected by the multiplexer 18. ao~α3 is
It is added to the address a from the previous stage address counter (
(by the full adder 19), the address becomes address a', indicating the image information memory, and a window is displayed.

FIGS. 9 and 10 show the correspondence between the priority register (a) and the display screen (b). When there are 4 windows, the priority register 15 is 2 bits x
4 = 8 bits required, 00 from the lowest priority
,0+,10. If we decide to use II, the priority order in Figure 9 becomes Wo<Wl<W2<Wa, so
), and even if the boundaries are the same, the priority order in FIG. 10 is WO>Wl>W2>Wa, resulting in a display screen different from that in FIG. 9.

Here, in order to simplify the explanation, the number of windows is four, but any number of windows is possible.

In FIG. 5, the column map RAM + 2, row map RAM I 4, priority register 15, and bias register +7Q to 173 can be freely rewritten by the program, so it is possible to move the window, change the thick awning, or overlap the windows. Up and down switching can be done instantly without rewriting the image information memory.

With the above hardware, it is now possible to work on the display screen with many books, drawings, and report sheets placed on the desk, and the degree of freedom and usage efficiency of the display screen and image information memory has been improved. It is measured.

The present invention can be applied to character displays, bitmap displays, and CRTs (cathode ray tubes).

Can be used for EL, plasma displays, etc.

<Effect> +) To specify the position and size of a window, you only need to write up to four points in the screen border memory, and you can instantly move and change the size of the window.

2) By simply specifying the priority order in the priority register, the upper and lower priority order of window stacking can be instantly changed.

3) Address conversion can be performed simply by specifying the bias value for address conversion in a register called bias register.
Since the bias register can be freely rewritten, the window display area of the image information memory can be moved freely and instantaneously.

4) The degree of freedom of the screen is improved and the efficiency of use of the image information memory is improved.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are diagrams showing examples of multi-window display. FIG. 2 is a diagram for explaining the present invention, in which (a) shows the contents of the image information memory, and (b) shows the display screen. FIG. 3 is a block diagram showing a conventional display circuit. FIG. 4 is a block diagram showing a display circuit according to the present invention. FIG. 5 is a block diagram showing a specific configuration of the address translation circuit shown in FIG. 4. FIG. 6 is a diagram for explaining address conversion, in which (a) shows the contents of the image information memory, and (b) shows the display screen. FIG. 7 is a diagram for explaining the column and row map RAM shown in FIG. 5. FIG. 8 is a block diagram showing a specific configuration of the window selection circuit 16 shown in FIG. 5. FIGS. 9 and 10 are diagrams for explaining the correspondence between the contents of the priority register and the display screen. Description of symbols I Near address counter, 2: Image information memory, 3: Display timing circuit, 4: Horizontal/vertical timing circuit, 5: Display, 6: Bus line, 7: Address conversion circuit,
II: Column address counter, 12: Column map RAM, 1
8: Row address counter, 14: Row map RAM, 15
16: window selection circuit, 170-178: bias register, 18: multiplexer, 19: full adder, 21.22: T flip-flop, 23: AND gate, 24: priority circuit. (A No. (a) (b) Figure 1 Figure 2 Figure 9 Illustration 10 α1

Claims (1)

[Claims] 1. In order to specify window boundaries in multi-window display, information about the boundaries in two directions (vertical and horizontal) is stored in separate screen boundary memories, and each window is displayed in an arbitrary area of the image information memory. Therefore, the display address is converted by adding a bias value to the display address, and windows are superimposed with priority by specifying the window priority in the priority register. Features a display control circuit.