JPS60173978A - solid-state imaging device - Google Patents

Abstract

PURPOSE:To prevent diffusion of a pseudo signal electric charge by forming a shallow or deep groove packed with an insulation material or a semiconductor material between a photoelectric converting element group and a signal charge transfer element group. CONSTITUTION:A photodiode part 5 and an imbedded type vertical CCD channel 6 are formed by the 1st conduction type (e.g., n-channel) diffusion layer. A well diffusion layer 18-1 of the 2nd conductor type (e.g., p-channel) at the lower part of the photodiode 5 and the well diffusion layer 18-2 at the lower side of the vertical CCD channel 6 are formed on an n-channel semiconductor substrate 17. The wells 18-1, 18-2 are connected electrically at the lower part of a transfer gate 11. After a groove is formed by etching a part of the well diffusion layer, this groove is packed with the insulation material so as to form a pseudo signal electric charge diffusion preventing region 21-1. Since the depth xd of the insulation layer 21-1 is deeper than the depth xw of the well and the wells 18-1, 18-2 are separated completely, it is prevented that the signal electric charge 14 generated in the well 18-1 due to incident light is diffused and enters the well 18-2, and a false signal to the channel 6 of the vertical CCD is mixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a CCD type and MOS type black and white image forming apparatus in which a photoelectric conversion element and a scanning element for extracting a plurality of color signals and optical information are integrated on a semiconductor substrate. and a color solid-state image sensor.

[Background of the invention]

The fixed image sensor requires an image sensor with a resolution comparable to that of the imaging electron tube used in current television broadcasting, and therefore requires a photoelectric conversion element that constitutes a matrix of about 500 x 400 pixels and an equivalent scanning element. element is required. Therefore, the above-mentioned solid-state image sensor is manufactured using MO8 large-scale integrated circuit technology, which is relatively easy to achieve high integration, and generally consists of COD (photodiode + CCD shift register) or MOS transistor (photodiode + MOS shift register). ~ registers) etc. are used.

FIG. 1 shows the basic configuration of a conventional interline type CCD solid-state image sensor. 1 is a photoelectric conversion element consisting of a photodiode, 2 and 3 are vertical COD shift registers and horizontal CCD shift registers for taking out the optical signals accumulated in the photoelectric conversion element to the output end, and 4 is the signal accumulated in the photoelectric conversion element. This is a gate that transfers the optical signal to the vertical CCD shift register 2. FIG. 2(a) is an example of a cross-sectional view taken along line AA' in FIG. 1 when the COD is of a buried channel type. A photodiode section 5 stores optical signal charges generated by incident light in a PN junction capacitor or the like, and is formed of a first conductivity type diffusion layer (for example, n-type). Reference numeral 6 denotes a buried vertical COD channel, which is formed of a low concentration diffusion layer of a first conductivity type (for example, n-type). 7 is a semiconductor substrate of a second conductivity type (for example, p-type), and 8 is a high concentration diffusion layer of a second conductivity type as a channel stopper. Reference numerals 9 and 10 indicate CCD electrodes (gate electrodes), which are generally made of a first layer of polycrystalline silicon and a second layer of polycrystalline silicon that is slightly shaped like the first layer. Reference numeral 11 denotes a transfer gate that sends the optical signal charge accumulated in the photodiode section 5 to the channel 6 of the vertical CCD, and is generally made of the third layer of polycrystalline silicon, but it is made of the first or second layer. C.C.
The D electrode may be extended and used instead. 12 is a gate oxide film, and 13 is an insulating isolation film 5i02 formed by a conventional selective oxidation method. Reference numeral 14 denotes optical signal charges (for example, electrons) generated by light incident on the photodiode section.

FIG. 2(b) is an example of a sectional view taken along line BB' in FIG. In FIG. 2(b), the signal charge accumulated in the photodiode section 5 is transferred to the vertical COD channel 6 through the transfer gate channel 15 by applying a predetermined voltage to the transfer gate 11. There are other components that enter the vertical COD channel 6 through processes other than those described above that are unique to the so-called solid-state image sensor. Optical signal charges 14 excited in the silicon by light incident on the photodiode section 5 are generated deeper as the wavelength of the light becomes longer from blue to red. Since the generated optical signal charge 14 is isotropically diffused within the substrate, in addition to the component 16-1 that reaches and accumulates in the photodiode section 5, the channel of the vertical CCD adjacent to the photodiode section 5 Component 16 reaching 6
-2, and the optical signal component 16-2 is called a smear. Smear increases as the wavelength becomes longer, and since this smear is added as a false signal to the signal being scanned, image quality is significantly impaired, and smear is a major problem with current solid-state image sensors.

In order to suppress this mire, the following structure has recently been proposed (V, Tshjhara et al.
.

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p. 168). FIG. 3 is a cross-sectional view taken along B-4' of WI when the above structure is adopted. 18 is a semiconductor substrate of the first conductivity type (for example, type 11)]7
A well diffusion layer of a second conductivity type (for example, p-type) is formed on the well diffusion layer. Reference numeral 19 indicates a second conductivity type diffusion layer formed in the transfer gate portion, and reference numeral 20 indicates a CCD electrode formed of polycrystalline silicon as the first layer which also serves as the transfer gate I. In this structure, the thickness W of the well in the photodiode section is
It is shallower than the well thickness WQ of the shift register section, and the concentration is also thinner. The effect of this structure on smear is as follows.

(1) Charges 16-3 generated deeper than the well can be removed from the substrate 17 by applying a reverse bias between the substrate 17 and the well 18.
absorb into.

(ii) The concentration of the well below the photodiode section 5 is made thinner than the surrounding wells to form a potential barrier caused by the concentration difference, thereby preventing the smear component 16-4 from diffusing into the channel of the adjacent vertical CCD. can do.

This structure reduces smear, which is a problem with solid-state image sensors, and greatly improves image quality. However, this structure still has the following problems, and drastic improvements are required in order to improve performance and put it into practical use (mass productivity, etc.).

(1) The depth of the well 18 is W, 3 to 5 μm, 9W2, 5
~8 μm is required, and wl or Wc! An amount equivalent to 100% is also diffused in the horizontal direction. This depends on the dimensions of the wiring and electrodes formed on the main surface, and the gap (currently 1.5 to 3
μm). For this reason, the entire well area directly below the photodiode is shallower and has a lower concentration than the surrounding area (
It is difficult to obtain d) in Figure 3.

(2) If the alignment of the mask for forming the well depth W is poor,
) Due to the lateral diffusion mentioned above, the shallow region W has large variations in dimensions, and as a result, the smear suppression rate differs depending on the element.

(3) In the future, if the pixel size will be reduced by 9 compared to the present to improve resolution, this will increase even more than the previous item (]), and it will become virtually impossible to design the area with depth C into a predetermined shape. It becomes possible (
(This is because the lateral diffusion on the WQ side also pushes into the W, side).

(4) If the precision of the mask alignment described in the previous section (2) is poor, and if the smear suppression rate is below the allowable value, the device will be defective (yield decrease), increasing the price of the device itself or the video camera.

The yield of an image sensor whose element size is 4 to 10 times larger than that of a normal IC is the most important factor for the practical application of solid-state image sensors (solid-state video cameras).

[Purpose of the invention]

An object of the present invention is to eliminate the charges generated deep in the substrate by a false value signal charge diffusion prevention region, or by the diffusion prevention region and an impurity region provided thereunder, in order to improve the conventional drawbacks as described above. It is an object of the present invention to provide a solid-state image sensor that can drastically reduce false signals that are diffused and mixed into adjacent signal charge scan fI or photoelectric conversion elements.

[Summary of the invention]

In order to achieve the above object, the present invention transfers the optical signals accumulated in the photodiode and rode to the signal charge scanning area Z1. ．． In the area other than the transfer area (that is, in the area excluding the transfer gate), a second conductivity type semiconductor substrate formed on the first conductivity type semiconductor substrate -F by photoetching or the like is placed between the photodiode and the signal charge scanning area. Forming a trench shallower than the impurity diffusion layer or deeper than the second conductivity type impurity region reaching the substrate, and filling the trench with a line image material or semiconductor material, or directly filling it by oxidation. By this, a deep false value signal charge diffusion prevention region is formed, and the false signal generated under the photodiode is diffused and mixed into the signal charge scanning region or the photoelectric conversion element, and the diffusion prevention region directly blocks the false signal. Alternatively, the impurity diffusion layer is used in combination with the diffusion prevention region and is of the second conductivity type or the second electric shock type formed under the diffusion prevention region.

[Embodiments of the invention]

The present invention will be described in detail below using Examples.

FIG. 4(a) is an example of a cross-sectional structure taken along the line AA' in FIG. 1 when the present invention is applied to an interline type COD solid-state imaging device. Reference numeral 5 denotes a photodiode section, which is formed of a first conductivity type (for example, n-type) diffusion layer. Reference numeral 6 denotes a channel of a buried vertical CCD, which is formed of a first conductivity type diffusion layer. 17 is a first conductivity type semiconductor substrate;
8-1 is a second conductivity type well diffusion layer (for example, p-type) below the photodiode, and 18-2 is a well diffusion layer below the vertical CCD channel. The second conductivity type layer may be an epitaxial layer instead of a diffusion layer.

Well 18-1 and well 18-2 are shown in FIG. 4 (c) shown later.
) are electrically connected below the transfer gate 11. 21-1 is a false value signal charge diffusion prevention region (deep insulation isolation layer) formed by etching a part of the well diffusion layer to form a groove, and then filling this groove with an insulating material. In FIG. 4(a), the depth X, t of the deep insulating layer 21-1 is deeper than the well depth Xw, and FIG.
In the cross section at , the well 18-1 under the photodiode and the well 18-2 under the vertical CCD channel are completely separated, so the signal charge 14 generated in the well 18-1 by the incident light is diffused. The structure is such that it does not enter the well 18-2 and mix into channel 6 of the vertical CCD as a false signal.

FIG. 4(b) is a potential diagram within the well indicated by the broken line in FIG. 4(a). For example, Sin.

Since an insulator such as the one shown in FIG. 1 forms a much higher potential than a semiconductor, the signal charge 14 cannot cross the potential barrier and diffuse from the well 18-1 to the well 18-2.

FIG. 4(c) is an example of a cross-sectional structure taken along line B-B' in FIG. 21-2 is an insulating isolation layer having a depth Xl shallower than the well depth XW. Although this structure sufficiently serves to prevent diffusion, since the insulating separation layer 21-2 is shallower than the well 18, some of the signal charges 14 generated in the deep part pass under the separation layer 21-2 and become false signals. obtain. Figure 4 (d
) is below the insulating separation layer 21-2 in FIG. 4('c),
This is a case where an impurity layer 22 of a second conductivity type and higher concentration than the well 18 (for example, p-type) is provided. Potential barrier and deep insulation separation 21-2 caused by the concentration difference between the diffusion layer 22 and the well 18
Can be used in combination to prevent false signals.

FIG. 4 (8) is an example of a cross-sectional structure taken along line c-c' in FIG. It has a separate structure. With this structure, the signal charge 14 generated at the bottom of the photodiode diffuses into the adjacent photodiode, causing false signals (crosstalk).
Similar to smear, this can be prevented by the deep insulating separation layer 21-2 and the diffusion layer 22. Furthermore, if the diffusion layer 22 formed under the deep insulating separation layer 21-2 is formed to reach the semiconductor substrate of the first conductivity type (for example, n-type), the diffusion layer 22 is formed under the same first conductivity type as the substrate 17. By making the well diffusion layer 18 of conductive type so that it does not exist under the insulating separation layer 21-2, it is possible to prevent false signals from diffusing in the well 18.

FIG. 5 shows another embodiment of the present invention in cross-section taken along the lines 1--5' in FIG. 23 is a false value signal charge diffusion prevention region (deep insulating separation layer) formed by etching a part of the well diffusion layer to create a groove, and then filling the groove with Sin using the increase in volume due to thermal oxidation. It is. The separation layer 23 in FIG. 5 differs from the separation layer 21 in FIG. 4 in that a well 18 is present in the separation region. The depth Xl of the isolation layer 23 may be deeper than the depth XW of the well 18.

FIG. 6(a) shows another embodiment of the present invention as shown in FIG.
This is shown in cross-sectional structure. 5 is a photodiode section, and 6 is a channel of a buried vertical COD.

17 is a semiconductor substrate of the first conductivity type, and 18-1 is a well diffusion layer of a conductivity type different from that of the substrate below the photodiode (for example, P
1.8-2 is a well diffusion layer below the vertical COD channel.

24 is a false value signal charge diffusion prevention region in which a groove is formed by etching a part of the well diffusion layer, and then the groove is filled with polycrystalline silicon to provide a second conductivity type relay property; This is a highly concentrated layer with a sufficiently higher impurity concentration than the above. 25 is 5i
If it's n2, it's 1. FIG. 6(a) shows that due to the potential barrier caused by the concentration difference between the diffusion prevention region 24 and the well, the signal charge 14 generated in the well 18-1 by the incident light is transmitted to the channel 6 of the vertical CCD as a false signal. The structure is designed to prevent contamination.

FIG. 6(b) is a potential diagram within the well indicated by the broken line in FIG. 6(a). The depth X of the diffusion prevention region 24 may be shallower than the depth XW of the well.

FIGS. 6(c) and 6(d) are examples of cross-sectional structures taken along line A-A' in FIG. 1. 26 is a high concentration diffusion layer of the same electric shock type as the well formed under the diffusion prevention region 24, and 27 is a diffusion layer of the same first conductivity type as the substrate formed under the diffusion prevention region 24. The high-concentration diffusion layer 26 shown in FIG. 6(C) is formed due to the concentration difference between the well and the diffusion layer 26 when the depth XJ of the diffusion prevention type 1:well 24 is shallower than the well depth Xw. It is adopted to enhance the false signal suppression effect by utilizing the potential barrier. The diffusion layer 27 shown in FIG. 6(d) is formed to prevent the presence of a second conductivity type well diffusion layer between the diffusion prevention region 24 and the semiconductor substrate 7. This has the effect of removing components that cause false signals by diffusing the well 18 below. Also,
The diffusion layer 27 may be of the same second conductivity type as the well diffusion layer 18.

The solid-state imaging device of the present invention can be manufactured by replacing the conventional isolation region forming step using selective oxidation with, for example, the following site signal charge diffusion prevention region forming step, or by using it in combination.

The diffusion prevention region 21 in the embodiment of FIG. 4 can be manufactured as follows. A second conductivity type impurity diffusion layer 18 on a first conductivity type semiconductor substrate (for example, n-type) 17,
An oxide film 28 and a silicon oxide film 29 are formed, and a photoresist 30 is applied (FIG. 7(a)). After forming the resist pattern, desired portions of the silicon oxide film 29 and the oxide film 28 are removed by etching. Anisotropic etching is performed using silicon nitride as a mask to form deep grooves (Figure 7(b))
. An oxide film 31 is formed in the groove, and a second conductivity type dense diffusion layer 32 as a channel stop is formed by ion implantation. After the silicon oxide film 29 is removed, a silicon oxide film 33 is laminated again, and the groove is filled with polycrystalline silicon 34 (FIG. 7(C)). A desired portion of the polycrystalline silicon is etched to planarize the surface, the surface of the polycrystalline silicon is oxidized to form a 5in935 layer, and the silicon nitride 33 in the active region is removed to complete the process of forming a deep isolation layer ( Figure 7(d)).

This is one of the element structures of the present invention. The separation region 23 shown in FIG. 5 can be manufactured as follows.

Diffusion layer of second conductivity type on semiconductor substrate 17 of first conductivity type]8
After forming a mask pattern 36 consisting of a 5 in 2 film by a well-known photoetching method, a silicon nitride film 37 is laminated and deposited (FIG. 8(a)). By anisotropic etching, only the silicon nitride film 37 deposited on the sides of the 5102 film 36 is left, and the silicon tinide film 37 deposited on other parts is removed, and an oxide film 38 is formed on the surface. (Figure 8(b)). The silicon nitride film 37 is removed and the exposed surface of the well diffusion layer is etched using a selected etching method to form a groove with an extremely narrow groove width of several μm in depth.
A groove 39 is formed (FIG. 8(C)). The oxide film on the surface was removed, and the inside of the trench was made 5 inches deep using the increase in volume due to thermal oxidation.
At step 240, the filling step and deep separation layer forming step are completed (FIG. 8(d)).

Thereafter, a solid-state image sensor is formed using conventional MO8 integrated circuit technology (FIG. 5).

The diffusion prevention region shown in FIG. 6, which is one of the device structures of the present invention, is formed by forming an oxide film 3 in the formation process shown in FIG. 7(c).
1 and the silicon nitride film 33, the deposited polycrystalline silicon 34 has a conductivity different from that of the substrate (for example, p-type).
It can be created by having

Although the above explanation has been made with reference to interline type CCD solid-state image sensing devices, frames 1 to 3, which are another type of CCD type, will be described without departing from the spirit of the present invention.
It is obvious that the present invention can also be applied to a Lancer-type CCD solid-state image sensor and an MO8-type solid-state image sensor.

〔Effect of the invention〕

As explained above, according to the present invention, smear, which is a drawback of solid-state image sensors, can be directly prevented by the false value signal charge diffusion prevention region, or by using the false value signal charge diffusion prevention region in combination with the diffusion prevention region. This can be prevented by a high concentration impurity layer formed in the above. A similar mechanism can also prevent cross-over, in which charges generated in a photoelectric conversion element are diffused and mixed into an adjacent photoelectric conversion element.

In addition, since the diffusion prevention region directly prevents smearing,
The smear suppression rate does not differ depending on the element, and the smear suppression effect does not decrease even if the pixel size is reduced. By employing the present invention, in addition to the above, many excellent secondary effects listed below can be obtained.

(1) Since element isolation by conventional selective oxidation is not performed, no narrow channel effect occurs, and the element isolation region can be reduced compared to the conventional M-structure.

(2) Due to the reduction in the isolation region mentioned in the previous section (1), the active region area increases and the vertical C
Since it becomes possible to expand the signal storage capacity of the CD and the photoelectric conversion unit, the dynamic range with respect to the incident current becomes larger. Furthermore, since it is less susceptible to the adverse effects of dark current, it becomes possible to obtain high-quality images even at high temperatures.

(3) Since there is no narrow channel effect mentioned in the previous section (1),
It becomes possible to reduce the channel width of the vertical COD without deteriorating the transfer efficiency. This leads to an increase in the number of picture elements (that is, an improvement in resolution) or an improvement in the aperture ratio (the area that captures light).

Furthermore, since the scale-down rule (size reduction side) can be directly applied to the device structure of the present invention, in the future, if the width of the false value signal charge diffusion prevention region (2 to 3 μm in the current technology) is reduced, Furthermore, resolution or aperture ratio can be improved.

[Brief explanation of the drawing]

Figures 1 and 2 are an example of the basic configuration and cross-sectional view of an interline type CCD solid-state image sensor, Figure 3 is a diagram showing a conventional element structure proposed for smear low frequency, and Figures 4 and 2 are 7 is a diagram showing one embodiment of the present invention and its manufacturing process diagram; FIGS. 5 and 8 are diagrams showing the structure of another embodiment of the present invention and its manufacturing process diagram; FIG. FIG. 3 is a diagram showing the structure of another embodiment of the invention. 5... Photodiode section, 6... CCD channel, 17... Semiconductor substrate, 18.18-2... Well diffusion layer, 21-1... Groove deeper than well, 21-2...
...A groove shallower than a well. Agent Patent Attorney Akio Takahashi 'f31 Not shown 2 Figure (b) l Tomi 3 Kuchihi 4 Figure ((L) '27g-z+zt-t-f-ttr-t→21-J←
/g-2-@Kudzu 4 Figure (C) (d) Figure 4 (e) Figure 5 Figure 2 (missing) Noil ll1g-z+24-←-/g-/ +212 +
/8'-2-'-1Figure 2 (C/) ly 7 Figure 3ρ Figure 3

Claims (1)

[Claims] (1) A group of photoelectric conversion elements that form a semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type, and extract optical information from the main surface of the semiconductor layer of the second conductivity type; In a solid-state imaging device that integrates a group of signal charge transfer elements that sequentially transfer optical signal charges accumulated in the elements, an insulating material or a semiconductor material is filled between the photoelectric conversion element group and the signal charge transfer element group. A solid-state imaging device characterized in that a groove is formed that is shallower or deeper than the second conductivity type semiconductor layer, and the groove prevents the diffusion of false signal charges. 2. In the solid-state imaging device according to claim 1, an impurity further contacts the first conductivity type semiconductor substrate under the groove or having a slight gap between the first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate. A solid-state imaging device characterized by providing a layer.