JPS60171736A - Examining device - Google Patents
Examining deviceInfo
- Publication number
- JPS60171736A JPS60171736A JP2716784A JP2716784A JPS60171736A JP S60171736 A JPS60171736 A JP S60171736A JP 2716784 A JP2716784 A JP 2716784A JP 2716784 A JP2716784 A JP 2716784A JP S60171736 A JPS60171736 A JP S60171736A
- Authority
- JP
- Japan
- Prior art keywords
- section
- inspection
- inspected
- wafer
- manual handling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体ウェーハにおける欠陥の検査に好適な検
査技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an inspection technique suitable for inspecting defects in semiconductor wafers.
IC,LSI等の半導体装置の製造工程において、半導
体基板(ウェーハ)に付着する塵埃等の異物や傷(以下
、欠陥という)は半導体装置の歩留りを決定する上で重
要な要因となる。このため、この種製造工程においては
ウェー・・の欠陥を検査し、これら欠陥の発生原因の除
却9発生レベルの監視を行なうことが要求され、このた
めの種々の欠陥検査装置が提供されている。In the manufacturing process of semiconductor devices such as ICs and LSIs, foreign matter such as dust and scratches (hereinafter referred to as defects) attached to semiconductor substrates (wafers) are important factors in determining the yield of semiconductor devices. Therefore, in this type of manufacturing process, it is required to inspect defects in the wafer, remove the causes of these defects, and monitor the level of occurrence, and various defect inspection devices are provided for this purpose. .
例えば、第1図は本発明者が開発した装置の一例であり
、被検査ウェーハ1を収納したカー) リッジ2と、検
査部3と、検査の終了したウェーハ4を収納するカート
リッジ5との間に夫々ベルト等のウェーハ搬送手段6を
設ける一方、検査部3にはウェーハの全面を走査するた
めの走査駆動系7を設けている。そして、検査部3には
欠陥とノイズとを判別する欠陥判定回路8を、また、走
査駆動系7には欠陥を検出したときのウェーハ位置を認
知するための座標割出し回路9を接続し、これらを合成
することにより作図器10では第2図に示すようにウェ
ーハ1上の欠陥Xの分布を表示し、カウンタ11では欠
陥数を表示することができる。For example, FIG. 1 shows an example of a device developed by the present inventor, in which a ridge 2 containing a wafer to be inspected 1, an inspection section 3, and a cartridge 5 containing a wafer 4 that has been inspected. A wafer transport means 6 such as a belt is provided in each of the wafers, and a scanning drive system 7 is provided in the inspection section 3 to scan the entire surface of the wafer. A defect determination circuit 8 for distinguishing between defects and noise is connected to the inspection section 3, and a coordinate indexing circuit 9 for recognizing the wafer position when a defect is detected is connected to the scanning drive system 7. By combining these, the plotter 10 can display the distribution of defects X on the wafer 1 as shown in FIG. 2, and the counter 11 can display the number of defects.
したがって、この検査装置では、カートリッジ2をセッ
トしておけばウェーッ\1はウェーハ搬送手段6によっ
て順序的に検査部3へ搬送され、ここで第2図の分布お
よび欠陥数が検査された後搬送手段6によりカートリッ
ジ5内に収納されて全ての検査が完了されることになる
。Therefore, in this inspection apparatus, once the cartridge 2 is set, the wafers \1 are sequentially conveyed to the inspection section 3 by the wafer conveying means 6, where the distribution and number of defects shown in FIG. 2 are inspected, and then the wafers are conveyed. It is housed in the cartridge 5 by means 6 and all inspections are completed.
しかしながら、この検査装置にあっては、ウェーハ上に
おける欠陥の数やその分布(座標位置)が検査できても
、これがウェーッ・上におけるいずれのチップの欠陥で
あるかは不明であり、このため各チップの良否の判定や
その不良率を直ちに検査することができないという問題
があることが本発明者によって明らか圧された。However, with this inspection equipment, even if the number of defects on the wafer and their distribution (coordinate positions) can be inspected, it is unclear which chip on the wafer this defect belongs to, and therefore each The inventor of the present invention has clearly recognized that there is a problem in that it is not possible to immediately determine whether a chip is good or bad or to inspect its defective rate.
また、前述の検査装置は、カートリッジ2内に収納され
ているウェーッーのみが検査される構成であり、したが
って1枚のみのウェー71の検査を行なう場合にはウェ
ーハをカートリッジ内に入れることが要求されて異物発
生(欠陥発生)の原因となり、また作業性の低下を招い
ている。更に前述の構成では、逆にみればカートリッジ
2内のウェーハ1は全て検査されることになるため、抜
取検査のように小数枚のウェーハのみを検査することが
できず、この点からも作業性は低下されるという問題が
あることが本発明者によって明らかにされた。Furthermore, the above-mentioned inspection apparatus is configured to inspect only the wafer stored in the cartridge 2, and therefore, when inspecting only one wafer 71, the wafer is required to be placed in the cartridge. This causes the generation of foreign matter (defect generation) and reduces workability. Furthermore, in the above-mentioned configuration, since all the wafers 1 in the cartridge 2 are inspected, it is not possible to inspect only a small number of wafers as in the case of sampling inspection, and from this point of view, the work efficiency is also reduced. The inventors have discovered that there is a problem in that the
本発明の目的はウェーハにおける欠陥がいずれのチップ
上に存在しているかを検査できかつこれから不良チップ
更にはその不良率等を直ちに検査することのできる検査
技術を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an inspection technique that can inspect which chips on a wafer have defects and can immediately inspect defective chips and their defective rate.
また本発明の他の目的は全数、抜取り、1枚のみの各検
査を行なうことができ、これにより検査作業性の向上を
図ることのできる検査技術を提供することにある。Another object of the present invention is to provide an inspection technique that can perform inspections on all items, samples, and only one sheet, thereby improving inspection workability.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
〔発明の概要J
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Summary of the Invention J A brief overview of typical inventions disclosed in this application is as follows.
すなわち、被検査面上における欠陥位置情報と、この被
検査面を区分して形成される物の区分情報とを併合し得
るよう構成することにより、区分して形成される物にお
ける欠陥の有無が検査でき、これにより各々の物の良否
や不良率を直ちに検査することができる。In other words, by merging the defect position information on the surface to be inspected and the classification information of the object formed by dividing the surface to be inspected, it is possible to determine the presence or absence of defects in the object formed by dividing the surface to be inspected. This makes it possible to immediately check the quality and defective rate of each item.
また、被検査物の供給部、検査部および収納部の搬送路
上に手動取扱い部およびバイパス路を設けることにより
、必要な被検査物のみ或いは手動取扱い部に供給された
物のみを検査部に搬送でき、これにより不要な検査を省
略し、欠陥の新たな発生の防止や作業性の向上を達成す
ることができる。In addition, by providing a manual handling section and a bypass path on the conveyance path of the supply section, inspection section, and storage section for inspection objects, only the necessary inspection objects or only those supplied to the manual handling section can be transported to the inspection section. This makes it possible to omit unnecessary inspections, prevent new defects from occurring, and improve workability.
第3図ないし第5図は本発明の検査装置の一実施例を示
し、第3図において12は内部に被検査物としてのウェ
ーハ11を収納したローダ側のカートリッジ、13は検
査の終了した(検査を行なわなかった物も含む)ウェー
ッ・14を収納するアンローダ側のカートリッジであり
、これらの両カ−トリツク12.13は若干の距離をお
いて同一方向に向けて並置している。前記ローダ側のカ
ートリッジ12の前方位置にはウェーハ表面の欠陥を検
査するための検査部15を設け、これにはウェーハを走
査してその座標情報を取り出す走査駆動系16を付設し
ている。そして、前記ローダ側カー) IJソジ12ど
検査部15との間にベルト構造の搬送往路17を延設し
、また検査部15とアンローダ側カートリッジ130間
にL字型の搬送復路18を延設している。これらの搬送
往路17と搬送復路18は夫々矢印A、B方向にのみ移
動される。更に、前記搬送往路17の中間一部には手動
取扱い部(ステーション)19を形成し、この手動取扱
い部19と前記搬送復路18との途中とをバイパス路2
0で接続している。このバイパス路20も同様にべy)
構造として構成されるが、その操作により矢印C,,C
,の両方向に切換移動できる。3 to 5 show an embodiment of the inspection apparatus of the present invention. In FIG. 3, 12 is a cartridge on the loader side that houses a wafer 11 as an object to be inspected, and 13 is a cartridge after the inspection has been completed. This is a cartridge on the unloader side that stores wafers 14 (including those that were not inspected), and both of these cartridges 12 and 13 are placed side by side with a slight distance between them facing the same direction. An inspection section 15 for inspecting defects on the wafer surface is provided at a position in front of the cartridge 12 on the loader side, and is equipped with a scanning drive system 16 for scanning the wafer and extracting its coordinate information. Then, an outbound conveyance path 17 having a belt structure is extended between the loader-side car) IJ straightener 12 and the inspection section 15, and an L-shaped return conveyance path 18 is extended between the inspection section 15 and the unloader-side cartridge 130. It is set up. These forward transport path 17 and return transport path 18 are moved only in the directions of arrows A and B, respectively. Further, a manual handling section (station) 19 is formed in an intermediate part of the forward transport path 17, and a bypass path 2 is formed between this manual handling section 19 and the intermediate portion of the return transport path 18.
Connected with 0. Similarly, this bypass path 20)
It is configured as a structure, but its operation causes arrows C,,C
, can be switched in both directions.
前記手動取扱い部19および、18.20搬送路交点部
(以後、この部分の詳細説明は省略)は第4図(4)に
模式図を示すように、前記搬送往路17を構成する平行
べ/7)21.21の一方を複数個のプーリ22によっ
て凹状に通し、ここにバイパス路20を構成する平行ベ
ル)23.23の一端部をプーリ24と共に位置させる
。そして、このプーリ24の支軸25を上下動ソレノイ
ド26等に連結し、平行ベルト23を上下動させ得るよ
うにする。また、搬送往路17の平行ベルト21.21
間には上端に小径の載置台27を固着した支持ロッド2
8を垂直方向に立設し、上下動シリンダ29等によって
上下動させ得るようにしている。The manual handling section 19 and the transport path intersection section 18.20 (detailed explanation of this part will be omitted hereinafter) are connected to the parallel plate that constitutes the forward transport path 17, as shown in a schematic diagram in FIG. 4 (4). 7) One of the parallel bells 21 and 21 is passed through a plurality of pulleys 22 in a concave shape, and one end of the parallel bell 23 and 23 constituting the bypass path 20 is positioned together with the pulley 24. The spindle 25 of this pulley 24 is connected to a vertically moving solenoid 26, etc., so that the parallel belt 23 can be moved vertically. In addition, the parallel belts 21 and 21 of the outward conveyance path 17
In between is a support rod 2 with a small-diameter mounting table 27 fixed to its upper end.
8 is vertically installed and can be moved up and down by a vertical movement cylinder 29 or the like.
したがって、この手動取扱い部19では、バイパス路2
0の平行ベルト23および載置台27が図示のように下
動位置にあるときにはウェーハ11は搬送往路17のベ
ル)21.21によって図示左方(極査部15に向って
)に搬送される。Therefore, in this manual handling section 19, the bypass path 2
When the parallel belt 23 and the mounting table 27 are in the downward movement position as shown in the figure, the wafer 11 is conveyed to the left in the figure (towards the pole section 15) by the bells 21 and 21 of the forward conveyance path 17.
また、同図仮想線のように載置台27を上動した上でこ
こに1枚のウェーハ11を載置し、これを再び下動すれ
ば該ウェーハ11は搬送往路17のベル)21.21に
移載されて同様に左方へ搬送される。更に、同図0のよ
うに、バイパス路20のベルト23を上動したときには
、図示右方から搬送往路17のベル)21.21上を搬
送されてきたウェーハはバイパス路20のベル)23.
23に移載され、バイパス路上を前記矢印C8方向に移
動される。In addition, if the mounting table 27 is moved upward as shown by the imaginary line in the figure and one wafer 11 is placed there, and then moved downward again, the wafer 11 will be transferred to the bell (21.21) of the forward transport path 17. It is then transferred to and similarly transported to the left. Furthermore, when the belt 23 of the bypass path 20 is moved upward as shown in FIG.
23 and moved along the bypass road in the direction of the arrow C8.
一方、前記検畳部15には欠陥信号とノイズ信号とを判
別する欠陥判定回路30を接続し、また走査駆動系16
には欠陥を検出したときのウェーハ位置を認知するため
の座標割出し回路31を接続している。そして、これら
欠陥判定回路30と座標割出し回路31は信号合成回路
32に接続し、更に作図器33に接続している。なお、
欠陥判定回路30は欠陥数表示カウンタ34にも接続し
ており、また信号合成回路32にはウェーハサイズやチ
ップサイズ等の入力部35およびこの入力信号によりウ
ェーハ上におけるチップ配列を情報として出力するチッ
プ配列回路36を接続している。On the other hand, a defect determination circuit 30 for discriminating between a defect signal and a noise signal is connected to the detection section 15, and a scanning drive system 16 is connected to the detection section 15.
A coordinate indexing circuit 31 for recognizing the wafer position when a defect is detected is connected to the wafer. These defect determination circuit 30 and coordinate indexing circuit 31 are connected to a signal synthesis circuit 32 and further connected to a plotter 33. In addition,
The defect determination circuit 30 is also connected to a defect number display counter 34, and the signal synthesis circuit 32 has an input section 35 for inputting wafer size, chip size, etc., and a chip that outputs the chip arrangement on the wafer as information based on this input signal. An array circuit 36 is connected thereto.
以上の構造によれば、搬送往路17から検査部15に移
動されたウェーッS11は検査部15において全面走査
され、存在する欠陥情報が欠陥判定回路30から、また
このときの座標情報が座標割出し回路31から夫々信号
合成回路32に出力される。このとき、カウンタ34に
は欠陥数が表示される。一方、これと同時に入力部35
およびチップ配列回路36からは検査されるウェーッ・
11のウェーハサイズやチップサイズ等の情報が信号合
成回路32に入力される。これにより、信号合成回路3
2ではこれらの全ての情報に基づいて、ウェーハ11の
チップ区分、欠陥分布等を作図器33において作図させ
る。この結果、第5図に示すようなチップlla区分と
その上に分布された欠陥Xが表示されることになり、し
たがって各チップの良否および不良チップ数(不良率)
を直ちに検査することができる。According to the above structure, the entire surface of the wafer S11 moved from the forward transport path 17 to the inspection section 15 is scanned in the inspection section 15, and the existing defect information is sent from the defect determination circuit 30, and the coordinate information at this time is used as the coordinate index. Each signal is output from the circuit 31 to a signal synthesis circuit 32. At this time, the number of defects is displayed on the counter 34. Meanwhile, at the same time, the input section 35
and the waveform to be tested from the chip array circuit 36.
Information such as the wafer size and chip size of No. 11 is input to the signal synthesis circuit 32. As a result, the signal synthesis circuit 3
In Step 2, the chip classification, defect distribution, etc. of the wafer 11 are plotted by the plotter 33 based on all of this information. As a result, the chip lla classification and the defects X distributed on it are displayed as shown in Figure 5, and therefore the quality of each chip and the number of defective chips (defective rate) are displayed.
can be inspected immediately.
ところで、ローダ側のカートリッジ12内のウェーハを
全数検査する場合には、第4図囚のようにバイパス路2
0および載置台27を下動位置に保てば、ウェーハ11
は全て搬送往路17から検査部15に至り、更にここか
ら搬送復路1Bを通ってアンローダ側のカートリッジ1
3内に収納されることになる(、第3図矢印S)。By the way, when inspecting all the wafers in the cartridge 12 on the loader side, the bypass path 2 is
0 and the mounting table 27 in the downward movement position, the wafer 11
All of them reach the inspection section 15 from the forward transport path 17, and further pass through the return transport path 1B to the cartridge 1 on the unloader side.
3 (arrow S in Figure 3).
一方、カートリッジ12内のウェーハな抜取り検査する
場合には、搬送往路17を移動されるウェーハのタイミ
ングに合わせてバイパス路2oのベルト23を第4図■
のように上動すればよい。On the other hand, when performing a sampling inspection of wafers in the cartridge 12, the belt 23 of the bypass path 2o is moved in accordance with the timing of the wafer being moved on the forward transport path 17 as shown in FIG.
All you have to do is move up like this.
これにより、以後搬送往路17を通って手動取扱い部1
9を通過しようとするウェーハはベルト23.23に移
載され、バイパス路2oを通って搬送復路18へと移動
され、検査を行なうことなくカートリッジ13内に収納
される(第3図矢印R)。As a result, the manual handling section 1
The wafer passing through the wafer 9 is transferred to the belt 23, 23, is moved to the return path 18 through the bypass path 2o, and is stored in the cartridge 13 without being inspected (arrow R in FIG. 3). .
更に、1枚のウェーハのみを検査する場合には、第4図
(2)の仮想線のように載置台27を上動させかつこの
上にウェーハ11を載置した後にこれを下動させる。こ
れにより、ウェーハ11は搬送往路17により検査部1
5へ搬送される。これと同時に、バイパス路20は矢印
Ctのように反対方向に移動させておき、検査の終了し
たウェーハが搬送路18とバイパス路20の交点に来た
とき、搬送路18を上動すれば搬送復路18からバイパ
ス路20を通して手動取扱い部19に返送されてくる(
第3図矢印T)。Furthermore, when only one wafer is to be inspected, the mounting table 27 is moved upward as shown by the imaginary line in FIG. 4(2), and after the wafer 11 is placed thereon, it is moved downward. As a result, the wafer 11 is transferred to the inspection section 1 by the forward transport path 17.
5. At the same time, the bypass path 20 is moved in the opposite direction as indicated by the arrow Ct, and when the inspected wafer comes to the intersection of the transport path 18 and the bypass path 20, the wafer is moved up the transport path 18 and transferred. It is returned from the return route 18 to the manual handling section 19 through the bypass route 20 (
Figure 3 arrow T).
以上の作用を検査目的に応じて切換ることにより、夫々
最適な検査を行なうことができ、各検査における作業性
の向上を達成することができる。By switching the above-mentioned functions according to the inspection purpose, each inspection can be performed optimally, and workability in each inspection can be improved.
(1)ウェーハにおける欠陥位置(座標)情報と、ウェ
ーハにおけるチップ区分情報とを合成し得るよう構成し
、区分されたチップ上における欠陥の分布を検出できる
ように構成しているので、各チップの良否はもとよりチ
ップの不良数や不良率を直ちに検査することができる。(1) It is configured to combine defect position (coordinate) information on the wafer and chip classification information on the wafer, and is configured to detect the distribution of defects on the classified chips. It is possible to immediately inspect not only the quality of chips but also the number of defective chips and the defective rate.
(2) ウェーハのローダ位置と検査部を結ぶ搬送往路
上に手動取扱い部を設ける一方、検査部とアンローダ位
置を結ぶ搬送復路と搬送往路とにわたってバイパス路を
形成しているので、必要なりニームのみ或いは手動取扱
い部に供給されたウェーハのみを検査することができ、
抜取検査や1枚検査の検査作条性を向上することができ
る。(2) A manual handling section is provided on the forward transport path that connects the wafer loader position and the inspection section, while a bypass path is formed across the return transport path and the forward transport path that connect the inspection section and unloader position. Alternatively, only wafers fed to the manual handling section can be inspected;
Inspection processability for sampling inspection and single-sheet inspection can be improved.
(3)1枚検査では、ウェーハを手動取扱い部上に載置
するだけでよいので、カートリッジ等にセットする必要
もなく、新たな欠陥の発生を防止できる。(3) In single-wafer inspection, it is only necessary to place the wafer on the manual handling section, so there is no need to set the wafer in a cartridge or the like, and new defects can be prevented from occurring.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、搬送路を構
成するベルト手段に代えて順送り機構(ステップ機構)
を利用し【もよい。また、手動取扱い部は平面方向の方
向変換機構造であってもよい。更に搬送路は立体的な構
造であってもよい。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, instead of the belt means that constitutes the conveyance path, a progressive mechanism (step mechanism) is used.
Use [mayoi]. Further, the manual handling section may have a planar direction changer structure. Furthermore, the conveyance path may have a three-dimensional structure.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体ウェーハにお
ける欠陥検査装置に適用した場合について説明したが、
それに限定されるものではなく、たとえばホトマスクの
欠陥検査やその他の物、特に検査物を後に複数区分で切
離すような物の検査装置に適用することができる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to a defect inspection device for semiconductor wafers, which is the background field of application.
The present invention is not limited thereto, and can be applied to, for example, defect inspection of photomasks and other objects, especially those in which the object to be inspected is later separated into multiple sections.
第1図は本発明者が開発した装置の平面構成図、第2図
は欠陥分布を作図した図、
第3図は本発明の検査装置の平面構成図、第4図囚、■
は手動取扱い部の概略構、成図、第5図は本発明装置に
よる欠陥分布の作図である。
11−・・ウェーハ、11a=・チップ、12・・・カ
ートリッジ(ローダ側)、13・・・カートリッジ(ア
ンローダ側)、15・・・検査部、16・・・走査駆動
系、17・・・搬送往路、18・・・搬送復路、19・
・・手動取扱い部、20・・・バイパス路、30・・・
欠陥判定回路、31・・・座標割出し回路、32・・・
信号合成回路、33・・・作図器、34・・・カウンタ
、35・・・入力部、36・・・チップ配列回路。Fig. 1 is a plan configuration diagram of the device developed by the present inventor, Fig. 2 is a diagram plotting defect distribution, Fig. 3 is a plan configuration diagram of the inspection device of the present invention, and Fig. 4
5 is a diagram showing the schematic structure of the manual handling section, and FIG. 5 is a drawing of defect distribution by the apparatus of the present invention. DESCRIPTION OF SYMBOLS 11--Wafer, 11a=-chip, 12--cartridge (loader side), 13--cartridge (unloader side), 15--inspection section, 16--scanning drive system, 17-- Conveyance outward route, 18... Conveyance return route, 19.
...Manual handling section, 20...Bypass path, 30...
Defect determination circuit, 31... Coordinate indexing circuit, 32...
Signal synthesis circuit, 33... Plotter, 34... Counter, 35... Input section, 36... Chip array circuit.
Claims (1)
置情報を検出する手段と、前記被検査物を後に複数個の
領域又は部分に区分する区分情報を出力する手段と、前
記位置情報検出手段と区分情報出力手段の各情報を合成
し、かつ被検査物の表面に対応して欠陥分布と区分とを
合わせて作図表示する手段とを備えることを特徴とする
検査装置。 2、 ウェーハ表面の欠陥位置情報を検出する欠陥判定
回路および座標割出し回路と、ウェーハ上におけるチッ
プのチップ配列を出力するチップ配列回路と、これらの
各出力情報を合成する信号合成回路および作図器を有す
る特許請求の範囲第1項記載の検査装置。 3、被検査物のローダ部、検査部およびアンローダ部の
間を夫々搬送路で連絡してなる検査装置であって、前記
ローダ部と検査部の間の搬送往路中に被検査物を手動で
セット可能な手動取扱い部を設けると共に、この手動取
扱い部と前記検査部。 アンローダ部間の搬送復路との間にバイパス路を延設し
たことを特徴とす、る検査装置。 4、手動取扱い部はローダ部の被検査物を検査部又はバ
イパス路のいずれかに搬送方向を切換でき、またその上
にセットされた被検査物を検査部に向けて搬送し得るよ
う構成してなる特許請求の範囲第3項記載の検査装置。 5、バイパス路は正、逆方向に移動でき、手動取扱い部
に移動されて来た被検査物を前記搬送復路に搬送し或い
は搬送復路の被検査物を前記手動取扱い部に返送し得る
よう構成してなる特許請求の範囲第3項又は第4項記載
の検査装置。[Scope of Claims] 1. Means for detecting positional information of the object to be inspected, such as defects, on the inspection surface of the inspected object, and outputting classification information for later dividing the inspected object into a plurality of regions or parts. and a means for synthesizing each piece of information from the position information detecting means and the classification information outputting means, and plotting and displaying the defect distribution and classification together corresponding to the surface of the object to be inspected. Inspection equipment. 2. A defect determination circuit and coordinate indexing circuit that detect defect position information on the wafer surface, a chip array circuit that outputs the chip array of chips on the wafer, and a signal synthesis circuit and plotter that synthesizes each of these output information. An inspection device according to claim 1, having: 3. An inspection device in which a loader section, an inspection section, and an unloader section of an object to be inspected are connected through a conveyance path, and the object to be inspected is manually transferred during the outward transportation path between the loader section and the inspection section. A settable manual handling part is provided, and the manual handling part and the inspection part. An inspection device characterized in that a bypass path is provided between the unloader section and the return path. 4. The manual handling section is configured to be able to switch the conveyance direction of the object to be inspected in the loader section to either the inspection section or the bypass path, and to convey the object to be inspected set thereon toward the inspection section. An inspection device according to claim 3 comprising: 5. The bypass path is configured to be able to move in the forward and reverse directions, and is capable of transporting the object to be inspected that has been moved to the manual handling section to the return path, or returning the object to be inspected on the return path to the manual handling section. An inspection device according to claim 3 or 4, which comprises:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59027167A JPH0669060B2 (en) | 1984-02-17 | 1984-02-17 | Inspection equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59027167A JPH0669060B2 (en) | 1984-02-17 | 1984-02-17 | Inspection equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60171736A true JPS60171736A (en) | 1985-09-05 |
JPH0669060B2 JPH0669060B2 (en) | 1994-08-31 |
Family
ID=12213495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59027167A Expired - Lifetime JPH0669060B2 (en) | 1984-02-17 | 1984-02-17 | Inspection equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0669060B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0344054A (en) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | Inspection system and electronic device manufacturing method |
US5210041A (en) * | 1990-07-24 | 1993-05-11 | Hitachi, Ltd. | Process for manufacturing semiconductor integrated circuit device |
US6404911B2 (en) | 1989-07-12 | 2002-06-11 | Hitachi, Ltd. | Semiconductor failure analysis system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5555206A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Electronics Eng Co Ltd | Inspection data processing system for defect on face plate |
JPS55111135A (en) * | 1979-02-19 | 1980-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
JPS5759353U (en) * | 1980-09-27 | 1982-04-08 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5658052A (en) * | 1978-07-28 | 1981-05-20 | Toray Industries | Artificial leather |
-
1984
- 1984-02-17 JP JP59027167A patent/JPH0669060B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5555206A (en) * | 1978-10-20 | 1980-04-23 | Hitachi Electronics Eng Co Ltd | Inspection data processing system for defect on face plate |
JPS55111135A (en) * | 1979-02-19 | 1980-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
JPS5759353U (en) * | 1980-09-27 | 1982-04-08 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0344054A (en) * | 1989-07-12 | 1991-02-25 | Hitachi Ltd | Inspection system and electronic device manufacturing method |
JP2941308B2 (en) * | 1989-07-12 | 1999-08-25 | 株式会社日立製作所 | Inspection system and electronic device manufacturing method |
US6185322B1 (en) | 1989-07-12 | 2001-02-06 | Hitachi, Ltd. | Inspection system and method using separate processors for processing different information regarding a workpiece such as an electronic device |
US6330352B1 (en) | 1989-07-12 | 2001-12-11 | Hitachi, Ltd. | Inspection data analyzing system |
US6339653B1 (en) | 1989-07-12 | 2002-01-15 | Hitachi, Ltd. | Inspection data analyzing system |
US6404911B2 (en) | 1989-07-12 | 2002-06-11 | Hitachi, Ltd. | Semiconductor failure analysis system |
US6529619B2 (en) | 1989-07-12 | 2003-03-04 | Hitachi, Ltd. | Inspection data analyzing system |
US6628817B2 (en) | 1989-07-12 | 2003-09-30 | Hitachi, Ltd. | Inspection data analyzing system |
US5210041A (en) * | 1990-07-24 | 1993-05-11 | Hitachi, Ltd. | Process for manufacturing semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
JPH0669060B2 (en) | 1994-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101804331B1 (en) | Linear inspection system | |
TW452915B (en) | Method of sorting and investigating automatic semiconductor wafer with extended optical inspection and apparatus for implementing the same | |
JPH0476472A (en) | Ic inspection device | |
KR101777547B1 (en) | The equipment and method for semiconductor PCB(Printed Circuit Board) inspection | |
JP2009250971A (en) | System and method for inspecting electronic device | |
JP2012228638A (en) | Mounted chip test/selection device | |
EP2105216B1 (en) | Inspecting apparatus with eddy current inspection | |
JP2002188999A (en) | Foreign matter / defect detection device and detection method | |
JPS60171736A (en) | Examining device | |
TW201033600A (en) | System and processing of a substrate | |
CN114535116A (en) | Visual detection device | |
JP2012073155A (en) | Magnetic disk inspection device and inspection method | |
JP2001050907A (en) | Method for inspecting substrate | |
KR200441696Y1 (en) | Strip inspection device for semiconductor device manufacturing | |
CN101339146A (en) | Automatic optical detection device | |
JPH11121579A (en) | Carriage system for semiconductor wafer | |
JP2002113427A (en) | Device for testing fine object | |
TW200848722A (en) | Automatic optical inspection device | |
CN111474180A (en) | Detection data concatenation system and method | |
JPH10197231A (en) | Appearance inspection device | |
JP2009025004A (en) | Inspection device and method for plane substrate | |
JPH0557254A (en) | Method for classifying glass plate | |
CN217017474U (en) | Screening mechanism and production equipment | |
CN212384099U (en) | An automatic online testing machine for circuit board production | |
JPS62119404A (en) | Appearance inspecting device |