JPS6017131B2 - memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention specifically provides that addresses are allocated in byte units,
The present invention relates to a memory control circuit suitable for a processing device equipped with a memory in which memory access is performed in units of 2 bytes or more.

For example, in a processing device that can issue/write data in 2-byte units, addresses are generally assigned to memory by assigning an even number of addresses to every 2 bytes, as shown in Figure 1a. 3 lower bytes of
address, ... is the lower byte of the address (N is a positive integer) 2N+
This is done by assigning addresses like address 1.

In this case, for example, the operation of reading 2 bytes (even number, odd number bare) at address 2 can be performed in one memory cycle. On the other hand, to read 2 bytes at consecutive addresses, the first
For example, as shown in Figure b, the 2 bytes at addresses 3 and 4 (
(odd number, even number bear), two memory cycles are required. That is, by first reading the lower byte at address 2 of memory 1 and holding it in the upper byte of register 2, then reading the upper byte of address 4 of memory 1 and holding it in the lower byte of register 2,
2 bytes are read. In such a case, it is necessary to increment the memory address by 1 after the first read to prepare for the second read. By the way, in order to increment the memory address, conventionally an adder 3 is provided as shown in FIGS.

'2} Use the arithmetic circuit included in the processing device.

Such methods were used. However, the method (1} has the disadvantage that the amount of hardware increases and the device becomes expensive. Also, the method {21} requires a microprogram to operate the arithmetic circuit, and because of this program processing, There was a drawback that the address increment was delayed and the memory access speed was slow.In other words, both of the above methods [1] and (2) are not sufficiently effective for memory usage that exceeds the memory address boundary. I couldn't say yes.
The present invention has been made in view of the above circumstances, and its purpose is to:
An object of the present invention is to provide a memory control circuit that can perform memory access across memory address boundaries with a small hardware configuration and at high speed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Note that this embodiment is implemented in a processing device equipped with a memory in which addresses are allocated in byte units and memory access is performed in 2-byte (HALFWORD) units. FIG. 3 is a block diagram showing the configuration of a memory control circuit of the present invention applied to such a processing device. In the figure, 11 is a memory address register for holding memory address information for a memory (not shown). This memory address register 11 has at least an up-counting function, and its contents are incremented by 11 by receiving a count-up signal CU from an address control circuit 14, which will be described later. 12 is the information of the least significant bit of this memory address register 1 and the mode signal M
This is an AND gate that inputs ODE and an end signal ENDI.

This mode signal MODE is a signal that becomes valid (logic "1") in the 2-byte unit access mode. Note that the end signal ENDI is a signal output from a memory activation circuit 15, which will be described later. 13 is a flip-flop (hereinafter referred to as F
(referred to as F).

The FF 13 uses the output of the AND gate 12 as a set (S) input, and uses the end signal END2 as a reset (R) input.
This end signal END2 is a signal output from a memory activation circuit 15, which will be described later. 14 is an address control circuit.

The address control circuit 14 is configured to output a count up signal CU in response to the set output of the FF 13. Further, 15 is a memory activation circuit. The memory starting circuit 15 is configured to output a memory start signal START for starting the memory, regardless of whether the memory is accessed by an even number, an odd number bear, or an odd number or an even number bear. Furthermore, the memory activation circuit 15
The memory start signal START is also outputted again in response to the set output of the FF 13. Furthermore, the memory activation circuit 15 is configured to output an end signal ENDI at the end of the first memory cycle, and output an end signal END2 at the end of the second memory cycle. Next, the operation of the configuration shown in FIG. 3 will be explained with reference to the timing chart shown in FIG.

For example, assume that the memory address register 1 holds a memory address indicating an odd number, for example, address 3 (see Figure 4), and the mode signal MODE for instructing the AND gate 12 to access the 2-byte unit access mode. At this time, the memory start signal START is outputted from the memory start circuit 15 as shown in the tree in FIG. As explained using b, in the first memory cycle (Fig. 4a),
For example, one byte at address 3 (lower byte at address 2) in a memory (not shown) is read out. Then, at the end of the first memory cycle, the fourth
As shown in the figure, an end signal ENDI is output.

This end signal ENDI is input to AND gate 12. This AND gate 12 receives the mode signal MOD described above.
In addition to E, information on the least significant bit of the memory address register 11 is input. In this case, the content of the memory address register 11 is address 3, ie, an odd address, and therefore the information of the least significant bit is logic "1". Therefore, at the input timing of the end signal ENDI, the AND condition of the AND gate 12 is satisfied, and the AND gate 12 outputs a signal of logic "1". That is, the AND gate 12 determines at the end of the first memory cycle that this is an odd or even bear access, or in other words, a memory access that crosses an address boundary. As is clear, the AND condition of AND gate 12 is satisfied in the case of access in units of bytes (byte access), in the case of even and odd bare accesses, that is, in the case of memory accesses that do not cross address boundaries. There's nothing to do. The FF 13 is set by the logic "1" output of the AND gate 12, and its FF output (Q output) transitions from logic "0" to logic "1" as shown in FIG. 4-2.

Then, in response to the set output of the FF 13, the memory start signal START is output again from the memory start circuit 15 as shown in FIG. 4E.

This activates the memory and starts the second memory cycle. Similarly, in response to the set output of the FF 13, the address control circuit 14 outputs a count up signal CU as shown in FIG. This count up signal CU is applied to memory address register 1.
This causes the contents of the memory address register 11 to be incremented by 11. That is, the contents of memory address register 1 (memory address) are incremented from address 3 to address 4 as shown in FIG. Then, based on the contents of memory address register 1, as explained using FIG. 1b, in the second memory cycle (FIG. (upper byte of) is read. Note that in both the first and second times, the read data is shifted by one byte and taken into the register (memory data register) as shown in FIG. Further explanation will be omitted. According to this embodiment, it is possible to deal with memory accesses that cross address boundaries without requiring a special hardware configuration such as an adder.

Moreover, in this embodiment, since the memory address is incremented without using microprogram processing, the address increment is performed at high speed when moving to the second memory cycle, and therefore high-speed memory access is possible. Become. Note that the FF 13 receives the end signal END2 (fourth
(c) is reset as shown in FIG. 4(b). Next, other embodiments of the present invention will be described.

FIG. 5 is a block diagram showing another embodiment of the memory control circuit of the present invention, and the same parts as those in FIG. 3 are given the same reference numerals and their explanation will be omitted. In the figure, 111 is a memory address register having an up-counter function. This memory address register 111 increments its contents by 11 when a count-up signal CU is input from an address control circuit 114, which will be described later. When the countdown signal CD is input from the address control circuit 114, its contents are incremented by 1. 114 is an address control circuit. The address control circuit 114 responds to the set output of the FF 13. In addition to outputting a count up signal CU, a count down signal CD is also output in response to the reset output of the FF 13.Next, the operation of the configuration shown in FIG. 5 will be briefly explained with reference to the flowchart shown in FIG. explain.

In FIG. 6, I to I in FIG. 6 are the same as I to I in FIG. 4. That is, the difference in operation between the configurations of FIG. 3 and FIG. 5 is the difference in operation at the time of resetting the FF 13, in other words, at the end of the second memory cycle. In FIG. 5, when the second memory cycle is completed, the third
FF13 is reset in the same way as in the case shown in the figure (Fig. 6, 2).
. Then, in response to the reset output of the FF 13, the address control circuit 114 outputs a countdown signal CD as shown in FIG. 6 (this is the difference from FIG. 3). This countdown signal CD is input to the memory address register 11, and thereby the contents of the memory address register 11 (memory address indicating address 4)
is reduced by -1. That is, at the end of the second memory cycle, in other words, at the end of odd and even bear access, the contents (memory address) of the memory address register 111 change from address 4 to address 3 (
The memory address (ie, the initial value) at the time of the first memory cycle is returned. In this way, according to the present embodiment, the memory address register 11 is changed after the second memory cycle is completed, without using a special hardware configuration such as a subtracter, and without performing subtraction processing by a microprogram.
The contents of can be returned to the memory address value at the first memory cycle at high speed.

In other words, the case where memory access of odd numbers and even bears is performed as shown in FIG.
There is a demand to be able to handle microprograms in the same way. For this purpose, since the contents of the memory address register are not updated in corner number and odd bear memory accesses, the contents of the memory address register are decremented by 1 after the second memory cycle in odd and even bear memory accesses. The memory address must be returned to the memory address at the first memory cycle. On the other hand, conventionally, a subtracter is provided to reduce the value by 1, or an arithmetic circuit within the processing device is used.
There was a way to set the value to -1 through microprogram processing. However, the former has the drawback of increasing the amount of hardware and is expensive, and the latter has the drawback of slow processing speed.
In contrast to the conventional means having such drawbacks, the configuration shown in FIG.
Since the contents of the memory address register 111 can be returned to the initial value at high speed, it can be handled similarly in microprogram processing without sacrificing processing speed.

Furthermore, it goes without saying that the configuration shown in FIG. 5 can also exhibit the effects obtained with the configuration shown in FIG. 3. In the above embodiment, the case of memory access in units of 2 bytes (HALFWORD) was explained, but according to the gist of the present invention, it can be easily applied to memory access in units of 4 bytes (FULLWORD), for example. Of course.

In this case, unlike the previous embodiment, it is necessary to input the OR output of the lower two bits of the memory address registers 11 and 111 to the AND gate 12. As described in detail above, according to the memory control circuit of the present invention, memory IJ access across memory address boundaries can be performed at high speed with a small hardware configuration.

[Brief explanation of the drawing]

Figures 1a and b are diagrams showing a general address allocation and access method for memory, Figure 2 is a diagram showing a conventional address increment circuit for memory access across address boundaries, and Figure 3 is a diagram showing the present invention. FIG. 4 is a timing chart for explaining the operation of the above embodiment, and FIG. 5 is a block diagram showing another embodiment of the memory control circuit of the present invention. FIG. 6 is a timing chart for explaining the operation of the other embodiment described above. 4, 11, 111...Memory address register, 12...And gate (discrimination circuit), 13...Flip-flop (FF), 1
4,114...address control circuit, 15...memory activation circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. A memory address register that holds memory address information for the memory and has at least an up counter function, and a memory address register that stores memory address information and information indicating the data width of the memory access when the first memory access is completed. a determining means for determining whether or not the memory access exceeds the address boundary based on the determination means; and when the determining means determines that the memory access exceeds the address boundary, the memory address register is configured according to the output of the determining means. an address control circuit that updates the address value of the memory, and outputs a signal for performing a second memory activation in accordance with the output of the discrimination means when the discrimination means judges that the memory access exceeds the address boundary. A memory control circuit comprising a memory activation circuit. 2. The memory address register is configured with a counter having an up-down function, and when the second memory access is completed, the memory address control circuit converts the address value of the memory address register back to the original address according to the output of the determining means. 2. The memory control circuit according to claim 1, wherein the memory control circuit updates to a value.