JPS60170856U - Microprocessor board test equipment - Google Patents
Microprocessor board test equipmentInfo
- Publication number
- JPS60170856U JPS60170856U JP5951684U JP5951684U JPS60170856U JP S60170856 U JPS60170856 U JP S60170856U JP 5951684 U JP5951684 U JP 5951684U JP 5951684 U JP5951684 U JP 5951684U JP S60170856 U JPS60170856 U JP S60170856U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- test equipment
- oven
- switches
- board test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に適用される一実施例の試験装置の略図
である。第２図は試験装置に備えられるスイッチの構成
図及び結線図の一例である。
第１図において、１・・・スイッチ台、２・・・ＩＣソ
ケット、３・・・スイッチ台とＩＣソケットの接続線、
４・・・アドレス信号設定のスイッチ、５・・・データ
信号設定のスイッチ、６・・・システム制御信号設定の
スイッチ、７・・・オーブン端子ピン。FIG. 1 is a schematic diagram of an embodiment of a test apparatus applied to the present invention. FIG. 2 is an example of a configuration diagram and a wiring diagram of a switch provided in the test equipment. In Fig. 1, 1... switch stand, 2... IC socket, 3... connection line between switch stand and IC socket,
4...Switch for address signal setting, 5...Switch for data signal setting, 6...Switch for system control signal setting, 7...Oven terminal pin.
Claims (1)
、ロウレベル、オーブンに設定可能なｍ個のスイッチと
、ｎビットのデータバス上のデータ信号ヲハイレベル、
ロウレベル、オーブンに設定可能なｎ個のスイッチと、
マイクロプロセッサあるいはマイクロプロセッサ周辺Ｌ
ＳＩのシステム制御信号をハイレベル、ロウレベル、オ
ーブンに設定可能なで個のスイッチと、前記マイクロプ
ロセッサあるいはマイクロプロセッサ周辺Ｉ、ＳＩ用の
ＩＣソケットとを備え、前記３種のスイッチの各端子を
前記マイクロプロセッサあるいはマイクロプロセッサ周
辺ＬＳＩの端子配列に対応するように前記ＩＣソケット
の端子に接続したことを特徴とするマイクロプロセッサ
ボード試験装置。The address signal on the m-bit address bus can be set to high level, low level, or oven, and the data signal on the n-bit data bus can be set to high level.
n switches that can be set to low level and oven,
Microprocessor or microprocessor peripheral L
It is equipped with switches that can set the system control signal of the SI to high level, low level, and oven, and an IC socket for the microprocessor or the microprocessor peripheral I, and the SI, and each terminal of the three types of switches is connected to the A microprocessor board testing device, characterized in that it is connected to the terminals of the IC socket so as to correspond to the terminal arrangement of a microprocessor or a microprocessor peripheral LSI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5951684U JPS60170856U (en) | 1984-04-23 | 1984-04-23 | Microprocessor board test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5951684U JPS60170856U (en) | 1984-04-23 | 1984-04-23 | Microprocessor board test equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60170856U true JPS60170856U (en) | 1985-11-12 |
Family
ID=30586017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5951684U Pending JPS60170856U (en) | 1984-04-23 | 1984-04-23 | Microprocessor board test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60170856U (en) |
-
1984
- 1984-04-23 JP JP5951684U patent/JPS60170856U/en active Pending
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