JPS60170347A - Phase detecting circuit - Google Patents

Abstract

PURPOSE:To eliminate the necessity of a time-constant circuit, by obtaining information showing the phase relation between biphase data signals and clock pulses by means of a phase difference detecting circuit composed of a logical circuit. CONSTITUTION:A phase difference detecting circuit 13 is composed of an AND circuit 15, FF3, and EX-OR circuit 16. A clock pulse from a voltage controlled oscillator 11 is applied to a frequency divider 14 and an inverted clock pulse is fed to another phase difference detecting circuit 13. Moreover, the output of the frequency divider 14 and a biphase data signal Bi are supplied to the circuit 13. Then the circuit 13 forms a pulse width signal corresponding to the phase difference between the boundary time point of each data section and clock pulse. The output of the oscillator 11 is controlled by the pulse width signal. Therefore, it is not necessary to delay input biphase data signals and, as a result, the necessity of a time constant circuit can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase difference detection circuit used in a phase-locked loop (PLL) circuit or the like for reproducing pi-phase data.

[Technical background of the invention]

Generally, biphase data (B) is a type of PCM signal. I), the clock signal (
For a), the level is always inverted at the data boundary.

In each data interval, if the data is O, the level is maintained, and the level is inverted at the center of the interval from data 1 to the waveform signal. In order to demodulate this kind of pi-phase data, a recovered clock (CK) with twice the data period synchronized with this data is required, as shown in Fig. 1(a). As shown on pages 40 to 41 of Analysis Digital Circuit J (CQ Publishing ■), the pulse that detected the rising edge of the input biphase data signal from the signal obtained by delaying the input biphase data signal and the original signal. , from which you can make the regenerated clock pulses mentioned above.

That is, as shown in FIGS. 2 and 3, the delayed biphasic data signal (DB
i) and the original input biphase data signal (B1) to form an edge pulse (EP), which is combined with a voltage controlled oscillator (VCO) (
1) Exclusive OR with the output clock pulse (CK) to obtain a phase difference pulse (PD) whose pulse width indicates the phase relationship between the clock pulse and the edge pulse, as well as the input biphase data signal. This pulse is converted into a DC voltage by a low-pass filter (LPF) (2), which controls the output clock of VCO (H), and as shown in Figure 3 (a) to (e), the integral of the phase difference pulse becomes 0. In other words, the phase relationship is stabilized such that the rising edge of the clock pulse is at 1/2 of the rising edge of the input Bianese data signal and the delayed biphase data signal.

For example, as shown in FIG. 3(f), the input biphase data signal is connected to the resistor 3. Obtain an output bi-phase data signal (addition) delayed by the delay circuit of capacitor C1.

This can be reproduced using the clock pulse shown in FIG. 3(d).

By the way, when the clock reproduction circuit is configured as described above, a delay circuit, that is, a time constant circuit is required in order to generate edge pulses and to delay the incoming i-phase data signal, and a resistor element and a capacitor are required. Delay time varies depending on element variations.

If the pulse width of the edge pulse changes, the phase detection sensitivity will change, making it difficult to design an integrated circuit. Furthermore, unless the value of the time constant circuit is changed according to the frequency of the biphase data signal, the phase detection sensitivity will change, resulting in lack of versatility.

In order to implement an integrated circuit, it is necessary to externally attach a part of the time constant circuit, which also requires adjustment.

Furthermore, if the input biphase data signal has a high frequency, it becomes difficult to design a time constant circuit with a small time constant.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a phase detection circuit that does not require a time constant circuit, does not require adjustment, is easy to design, and can be made into a fully integrated circuit. .

[Summary of the invention]

The present invention includes a frequency divider that divides the output clock pulse of a variable frequency oscillator, and inputs the frequency divider output, the clock pulse, and a biphase data signal, and a boundary between each data section of the biphase data signal. A phase difference detection circuit configured as a logic circuit for obtaining a pulse width signal according to a phase difference between a time point and the clock pulse is provided, and the output of the phase difference detection circuit is used to control the output of the oscillator.

〔Effect of the invention〕

According to the present invention, since information indicating the phase relationship between the cipher phase data signal and the clock pulse output from the oscillator is obtained by the phase difference detection circuit having a logic circuit configuration, a time constant circuit is not required, and the entire A phase detection circuit that can be easily integrated into an integrated circuit can be obtained.

[Embodiments of the invention]

An embodiment of the present invention will be described below. FIG. 4 shows an embodiment of the phase detection circuit of the present invention. In the same figure,
(11) is a voltage controlled oscillator (VCO), which receives the signal that has passed through the low-pass filter (LPF) (2).2 The higher the voltage, the higher the frequency of the output clock pulse (CK). controlled. The clock pulse (CK) of the VCOI output is input to the phase difference detection circuit (13), and the one inverted clock pulse (CK) is input to the divider I.

Brancher I is a two-stage D type flip-flop (FFI)
, (FF2) is empty, and the inverted clock pulse (CK) of (C0a1) is input to the clock terminal of the flip-flop (FFI). D of flip-flop (FF2)
The Q output Q8 of the flip-flop (FF1) is input to the terminal, and the clock pulse of vco (xi) is input to the clock terminal. This flip-flop (FF2)
The Q output Q2 is input to the D terminal of the 7-lip 70-tub (FF1).

The phase difference detection circuit α■ is an AND circuit (IQ) that takes the logical product of the output of the flip 70 tube (FF2) and the clock pulse (CK) of the VCO (11), and inputs the output of this circuit to the clock terminal and performs a bypass. A D type flip-flop (FF3) that receives a phase data signal as the D terminal input, an exclusive OR circuit (FF3) that takes the exclusive OR of the Q output Q of this flip-flop, and the bi-phase data signal.
1G). The output of the phase difference detection circuit (131) and the output Q1 of the flip-flop (FFI) are ANDed in an AND circuit η, and this output is input to the LPF (1'J).

The operation of the phase detection circuit shown in FIG. 4 will be explained with reference to the waveform diagram shown in FIG. The clock pulse at the output of the VCO (Iυ) is shown in FIG. b).On the other hand, the clock input of the flip-flop (F'F2) is the clock pulse of VCOQυ, and the D input is the above Q.The state of the D input is output at the rising edge of the clock pulse. Therefore, the inverted output Qt of the flip-flop (FF2) output is shown in FIG. A pulse of frequency is obtained.

The AND circuit α in the α station of the phase difference detection circuit performs the logical product of the inverted output Q2 of the 7 lip-flop (FF2) and the clock pulse (CK) of the VCO (11), resulting in the result shown in Fig. 5(d).
), a pulse train A that rises at the center of the biphase data signal is obtained.

Assume now that the input biphase data signal (Bi) is 00100 as shown in FIG. 5(e). In the figure, a solid line shows a waveform in a stable state, and a chain line shows a waveform in a state where input Bi is slightly delayed.

The flip-flop (F'F'3) has a function of outputting the input to the D terminal when the input to the clock terminal is at H level. The clock terminal receives the output signal (A) of the AND circuit (15), and the D terminal receives the Pineneese data signal (B).
As shown in FIG. 5(f), the output Q becomes a signal whose level is inverted at the center of the 00 data interval of the biphase data signal (BJ).

At this time, if the oscillation frequency of VCO (lυ) becomes a little higher, that is, if Bl lags a little, Q, as shown by the dotted line, becomes a signal 1.
The waveform also generates a pulse at the center of the data interval. Since the Q output Q3 of the 7-lip flop (FF3) and the input Bianese data signal (Bi) are exclusive ORed in the exclusive OR circuit αe, the A signal that inverts the level is obtained. This signal becomes a waveform in which the first part of each data section is missing when Bi is delayed.

The signal E is ANDed by the Q output Q1 of the flip-flop (FF1) and the AND circuit η, and a signal E shown in FIG. 5(h) is obtained. The width of this pulse signal E is.

The biphase data signal (Bi) is delayed (i.e.
The higher the oscillation frequency of the VCO αυ output, the narrower the fi.
, the voltage F applied to the VCO (1υ) through the LPF (L) becomes lower.

Therefore, the frequency of the clock pulse output from the VCO (11) decreases, and as a result, Bi becomes relatively advanced and stable. Conversely, as Bi advances, F increases and the frequency of the output of pvco(u) increases.

In this manner, in the embodiment of FIG. 4, the clock pulse (CK) of the vCOαυ output and the input biphase data signal (B) are stabilized in the relationship shown in FIG. 5 (Fl) and (e) (solid lines).

The above embodiment has the advantage that one circuit configuration is simple.

By the way, in the above embodiment, the frequency of the output clock pulse becomes constant when a predetermined voltage (voltage corresponding to E in FIG. 5th) is applied to vco (o). However, it is also possible to use a VCO in which the frequency of the output clock pulse is constant when the input voltage is 00. The configuration of an embodiment of this type of the present invention is shown in FIG.

This embodiment also has a VCO (2+) having the same configuration as the above embodiment.
.

It has a low-pass filter 07J1 phase difference detection circuit C3) and a frequency divider Q4). This embodiment also includes a switch circuit (5). The switch circuit (27) is in an AND circuit which takes the AND of the Q output Q of the flip-flop (FF1) and the Q output Q2 of the 7 flip-flop (FF2).

It consists of an AND circuit that takes the logical product of the Q output Q of the 7-lipflip ptub (pFl) and the output of the exclusive off circuit, and an OR circuit that takes the logical sum of the outputs of both the AND circuits. The output of this switch circuit is fed into a Lohas filter.

The waveforms of various parts of the embodiment shown in FIG. 6 are shown in FIG. 7th
(a) to Φ) in the figure are the fifth
The waveform is exactly the same as the one shown in the figure. On the other hand, since the output of the AND circuit (2) is the AND of the Q outputs of the flip-flops (FFI) and (FF2), it has a G waveform as shown in FIG. 7(i). This waveform has no relation to the advance or delay of the biphase data signal, and the output H of the OR circuit becomes as shown in FIG. 7 (0). As shown by the dotted line, the bi-phase data signal (if the B is delayed, the output of the OR circuit (to) is
PF (signal F passed through 221 becomes a negative voltage, and vco
(The frequency of the clock pulse (CK) of the 2D output decreases. Conversely, when the biphase data signal (Bi) advances (that is, the frequency of the output pulse of the VCO decreases), the output F of LPF Q3 becomes a positive voltage. However, the frequency of the output pulse of vCOQη becomes higher. In this way.

This phase detection circuit becomes stable when the signal F is in the O state.

In this embodiment, not only signal E is applied to LPFQ3.

A similar waveform G is switched and used as the phase detection output υ, and the offset of the average DC level of the low-pass filter (2υ output is small. In other words, when the input terminal is 0 as the VCO (2υ), the frequency of the output clock pulse changes. It is possible to use a voltage controlled oscillator that does not have a
The system is stabilized by the phase relationship between CK and Bi shown in a) and (e).

In both of the above embodiments, there is no need to delay the input bi-phase day and night signals, and therefore there is no need for the time constant circuit constituted by the resistor R2 and capacitor C2 shown in FIG.

It should be noted that the present invention is not limited to the above-described embodiment, and the configuration and polarity of the phase difference detection circuit and switch circuit of the branching unit 9 can be freely set depending on the type of logic circuit used.

In addition, a voltage controlled oscillator (VCO) can be one in which the frequency of the output pulse has an inverse relationship to the input voltage, and more generally, not only the voltage controlled type, but also the frequency of the output pulse and the input pi-phase Any device that changes the oscillation frequency in accordance with a signal indicating information on the phase relationship of data signals may be used.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining a bi-phase data signal, Fig. 2 is a diagram showing a phase detection circuit configured according to the conventional technology, Fig. 3 is an explanatory diagram of the operation of the circuit in Fig. 2, and Fig. 4 is a diagram for explaining the operation of the circuit in Fig. 2. 5 is a diagram illustrating the operation of the circuit of FIG. 4. FIG. 6 is a diagram illustrating a phase detection circuit according to another embodiment of the present invention. FIG. 7 is an explanatory diagram of 1b of the circuit of FIG. 6. 11.21... Voltage controlled oscillator 12.22... Low pass filter 13, 23... Phase difference detection circuit 14.24... Frequency divider 15, 25, 28, 29... AND circuit 16
, 26... exclusive OR circuit 17...
・・・・・・AND circuit 27・・・・・・・・・・・・Switch circuit agent Patent attorney Norichika Kensuke (1 person) 1st
Figure 2 Part 4 Figure 5 Figure 7

Claims (2)

[Claims] (1) An oscillator that changes the frequency of the output clock pulse, a divider that divides the clock pulse output from this oscillator, and a biphase data signal that receives the output of the frequency divider, the clock pulse, and the biphase data signal as input. and a phase difference detection circuit having a logic circuit configuration that obtains a pulse width signal corresponding to the phase difference between the boundary point of each data interval and the clock pulse, and controls the output of the oscillator using this signal. Phase detection circuit. (2) The phase difference detection circuit includes an AND circuit that takes the logical product of the output signal of the divider and the clock signal, and a D-type flip-flop that uses the output of the AND circuit as the clock input and the biphase data signal as the D input. 2. The phase detection circuit according to claim 1, comprising an exclusive OR circuit which receives the output of the D-type flip-flop and the biphase data signal and performs an exclusive OR.