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JPS60169984U - Feedback clamp circuit - Google Patents

Feedback clamp circuit

Info

Publication number
JPS60169984U
JPS60169984U JP5702184U JP5702184U JPS60169984U JP S60169984 U JPS60169984 U JP S60169984U JP 5702184 U JP5702184 U JP 5702184U JP 5702184 U JP5702184 U JP 5702184U JP S60169984 U JPS60169984 U JP S60169984U
Authority
JP
Japan
Prior art keywords
resistor
transistor
clamp circuit
control means
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5702184U
Other languages
Japanese (ja)
Other versions
JPH0339980Y2 (en
Inventor
里見　英雄
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP5702184U priority Critical patent/JPS60169984U/en
Publication of JPS60169984U publication Critical patent/JPS60169984U/en
Application granted granted Critical
Publication of JPH0339980Y2 publication Critical patent/JPH0339980Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の帰還型クランプ回路を示す回路図、第
２図は本考案の帰還型クランプ回路を示す他の実施例の
回路図である。 主な図番の説明、２・・・電源ライン、４・・・第１の
抵抗、５・・・第２の抵抗、６・・・第３の抵抗、７・
・・第４の抵抗、８・・・第１のトランジスタ、９・・
・第２のトランジスタ、１３・・・比較制御手段、１６
・・・カレントミラー回路。FIG. 1 is a circuit diagram showing a feedback clamp circuit of the present invention, and FIG. 2 is a circuit diagram of another embodiment of the feedback clamp circuit of the present invention. Explanation of main figure numbers, 2... Power supply line, 4... First resistor, 5... Second resistor, 6... Third resistor, 7...
...Fourth resistor, 8...First transistor, 9...
- Second transistor, 13... Comparison control means, 16
...Current mirror circuit.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）磁気録画再生装置の記録系において、電源ライン
とアース間に接続した第１の抵抗、第１のトランジスタ
及び負荷と、前記電源ラインとアース間に直列接続した
第２の抵抗及び、その入力と基準電圧を比較した比較出
力を制御する比較制御手段と７、そのベースを該比較制
御手段と、またコレクタを前記第１のトランジスタのエ
ミッタと接続すると共にエミッタを第３の抵抗を介して
接地した第２のトランジスタとより構成され、前記負荷
の一端と前記比較制御手段を接続して該比較制御手段、
前記第１及び第２のトランジスタにより帰還ループを成
し、前記第１のトランジスタのベースに映像信号を入力
し、前記比較制御手段から出力信号を得ることを特徴と
する帰還型クランプ回路。(1) In a recording system of a magnetic recording/playback device, a first resistor, a first transistor, and a load are connected between the power line and the ground, a second resistor is connected in series between the power line and the ground, and the second resistor is connected in series between the power line and the ground. a comparison control means 7 for controlling a comparison output obtained by comparing an input and a reference voltage, the base of which is connected to the comparison control means, the collector connected to the emitter of the first transistor, and the emitter connected to the first transistor through a third resistor; a grounded second transistor, connecting one end of the load to the comparison control means;
A feedback clamp circuit comprising a feedback loop formed by the first and second transistors, inputting a video signal to the base of the first transistor, and obtaining an output signal from the comparison control means. （２）　　前記負荷として第４の抵抗を接続した実用新
案登録請求の範囲第１項記載の帰還型クランプ回路。(2) The feedback clamp circuit according to claim 1, wherein a fourth resistor is connected as the load. （３）前記負荷としてカレントミラー回路を接続した実
用新案登録請求の範囲第１項記載の帰還型クランプ回路
。(3) The feedback clamp circuit according to claim 1, wherein a current mirror circuit is connected as the load.
JP5702184U 1984-04-18 1984-04-18 Feedback clamp circuit Granted JPS60169984U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5702184U JPS60169984U (en) 1984-04-18 1984-04-18 Feedback clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5702184U JPS60169984U (en) 1984-04-18 1984-04-18 Feedback clamp circuit

Publications (2)

Publication Number Publication Date
JPS60169984U true JPS60169984U (en) 1985-11-11
JPH0339980Y2 JPH0339980Y2 (en) 1991-08-22

Family

ID=30581164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5702184U Granted JPS60169984U (en) 1984-04-18 1984-04-18 Feedback clamp circuit

Country Status (1)

Country Link
JP (1) JPS60169984U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352182A (en) * 2000-06-05 2001-12-21 Sharp Corp Chassis structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485634A (en) * 1977-12-20 1979-07-07 Sharp Corp Dark current clipping circuit for television camera
JPS5910076A (en) * 1982-07-08 1984-01-19 Hitachi Denshi Ltd Gamma compensating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485634A (en) * 1977-12-20 1979-07-07 Sharp Corp Dark current clipping circuit for television camera
JPS5910076A (en) * 1982-07-08 1984-01-19 Hitachi Denshi Ltd Gamma compensating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352182A (en) * 2000-06-05 2001-12-21 Sharp Corp Chassis structure

Also Published As

Publication number Publication date
JPH0339980Y2 (en) 1991-08-22

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