JPS6016465A - Transistor - Google Patents

Abstract

PURPOSE:To effectively restrain parasitic effect by a method wherein the surface of an N type island region is provided with a P type capture region and an N<+> connection layer contacting it so as to surround the base, emitter, and collector layers, and an electrode in ohmic contact with both is attached. CONSTITUTION:The N type island 52 isolated with an N<+> buried layer 55 and a P<+> layer 54 is provided by the diffusion of the P<+> capture region 59, P-base layer 56, and N<+> connection layer 63 at the same time with the N-emitter 57. The connection layer 63 is made adjacent outside the capture region 59 opposed to the emitter layer 57 most alienated from the connection layer 58 of the collector region 53, and the region 59 and the layer 63 are short-circuited with the electrode 64. Such a construction enables to effectively restrain the parasitic effect of the transistor by means of a feedback loop formed of the capture region 59, connection region 53, and connection electrode 64. Since the connection layer 63 is provided at the position of the minimum collector potential at which the parasitic effect is easy to generate, leakage currents to the P type substrate 31 can be securely recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a transistor with reduced parasitic effects.

(b) Prior art As shown in FIG. 1, an NPN transistor incorporated in a conventional monolithic integrated circuit consists of a P-type semiconductor substrate (1), an N-type epitaxial layer (2) serving as a collector region, and an epitaxial layer (2). A P-type isolation region (4) separated into an island region (3), an N''W buried layer (5) provided on the bottom surface of the island region (3), and a P-type doubly diffused layer on the surface of the island region (3).
Consisting of a type base region (6), an N1 type emitter region (7), a square type collector contact region (8) formed on the surface of the epitaxial layer (2), a collector electrode (9), a heath electrode a0, and an emitter electrode αυ. has been done.

In such a transistor, a parasitic PNP transistor is formed in the space region (61, epitaxial layer (2) and substrate (1)). This equivalent circuit is shown in FIG.

In FIG. 2, Ql is an original NPN) transistor and Q2 is a parasitic PNP transistor.

The present inventor made an improvement shown in FIG. 3 in order to remove the layered parasitic PNP transistor. That is, this transistor consists of a P-type silicon semiconductor substrate (21J) and a substrate (21J).
), an N-type epitaxial layer (4) provided on the epitaxial layer (2Z), a P+-type isolation region (24) that separates the epitaxial layer (2Z) into island regions (c), and a T-type buried layer ( 2 heat and an island area on the embedded 4 layer e section (c) 2 on the surface
P type base region (2) formed by heavy diffusion, N' type emitter region (27), and epitaxial layer of island region (c) (V type collector contact region formed on the surface of 22).
C), the space area that essentially constitutes the transistor, the emitter region (2η and 19=p, -V lid contact 5 area), the P-type capture area surrounding the 2 camphors, the space between each area (2
) (2) Emitter electrode and base electrode C31) in ohmic contact with.

It consists of a collector electrode (13), which extends beyond the collector electrode (13) over the oxide film (2) and is connected to the capture region (2o).

According to the improved structure on the layer, the capture area (2 dark substrates)
Almost all of the current flowing through the parasitic PNP transistor is recovered and returned to the collector electrode 04.

However, in this structure, the edge of the capture region is the collector electrode (
Since the trapping region (2ω is the collector potential 0), the trapping region (2) must be at least lower than the base potential in order for holes to be injected from the base region (4). Naturally, there was a drawback that the hole could not be captured using the guard ring.

(c) Purpose of the Invention The present invention has been made in view of the above drawbacks, and is an object of the present invention to realize a transistor which can effectively suppress parasitic effects.

Structure of the Invention The transistor according to the present invention, as shown in FIG. 4 and FIG.
53), a P-type isolation region +541, an N+-type buried layer 65), and a P-type base region 6 [and an N-type emitter region 67] on the surface of the island region G3). It is composed of a P-type capture region (59) surrounding the P-type contact region (63), and a connection electrode @a that connects the two.

(E) Embodiment According to the present invention, a P-type silicon semiconductor substrate oIJ,
Six N-type epitaxial layers provided on the substrate υ, a P-type isolation region 5 that sufficiently separates the epitaxial layer M E21 to the island region 6J of the number, and a P-type isolation region 5 provided on the island region 6J. P-type buried layer G gloss and buried layer 651
A P-type base region and a P-type emitter region 57) formed by double diffusion on the surface of the upper island region 531, and the island region-
an N-type collector contact region (to) provided on the surface;
Emitter area 6? ) A transistor is provided which includes an emitter electrode-base electrode 6υ and a collector electrode 12 that are in ohmic contact with the base region side and the end of the collector contact region, and the base region (to) emitter region L5η and the collector contact region that substantially constitute the transistor are provided. A P-type capture region 6I is provided on the surface of the island region 6 (G) so as to surround the end, and a P-type contact region is provided on the surface of the island region adjacent to the capture region 3), thereby making an ohmic connection between the two. Equipped with electrodes.

Features of the present invention include six capture regions and a contact region 131.
It is in. The capture region 6 is formed by diffusion at the same time as the base region (T), and the end of the contact region is formed by diffusion at the same time as the emitter region 6η. Contact area 1: i &
'! Provided in the collector region 6 ~ where the voltage drop is large,
Specifically, as shown in Figure 5, the collector contact area (T)
It is provided adjacent to the outside of the capture region (51) opposite to the emitter region (67) which is the farthest away from the capture region (51).
A connecting electrode (material) is formed to short-circuit the 'll and the contact area. The connecting electrode (goods) is the capture area (!
It may be extended in ohmic contact over the il.

According to the structure of the present invention, the holes captured in the capture region 69) are returned to the collector region 6th floor from the contact region 6J via the connection electrode (material) and consumed again by the transistor operation. The greatest feature of the present invention is the contact area 1'
! The point is that J is formed in the part of the collector region 6 (towards) where the collector potential is lowest, where parasitic effects are likely to occur. As a result, since the capture region side is biased to the lowest collector potential via the connection electrode (G41), it is naturally lower than the base potential, and holes injected from the end of the pace region can be effectively and reliably captured. As a result, the parasitic effects can be suppressed more effectively than the conventional improved structure shown in FIG.
It can be effectively suppressed by a feedback loop formed by the contact region ( ) and the connection electrode. Furthermore, since the contact region is provided at the lowest collector potential where parasitic effects are likely to occur, leakage current to the substrate (5υ) can be reliably recovered.

[Brief explanation of drawings]

FIG. 1 is a sectional view illustrating a conventional transistor, FIG. 2 is an equivalent circuit diagram thereof, FIG. 3 is a sectional view illustrating a conventional improved transistor, and FIGS. 4 and 5 are transistors of the present invention. FIG. 2 is a cross-sectional view and a top view for explaining. Explanation of main figure numbers 51) is a P-type semiconductor substrate, I52 is an N-type epitaxial layer, 6 [Yes] is an island region, (b) is a P-type isolation region, (5e
is a P type base region, 67) is an N+ type emitter region, gloss is a tm collector contact region, axis is a P type capture region,
The reference character is an N+ type contact region, and the negative character is a connection electrode. Day 1, Figure 54? 1) 5 days

Claims (1)

[Claims] (1) - A semiconductor substrate of a conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate and serving as a collector region, an isolation region of one conductivity type for separating the epitaxial layer into island regions, and a separation region provided on the bottom surface of the island region. a buried layer of opposite conductivity type, a space region of one conductivity type formed on the surface of the island region on the buried layer, and an emitter region of opposite conductivity type formed on the surface of the base region. A trapping region of one conductivity type is provided to surround the base region, a contact region of the opposite conductivity type is provided in the lowest part of the collector region, and the contact region and the trapping region are connected by a connecting electrode. A transistor characterized by: