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JPS60163506A - Phase modulation circuit - Google Patents

Phase modulation circuit

Info

Publication number
JPS60163506A
JPS60163506A JP1840284A JP1840284A JPS60163506A JP S60163506 A JPS60163506 A JP S60163506A JP 1840284 A JP1840284 A JP 1840284A JP 1840284 A JP1840284 A JP 1840284A JP S60163506 A JPS60163506 A JP S60163506A
Authority
JP
Japan
Prior art keywords
differential amplifier
amplifier circuit
balanced
transistors
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1840284A
Other languages
Japanese (ja)
Inventor
Satoru Shinozaki
篠崎 了
Noboru Kusama
草間 昇
Yoichi Saito
洋一 斉藤
Shozo Komaki
小牧 省三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1840284A priority Critical patent/JPS60163506A/en
Publication of JPS60163506A publication Critical patent/JPS60163506A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C1/00Amplitude modulation
    • H03C1/52Modulators in which carrier or one sideband is wholly or partially suppressed
    • H03C1/54Balanced modulators, e.g. bridge type, ring type or double balanced type
    • H03C1/542Balanced modulators, e.g. bridge type, ring type or double balanced type comprising semiconductor devices with at least three electrodes
    • H03C1/545Balanced modulators, e.g. bridge type, ring type or double balanced type comprising semiconductor devices with at least three electrodes using bipolar transistors

Landscapes

  • Amplitude Modulation (AREA)

Abstract

PURPOSE:To attain stable and excellent characteristic at a high frequency band and also to attain ease of circuit integration by blocking a DC component and inputting the result to a double balanced differential amplifier circuit after an unbalanced carrier signal is converted into a balanced signal. CONSTITUTION:Two collector outputs of the differential amplifier circuit composisting of transistors (Tr)7, 8 are fed respectively via capacitor C1, C2 as the carrier signal input of the double balanced differential amplifier circuit comprising Trs 1-6. Moreover, the unbalanced carrier signal is inputted from an input terminal CIN to a base of the Tr7 via a bias blocking capacitor C3 and the base of the Tr8 is terminated by a resistor R1 via a bias blocking capacitor C4. Thus, the differential amplifier comprising the Trs 7, 8 is applied with unbalanced signal from one input and there is a difference is the DC operating point between the collectors, the DC component is blocked by the capacitors C1, C2 and no effect is given to the balance of the double balance differential amplifier circuit, and stable phase modulation is attained together with the temperature characteristic.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トランジスタで構成される差動増幅回路を基
本とした平衡変調回路に関し、特に無線通信装置などの
高周波帯域での使用に適する位相変調回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a balanced modulation circuit based on a differential amplifier circuit composed of transistors, and is particularly suitable for use in a high frequency band such as a wireless communication device. Related to modulation circuits.

〔従来技術〕[Prior art]

従来、高周波帯域での位相変調回路としては。 Conventionally, as a phase modulation circuit in a high frequency band.

ダイオードブリッジと平衡トランスとで構成されるリン
グ変調回路が一般的であった。しかしながら、このよう
なトランスを用いた回路は、集積回路化に適さないとい
う欠点があった。
Ring modulation circuits consisting of diode bridges and balanced transformers were common. However, a circuit using such a transformer has a drawback in that it is not suitable for integration into an integrated circuit.

これに対し、近年、集積回路技術の進歩によシ。On the other hand, in recent years, advances in integrated circuit technology have made this possible.

集積されるトランジスタも高周波で動作可能なものが実
現できるようになってきておシ、高周波トランジスタと
抵抗とによる差動増幅回路を組合せた集積回路による平
衡変調回路が提供されている。
Integrated transistors that can operate at high frequencies have become available, and balanced modulation circuits using integrated circuits that combine differential amplification circuits using high-frequency transistors and resistors have been provided.

この回路は、トランスが不要でしかも容易に得られると
いうだけでなく、ダイオードブリッジも無くダイオード
容量変化に起因する位相変化が無いため、高精度化が可
能という特長を有している。
This circuit not only does not require a transformer and can be easily obtained, but also has the advantage of being highly accurate since there is no diode bridge and there is no phase change caused by changes in diode capacitance.

とは言え、トランジスタ差動増幅回路を用いた回路には
問題点もアシ、その一つに差動増幅回路の基本素子であ
る対向する2個のトランジスタのジャンクション順方向
耐圧などの差によって生じる平衡度の差がある。このた
めトランジスタの電気的緒特性をそろえるなどしてこの
平衡度の差をできるだけ小さくする工夫がなされている
。特に。
However, circuits using transistor differential amplifier circuits have some problems, one of which is the imbalance caused by the difference in junction forward breakdown voltage between two opposing transistors, which are the basic elements of a differential amplifier circuit. There are differences in degree. For this reason, efforts have been made to minimize this difference in balance by making the electrical characteristics of the transistors the same. especially.

このような差動増幅回路を位相変調回路に用いる場合、
この平衡度の差をt丘とんど無視し得る値に抑え込まな
いと、搬送波信号の抑圧比が充分に得られず、特性上問
題となる場合が多い。これに対しては1通常、差動増幅
回路の直流動作点を調整して搬送波抑圧比を最良点を選
ぶなどの方法がとられる。また、環境温度の変化によっ
て一般に平衡度の差は変化し、直流動作点の調整による
補正量が多いほど特性劣化の度合が大きいという問題も
ある。
When using such a differential amplifier circuit in a phase modulation circuit,
Unless this difference in balance is suppressed to a value that can be ignored, a sufficient suppression ratio of the carrier signal cannot be obtained, which often causes problems in terms of characteristics. To deal with this, a method is usually used, such as adjusting the DC operating point of the differential amplifier circuit and selecting the best point for the carrier wave suppression ratio. Another problem is that the difference in balance generally changes with changes in environmental temperature, and the greater the amount of correction by adjusting the DC operating point, the greater the degree of characteristic deterioration.

一方、差動増幅回路を基本とした平衡変調回路では、原
理的には変調入力信号、搬送波入力信号。
On the other hand, in a balanced modulation circuit based on a differential amplifier circuit, in principle, the modulation input signal and carrier wave input signal.

変調出力信号は平衡入出力であシ、不平衡入出力とする
場合には2片側を抵抗終端とする方法が良く用いられる
。これに対して、高周波の位相変調回路においては、変
調入力信号は比較的低周波で。
The modulated output signal must be a balanced input/output signal, and when it is an unbalanced input/output signal, a method in which two sides are terminated with a resistor is often used. In contrast, in a high-frequency phase modulation circuit, the modulation input signal is at a relatively low frequency.

普通、平衡信号で取シ扱われるが、搬送波信号及び変調
出力信号は高周波でアシ、不平衡信号としないと取シ扱
いが難しい。このうち出力信号に関しては、平衡出力の
片側を抵抗終端とすることで。
Normally, they are handled as balanced signals, but it is difficult to handle them unless the carrier wave signal and modulated output signal are high-frequency, unbalanced signals. Regarding the output signal, one side of the balanced output is terminated with a resistor.

擬似的な平衡負荷条件が得られるので、変調回路に与え
る影響はほとんど無いと考えられる。しかし、搬送波信
号については、差動増幅回路の平衡入力の片側を抵抗終
端とすることで信号源インピーダンスの平衡性は保たれ
るが、動作状態において差動増幅回路の2個のトランジ
スタのうち、搬送波信号の入力するトランジスタと終端
抵抗に接続されたトランジスタとでは動作条件に差がア
シ。
Since a pseudo-balanced load condition is obtained, it is thought that there is almost no effect on the modulation circuit. However, for the carrier signal, the balance of the signal source impedance can be maintained by terminating one side of the balanced input of the differential amplifier circuit with a resistor, but in the operating state, of the two transistors of the differential amplifier circuit, There is a difference in operating conditions between the transistor that receives the carrier wave signal and the transistor that is connected to the termination resistor.

平衡度に差がでる。このため、温度特性も含めて良好な
位相変調特性を得るには、搬送波信号を平衡信号に変換
して差動増幅回路に入力する必要がある。この不平衡を
平衡に変換する手段としてトランス等を使用すると、集
積回路化が困難となシ安価にすることができないという
ことは前述した通シである。
There will be a difference in balance. Therefore, in order to obtain good phase modulation characteristics including temperature characteristics, it is necessary to convert the carrier signal into a balanced signal and input it to the differential amplifier circuit. As mentioned above, if a transformer or the like is used as a means to convert this unbalanced state into a balanced state, it will be difficult to integrate the circuit and it will not be possible to reduce the cost.

〔発明の目的〕[Purpose of the invention]

本発明は1以上の考察にもとづいてなされたもので、高
周波帯域においても良好な特性が得られ集積回路化が容
易で動作の安定な位相変調回路を提供することを目的と
している。
The present invention was made based on one or more considerations, and an object of the present invention is to provide a phase modulation circuit that exhibits good characteristics even in a high frequency band, is easy to integrate into an integrated circuit, and has stable operation.

以下2図面を参照して説明する。This will be explained below with reference to two drawings.

第1図は、トランジスタ差動増幅回路を用いて平衡変調
回路を構成した例であシ、二重平衡差動増幅回路である
。この回路ではトランジスタ1゜2.5と3+4t6の
2組の差動増幅回路の出力を逆極性で共通接続し、トラ
ンジスタ5,6をそれぞれエミッタ抵抗REI 、 R
E2を介して定電流源CC,に接続して2重平衡差動増
幅回路としているのが特徴である。これによって、平衡
変調信号入力端子INIとIN2に入力される平衡信号
は正負の値をとることができ、との信釡に比例して出力
が平衡変調出力端子0UTI 、 0UT2間に平衡信
号として得られる。従って、平衡搬送波信号入力端子C
INIとClN2に搬送波信号を平衡信号として入力す
ることによシ、2相の位相変調回路として動作させるこ
とができる。
FIG. 1 shows an example in which a balanced modulation circuit is constructed using a transistor differential amplifier circuit, and is a double balanced differential amplifier circuit. In this circuit, the outputs of two sets of differential amplifier circuits, transistors 1°2.5 and 3+4t6, are connected in common with opposite polarities, and transistors 5 and 6 are connected to emitter resistors REI and R, respectively.
It is characterized in that it is connected to a constant current source CC via E2 to form a double balanced differential amplifier circuit. As a result, the balanced signal input to the balanced modulation signal input terminals INI and IN2 can take positive and negative values, and the output is obtained as a balanced signal between the balanced modulation output terminals 0UTI and 0UT2 in proportion to the input terminals 0UTI and 0UT2. It will be done. Therefore, balanced carrier signal input terminal C
By inputting a carrier signal as a balanced signal to INI and ClN2, it can be operated as a two-phase phase modulation circuit.

〔発明の構成〕[Structure of the invention]

本発明は、高周波帯域での使用に適した不平衡搬送波信
号をトランジスタ差動増幅回路によって平衡信号に変換
した後、コンデンサによって直流分を阻止して二重平衡
差動増幅回路に入力し9位相変調回路としたことを特徴
とする。
The present invention converts an unbalanced carrier signal suitable for use in a high frequency band into a balanced signal using a transistor differential amplifier circuit, and then blocks the DC component using a capacitor and inputs it to a double balanced differential amplifier circuit. It is characterized by being a modulation circuit.

〔発明の実施例〕[Embodiments of the invention]

以下9本発明の詳細な説明する。 Hereinafter, nine aspects of the present invention will be described in detail.

第2図は本発明の一実施例の回路で、第1図同様トラン
ジスタ1t2t3,4,5,6で構成される二重平衡差
動増幅回路の搬送波信号入力としてトランジスタ7.8
で構成される差動増幅回路の差動出力、すなわち2つの
コレクタ出力をそれぞれコンデンサC1及びC2を介し
て供給し、不平衡搬送波信号入力端子CINよシネ平衡
搬送波信号をバイアス阻止用のコンデンサC3を介して
トランジスタのペースに入力する構成となっている。
FIG. 2 shows a circuit according to an embodiment of the present invention, in which transistors 7 and 8 are used as carrier wave signal inputs of a double-balanced differential amplifier circuit composed of transistors 1t2t3, 4, 5, and 6 as in FIG.
The differential outputs, that is, the two collector outputs, of the differential amplifier circuit configured with the circuit are supplied via capacitors C1 and C2, respectively, and the cine balanced carrier signal is supplied to the unbalanced carrier signal input terminal CIN through the bias blocking capacitor C3. The configuration is such that the input is input to the pace of the transistor through the circuit.

差動増幅回路のもう一方の入力であるトランジスタ8の
ペースは、バイアス阻止用のコンデンサC4を介して抵
抗R1で終端されている。B1〜B4はバイアス印加用
のプリーダ回路である。
The other input of the differential amplifier circuit, the transistor 8, is terminated with a resistor R1 via a bias blocking capacitor C4. B1 to B4 are reader circuits for applying bias.

トランジスタ7.8の差動増幅回路は、入力のら 片側か!不平衡信号を印加しているので、平衡度に差が
生じ、差動出力であるトランジスタ7.8のコレクタ間
の直流動作点にも差が生じるが、コンデンサCI、C2
によって直流成分が阻止されるので二重平衡差動増幅回
路の平衡度に影響を与えな馳で済み、温度特性も含めて
安定な位相変調回路として動作することが可能である。
Is the differential amplifier circuit of transistors 7 and 8 on one side from the input? Since an unbalanced signal is applied, a difference occurs in the degree of balance, and a difference also occurs in the DC operating point between the collectors of transistors 7 and 8, which are differential outputs.
Since the DC component is blocked by this, it does not affect the balance of the double-balanced differential amplifier circuit, and it is possible to operate as a stable phase modulation circuit including temperature characteristics.

〔発明の効果〕〔Effect of the invention〕

この位相変調回路によれば、搬送波信号の外部からの入
力は高周波帯での取扱いが容易な不平衡信号で良く、不
平衡搬送波信号を平衡信号に変換する事によシ、二重平
衡差動増幅回路においては不平衡高周波信号の入力によ
る特性劣化を抑える事ができる。また、不平衡搬送波信
号をトランジスタ差動増幅回路によって平衡に変換する
ことで集積回路化が容易となる。更に、トランジスタ差
動増幅回路からの搬送波平衡信号をコンデンサによシ直
流成分を阻止することによシアトランジスタ差動増幅回
路の入力の片側を抵抗終端としてもそこで発生する直流
の平衡度の差が回路特性に影響を与えないという利点を
有する。
According to this phase modulation circuit, the input of the carrier signal from the outside can be an unbalanced signal that is easy to handle in a high frequency band, and by converting the unbalanced carrier signal into a balanced signal, a double balanced differential signal can be input. In the amplifier circuit, characteristic deterioration due to input of unbalanced high frequency signals can be suppressed. In addition, by converting an unbalanced carrier wave signal into a balanced one using a transistor differential amplifier circuit, integration into an integrated circuit is facilitated. Furthermore, by blocking the DC component of the carrier-balanced signal from the transistor differential amplifier circuit using a capacitor, even if one side of the input to the shear transistor differential amplifier circuit is terminated with a resistor, the difference in DC balance that occurs there can be suppressed. It has the advantage of not affecting circuit characteristics.

以上のことから、高周波帯での使用に適した不平衡搬送
波信号で入力できるうえに安定で良好な特性が得られ、
しかもトランジスタと抵抗及びコンデンサを回路素子と
するだめ集積回路化が容易で、量産化することによって
安価な位相変調回路が得られる。
From the above, it is possible to input an unbalanced carrier signal suitable for use in high frequency bands, and to obtain stable and good characteristics.
Furthermore, by using transistors, resistors, and capacitors as circuit elements, it is easy to integrate the circuit, and by mass producing it, an inexpensive phase modulation circuit can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は二重平衡差動増幅回路の例。 第2図は本発明の一実施例の位相変調回路。 CCI 、 CC2・・・定電流源、Bl、B2.B3
゜B4・・・バイアス印加用プリーダ回路、 INI 
、 IN2・・・平衡変調信号入力端子、 0UTI 
、 0UT2・・・平衡変調信号出力端子、 CINI
 、 ClN2・・・平衡搬送波信号入力端子、 CI
N・・・不平衡搬送波信号入力端子。 Vco・・・回路電源、RI・・・終端抵抗。
Figure 1 shows an example of a double-balanced differential amplifier circuit. FIG. 2 shows a phase modulation circuit according to an embodiment of the present invention. CCI, CC2...constant current source, Bl, B2. B3
゜B4...Bias application leader circuit, INI
, IN2...Balanced modulation signal input terminal, 0UTI
, 0UT2...Balanced modulation signal output terminal, CINI
, ClN2...Balanced carrier signal input terminal, CI
N...Unbalanced carrier signal input terminal. Vco...Circuit power supply, RI...Terminal resistor.

Claims (1)

【特許請求の範囲】 1、 第1及び第2のトランジスタのエミッタ同士を接
続すると共に第3及び第4のトランジスタのエミッタ同
士を接続し、前記第1及び第3のトランジスタのコレク
タ同士を接続すると共に前記第2及び第4のトランジス
タのコレクタ同士を接続し、前記第1及び第4のトラン
ジスタのペース同士を接続すると共に前記第2及び第3
のトランジスタのペース同士を接続した2組の差動増幅
回路を含む2重平衡差動増幅回路を有し、第5及び第6
のトランジスタのエミッタ同士を接続した差動増幅回路
の2つのコレクタをそれぞれコンデンサを介して前記第
1及び第4のトランジスタのペース。 前記第2及び第3のトランジスタのペースに接続し、該
第5及び第6のトランジスタの一方のべ一一スを抵抗終
端とし、他方のぺτスから搬送波信号を入力することを
特徴とする位相変調回路。
[Claims] 1. Connecting the emitters of the first and second transistors, connecting the emitters of the third and fourth transistors, and connecting the collectors of the first and third transistors. and the collectors of the second and fourth transistors are connected together, the paces of the first and fourth transistors are connected together, and the second and third transistors are connected together.
It has a double balanced differential amplifier circuit including two sets of differential amplifier circuits in which the paces of transistors are connected to each other.
The emitters of the first and fourth transistors are connected to the two collectors of the differential amplifier circuit through capacitors, respectively. It is connected to the paces of the second and third transistors, one base of the fifth and sixth transistors is terminated with a resistor, and a carrier wave signal is input from the other base. Phase modulation circuit.
JP1840284A 1984-02-06 1984-02-06 Phase modulation circuit Pending JPS60163506A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1840284A JPS60163506A (en) 1984-02-06 1984-02-06 Phase modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1840284A JPS60163506A (en) 1984-02-06 1984-02-06 Phase modulation circuit

Publications (1)

Publication Number Publication Date
JPS60163506A true JPS60163506A (en) 1985-08-26

Family

ID=11970681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1840284A Pending JPS60163506A (en) 1984-02-06 1984-02-06 Phase modulation circuit

Country Status (1)

Country Link
JP (1) JPS60163506A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01161907A (en) * 1987-11-18 1989-06-26 Stc Plc Phase modulator circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01161907A (en) * 1987-11-18 1989-06-26 Stc Plc Phase modulator circuit

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