JPS60161673A - Nonvolatile semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile semiconductor memory having a floating gate, and more particularly to an electrically selectively erasable nonvolatile memory.

[Prior art and its problems]

Conventionally, a semiconductor nonvolatile memory element having a floating gate has been formed by an MO8 field effect transistor having a floating gate electrically insulated from the outside and a control gate above the floating gate.

FIG. 1 shows the structure of a conventionally used nonvolatile memory element having a floating gate.

FIG. 1(a) is a plan view of the element.(b) is a plan view of the device.
) is a plan view when the cells of (C) are arranged in a matrix.
) shows a cross-sectional view of A-AI. Basically, an insulated floating gate (1) and a control gate (21, (
9) and MOS with rewriting electrode (4) (source)
It is a type field effect transistor. Writing (erasing)
applies a high (low) potential to the control gates (2) and (9) and a low (high) potential to the rewrite electrode (4), and injects electrons into the floating gate (1), which has become at a high (low) potential ( remove)
It is done depending on the situation.

The edge readout is performed by applying an appropriate potential to the control gate (2) and drain (3) and determining whether or not a current flows through the channel depending on whether or not electrons are injected into the floating gate. However, the write/erase characteristics of the device change greatly due to variations in the size of the thin insulating film region H through which the tunnel current flows, causing variations in the characteristics of the memory cell and causing erroneous writes/erases. b. In order to obtain the cell structure as shown in Fig. 1(a), for example, as shown in Fig. 2(a), the S
There is a method in which the i-substrate is exposed by ordinary photolithography and a particularly thin insulating film (here, a thermal oxide film) is formed.

However, if we consider the case of configuring a memory cell matrix, for example, 0.5 μm in the X and Y directions in FIG. 2(a).
If the resist mask is shifted to some extent, the area where a thin oxide film is formed will be the shaded area (2 points).

In the Y direction of the cell matrix, there are two types of areas of the thin oxide film regions, resulting in large variations in the device characteristics of each cell.

Furthermore, in order to suppress the variation in device characteristics due to the variation in the size of the conventional thin insulating film region, the
A structure like b) has also been proposed. That is, a thin insulating film region is formed separated by a thick insulating film (field oxide film) for element isolation, and a region separating the thin insulating film region and the thick insulating film for element isolation is larger than the thin insulating film. This structure is characterized by a large film thickness. (Japanese Patent Application No. 57-29914 Wada) However, in this case as well, variations in the area of the thin insulating film region occur due to misalignment of the resist mask, as in FIG. 2(a). If the distance (margin) between the field oxide film and the thin insulating film is increased in order to reduce this variation, a problem arises in that the degree of integration of the device deteriorates.

Furthermore, the smaller the region of the thin oxide film, the faster the element can be rewritten, but the region where the thin oxide film is formed is determined by the limits of lithography, and there is a problem that it cannot be made smaller than the limit of lithography. there were.

[Purpose of the invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a nonvolatile semiconductor memory that can be electrically and selectively rewritten, has less variation in element characteristics, and has significantly improved element characteristics. It is said that

[Summary of the invention]

The present invention comprises first to third electrodes that are capacitively coupled to the floating gate, one of which has the same potential in all memory cells, and two of the first to third electrodes that are control electrodes. Only cells with high (low) potential and low (high) potential applied to other electrodes, which are rewriting electrodes, have their floating gates high (low).
A rewrite electrode and a floating gate that exchange charges in a non-volatile semiconductor memory in which memory contents are electrically and selectively rewritten by becoming a potential and exchanging electric charges with the other electrode. The thin insulating film region between the thin insulating film and the thin insulating film for element isolation is formed so as to be in contact with the thick insulating film for element isolation in at least two different regions, and the boundary is formed to coincide with the floating gate in at least one region. It is characterized by

〔Effect of the invention〕

In the present invention, the size of the thin insulating film region through which the tunnel current that transfers charge flows can be formed with less variation between devices, and the size of this region can be made significantly smaller than the limit of lithography, resulting in excellent characteristics. A nonvolatile semiconductor memory device can be provided.

[Embodiments of the invention]

FIG. 3 shows the memory cell structure of an embodiment of the nonvolatile memory according to the present invention, in which FIG. 3(a) is a plan view of the device, FIG. .

(d) The present invention can reduce variations in the size of the thin oxide film region through which the tunnel current that transfers stain charges flows, thereby reducing the variation between devices. FIG. 7 is a diagram for explaining that the region where transfer is performed is not the entire thin oxide film region but a smaller region.

The memory cell has an insulated floating gate c11), a first electrode or first control gate, and a second electrode or second control gate.
It is characterized by having a control gate (to). (
) is a male type drain, 0 is a male type source (third electrode)
(4G is a P-type 8i substrate, (to) is a field oxide film, (7), (378) to (37C) are oxide films.

Floating gate 0υ, 1st. The second control gates (to) and (g) are each made of furnace-type polycrystalline silicon and have a film thickness of, for example, 4000 Å. The thickness of the thermal oxide film is, for example, C3ni.
o.

A, (37a), (37b), and (37c) are each 1000^. The region C3I where charge is exchanged by tunnel current is shown in Fig. 3(C) and (d).
) in two different areas as shown in field oxide (
(to C'll), and at least part of the other part is bounded by the floating gate C'll), and the other region is surrounded by a thin oxide film (C'll).
The boundary borders the total impurity layer (goods).

To obtain a tunnel region OI like that shown in FIG. 3 (al), for example, after forming a gate oxide film of 100X in the element formation region as shown in FIG. Expose the area (to) that forms the area.

Next, in the area where the thin oxide film is to be formed, for example, an insulating film (here, a thermal oxide film is used, but it may also be a multilayer film of an oxide film and a silicon nitride film, a silicon nitride film, or another insulating film). Form 100A. At this time, the region (to) where the thin oxide film is to be formed is set to a size such that at least a part thereof is exposed than the region (c3+) where the floating gate is to be formed.

Thereafter, a polycrystalline silicon film doped with phosphorus, for example, is deposited over the entire surface, and a floating gate is patterned. Thereafter, the thermal oxide film in the desired region (301) is removed by ordinary photolithography, and an n-type impurity such as As is removed by I.times.10
It is formed by ion implantation at cm 100 KeV. At this time, the thin oxide film region (to) under the floating gate 01)
In this case, the floating gate Gυ serves as a mask and no ion implantation is performed. After that, the second gate oxide film is applied to
0A is formed. As shown in FIG. 3(d), the rewriting electrode is not the entire thin oxide film region (up to), but the n
This is a region obtained by lateral diffusion of the type impurity layer. This region 0 is capacitively coupled to the floating gate through a thin oxide film.

Therefore, as shown in Fig. 3(C), for example, the mask alignment of the region (to) where a thin oxide film is to be formed is ±05 in the X and Y directions.
Even if the underlying alignment pattern is changed by about μm, the rewriting electrode region C11IJ is determined only by the diffusion of the n-type impurity layer and does not suffer from so-called alignment errors. Also, this area (to) is not determined by the limit of ring graphie, and we were able to realize a smaller area. Further, as shown in Fig. 4, after forming a region (50) in which a thin oxide film is to be formed at a distance from the field edge using a normal photolithography method, a rewriting electrode region (49) is formed in the same manner as above. Needless to say, similar effects can be obtained.

The operation of this memory cell can be explained as follows. This memory cell is externally supplied with drain voltage VD, source voltage Vs,
Substrate voltage Vsub, first control gate voltage VCG,
A second control gate voltage VCG2 is applied.

Also, since the electrical equivalent circuit is shown in FIG. 5, the potential VFG of the floating gate is expressed by the following equation.

Here, C, , C2 are control gates α0, . Coupling capacitance between (g) and floating game H31), C5, C5ub
are the coupling capacitances with the source (goods) and substrate (4G), respectively. From equation (1), the substrate voltage Vs ub and the source voltage Vs
When fixed, the potential level of the floating gate can take on three states using the first control gate (to) and the second control gate (to). In other words, (1) When the first control gate (G) and the second control gate (G) are both at high potential, (II) Which of the first control gate (To) and the second control gate (C) is selected? If one is at high potential and the other is at low potential, (1
11) The first control gate (to) and the second control gate (c) are both at low potential. Therefore, as shown in FIG. 3(a), when the tunnel current of the oxide film OI under the floating gate (Cll) is (1) (Vs is a low potential), or (1)
In the case of 1+1 (Vs is a high potential), by forming the film with a thickness such that only K flows and does not flow in other states, it becomes possible to selectively write and erase cells.

In reality, the memory cells shown in FIG. 3 are arranged in a matrix on the substrate. For example, consider a memory cell matrix in which the above-mentioned memory cells M are arranged from M to M4 as shown in FIG. The source (goods) of M and distance are common, and the sources (goods) of Tame and M4 are also common. Similarly, the first control gate (to), @', the second control gate 1, 0 and 1 are also MI, nu9M3. and Ml.

This is common to Ms, Ms 9M4. Assuming that there is no charge accumulated in the floating gate of each memory cell in the initial state, 1. For example, when writing data to memory cell M1, the source (2), which is the third electrode, is given the same potential to all memory cells. , 04)' is OV.

Also, 1st. Apply +20V to the second electrode, control gate (to), G9, and control gate (to)1. (to)
Let 1 be OV.

In this way, the floating gate clD of M becomes a high potential, and electrons are injected into the floating gate 0υ by a tunnel current through the thermal oxide film OI, and the write state is ``0''.
becomes. If the memory cell stripes are to be written at the same time, +20V may also be applied to the control gate fi51'.

Next, when deleting the contents of M, source (B) (34
) 1 to +20V, 1st. If 0■ is applied to the second control gates (G) and (G) and m' and es' are kept at +20V, M
, the floating gate 61) is at a low level, electrons are emitted to the source 041 by a tunnel current, and the erased state becomes "1#".

The writing can also be performed by injection of hot electrons from the transistor region using a common drain signal line and a control gate signal line perpendicular to the common drain signal line, as in the conventional case.

In the above embodiments, a P-type substrate was used, but when an N-type substrate is used, the conductivity types of the source and drain are reversed.

As described above, according to the present invention, it is possible to electrically and selectively rewrite the memory contents, there is less variation in element characteristics, and the coupling capacitance between the floating gate and the rewriting electrode can be reduced, so the rewriting element A nonvolatile semiconductor memory with significantly improved characteristics can be realized.

[Brief explanation of drawings]

Figures 1 (a) to (C) are diagrams explaining the conventional example, and Figure 2 (
FIGS. 3A and 3B are plan views illustrating alignment errors in the conventional example, and FIGS. 3A and 3B are views illustrating an embodiment according to the present invention. FIG. 4 is a diagram illustrating another embodiment of the present invention. FIG. 5 is a circuit diagram for explaining an isochoric circuit according to an embodiment of the present invention, and FIG. 6 is a diagram for explaining a memory cell matrix according to an embodiment of the present invention. In the figure -1, 31, 41... floating gate. 2.36...first control gate (first electrode). 9.35... second control gate (second electrode), 4.
34... Source (third electrode), 3.33... Drain, 10.39... Tunnel oxide film region, 8.38...
field oxide. 5.40...P-type substrate.

Claims (2)

[Claims] (1) Memory cells having electrically insulated floating gates are arranged in an IJ sock shape on the same substrate. Each memory cell has first to third electrodes that are capacitively coupled to the floating gate and have one electrode which is provided with the same potential in at least two or more memory cells. Among the electrodes, only a memory cell in which two electrodes that are control electrodes are given a high potential and the other electrodes that are rewriting electrodes are given a low potential has a floating gate at a high potential, or the two electrodes that are control electrodes are given a high potential. Only memory cells to which a low potential is applied and a high potential is applied to the other electrode, which is the rewriting electrode, have their floating gates at a low potential, and charge is exchanged between the floating gate and the other electrodes to store memory. In a nonvolatile semiconductor memory in which content is electrically rewritten, a thin insulating film region between a rewriting electrode and a floating gate that transfers charge is formed into a polygon with approximately four sides, and a pair of opposing two A side is formed at the boundary between the thin insulating film and the thick insulating film for element isolation, and one of the remaining two sides is 7)
i A non-volatile semiconductor memory, characterized in that the non-volatile semiconductor memory is located at the periphery of the floating gate and under the floating gate. (2) The rewriting electrode is a highly impurity concentration layer of the same conductivity type as the source, and is connected to the source, and is a region obtained by diffusion after implanting impurities using the floating gate as a mask. 2. The nonvolatile semiconductor memory according to claim 1, wherein the floating gate is capacitively coupled via the thin insulating film.