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JPS60160698A - Multilayer ceramic board - Google Patents

Multilayer ceramic board

Info

Publication number
JPS60160698A
JPS60160698A JP1641684A JP1641684A JPS60160698A JP S60160698 A JPS60160698 A JP S60160698A JP 1641684 A JP1641684 A JP 1641684A JP 1641684 A JP1641684 A JP 1641684A JP S60160698 A JPS60160698 A JP S60160698A
Authority
JP
Japan
Prior art keywords
multilayer ceramic
external electrode
silver
paste
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1641684A
Other languages
Japanese (ja)
Other versions
JPH021393B2 (en
Inventor
隆之 猪井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1641684A priority Critical patent/JPS60160698A/en
Publication of JPS60160698A publication Critical patent/JPS60160698A/en
Publication of JPH021393B2 publication Critical patent/JPH021393B2/ja
Granted legal-status Critical Current

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Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は多層セラミック基板に関し、特にその外部電極
の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer ceramic substrate, and particularly to improvements in its external electrodes.

近年、コストパフォーマンスという観点から多層セラミ
ック基板の導体ペーストとして、高価な金ペーストの代
わりに、安価な銀−パラジウム系ペーストや、銀−白金
系ペーストなどを用いることが試みられている。
In recent years, from the viewpoint of cost performance, attempts have been made to use inexpensive silver-palladium pastes, silver-platinum pastes, etc. instead of expensive gold pastes as conductor pastes for multilayer ceramic substrates.

通常、ブリー/シート積層法で絶縁体グリ−/シート3
に銀−パラジウム系ペーストや銀−白金糸ペーストなど
を第1図に示すように断面Tの字状に孔内に充填して内
部電極1として形成して用いた場合には内部電極lのラ
ンド側の部分の剥離やふくれといった現象は観測されな
い。しかし前述のペーストを外部電極2として用いた場
合には外部電極2の外部に露出しているランド部分の剥
離やふくれといった好ましくない現象が生じる。
Normally, insulator green/sheet 3
When the internal electrode 1 is formed by filling the hole with a silver-palladium paste or silver-platinum thread paste in a T-shaped cross section as shown in Fig. 1, the land of the internal electrode 1 is used. No phenomena such as peeling or blistering on the side parts were observed. However, when the above-mentioned paste is used as the external electrode 2, undesirable phenomena such as peeling and blistering of the land portion exposed to the outside of the external electrode 2 occur.

従って銀−パラジウム系ペーストや銀−白金系ペースト
を外部電極として用いることは困難であった。
Therefore, it has been difficult to use a silver-palladium paste or a silver-platinum paste as an external electrode.

本発明の目的は、このような欠点を解決し、外部電極と
して銀−パラジウム系ペーストや銀−白金系ペーストな
どを用いて、外部電極のランド部の剥離やふくれの生じ
ない多層セラミック基板を提供することにある。
The purpose of the present invention is to solve these drawbacks and provide a multilayer ceramic substrate that uses silver-palladium paste, silver-platinum paste, etc. as the external electrode and does not cause peeling or blistering of the land portion of the external electrode. It's about doing.

本発明によれば多層セラミック積層体の最外層に減小し
て設けられた外部電極と、該外部電極の外形形状より小
なる開口窓を有する絶縁シートを開口窓と外部電極とを
合せて1層以上積層することを特徴とする多層セラミッ
ク基板が得られる。
According to the present invention, an external electrode is provided in a reduced size on the outermost layer of a multilayer ceramic laminate, and an insulating sheet having an opening window smaller than the external shape of the external electrode is combined with the opening window and the external electrode into one. A multilayer ceramic substrate characterized by laminating more than one layer is obtained.

以下、本発明を第2図〜第4図を参照し、本発明の実施
例について説明する。第2図に示すようにグリーンシー
トの所望の位置に設けた貫通孔内を導電ペーストで充填
形成させたバイアホール4を介してグリーンシートの上
下導通のためのランド状の内部電極5を両面印刷して設
けた絶縁体グリーンシート6とバイアホール4と接続し
てコンデンサ形成用の内部電極7aを下面に印刷した誘
電体グリ−/シート8と誘電体グリーンシート8ツバイ
アホールの突設上端と接続してコンデンサを形成する内
部型$7bを下面に印刷した絶縁体グリ−/シート9と
、抵抗体lOを上面に印刷した絶縁体グリーンシートl
lとを第2図の上下2層を除いた状態で各シートを積み
重ねて積層体12を形成する。次にこの積層体12の最
外層の外側に、最外層に形成された外部電極5と対応す
る同じ位置で、外部電極5の形状より小さい貫通孔から
なる窓部″′13を設けた絶縁体グリーンシート14を
積層する。これを温度ito’c、圧力200kg/c
rAの条件下で20分間熱圧着する。次に温度上昇速度
5℃/時間、最高m度450℃、最高温度保持時間4時
間の条件下で脱バインダー処理を行ない、最高温度85
0℃まで上昇させた後、室温まで冷却する温度プロファ
イルで焼結し第3図の多層セラミック基板を得た。
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2 to 4. As shown in Fig. 2, land-shaped internal electrodes 5 are printed on both sides for vertical conduction of the green sheet through via holes 4 formed by filling the through holes provided at desired positions of the green sheet with conductive paste. The insulator green sheet 6 and the via hole 4 are connected to each other, and the dielectric green sheet 8 and the dielectric green sheet 8 on which internal electrodes 7a for forming a capacitor are printed on the bottom surface are connected to the protruding upper end of the via hole. An insulator green sheet 9 with an internal mold $7b printed on the bottom surface to form a capacitor, and an insulator green sheet 1 with a resistor lO printed on the top surface.
A laminate 12 is formed by stacking each sheet with the upper and lower two layers shown in FIG. 2 removed. Next, on the outside of the outermost layer of this laminate 12, an insulator is provided with a window ''13 consisting of a through hole smaller than the shape of the external electrode 5 at the same position corresponding to the external electrode 5 formed on the outermost layer. Stack the green sheets 14 at a temperature of 200 kg/c and a pressure of 200 kg/c.
Thermocompression bonding is carried out for 20 minutes under rA conditions. Next, debinding was performed under the conditions of a temperature increase rate of 5°C/hour, a maximum temperature of 450°C, and a maximum temperature holding time of 4 hours, and the maximum temperature was 85°C.
The multilayer ceramic substrate shown in FIG. 3 was obtained by sintering with a temperature profile in which the temperature was raised to 0° C. and then cooled to room temperature.

この本発明多層セラミック基板は外部電極の剥離やふく
れを生じ易いランドの周縁部を絶縁体グリーンシート1
4で押圧された状態で保持される、なお、本実施例では
、剥離やふくれをおさえるための最外層の外側に積層す
る絶縁体グリーンシートの層数を1層にした場合につい
て述べたが、第4図に示すように2層以上の場合につい
ても試作してみたところ1層の場合よりもさらに良好な
結果が得られた。
In this multilayer ceramic substrate of the present invention, the periphery of the land where external electrodes are likely to peel or bulge is covered with an insulating green sheet
In this example, the case where the number of insulating green sheets laminated outside the outermost layer to suppress peeling and blistering is one layer is described. As shown in FIG. 4, when we tried manufacturing a case with two or more layers, even better results were obtained than in the case of one layer.

以上本発明により外部電極として銀−パラジウム系ペー
ストや銀−白金系ペーストなどを用いた場合の外部電極
の剥離やふくれといった従来の欠点が解消され、外部電
極として金ペーストより安価な銀−パラジウム系ペース
トや銀−白金系ペーストなどを用いることが可能となり
低コスト化が計れる利点がある。
As described above, the present invention solves the conventional drawbacks such as peeling and blistering of the external electrode when silver-palladium paste or silver-platinum paste is used as the external electrode, and silver-palladium paste, which is cheaper than gold paste, is used as the external electrode. It is possible to use paste, silver-platinum paste, etc., which has the advantage of reducing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来多層セラミック基板の電極形成層の断面図
。第2図は本発明実施例の積層前の多層セラミック基板
の断面図。第3図は第2図の完成後の主要部を示す切り
欠き斜視断面図。第4[F]は本発明の他の実施例の積
層前の多層セラミック基板の断面図。 l・・・・・・内部電極、2・・・・・・外部電極、3
・・・・・・絶縁体グリ−/シート、4・・・・・・バ
イアホール& 5・・・・・・内部電極う/ド、6,9
.11・・・・・・絶縁体グリ−/シート、7a、7b
・・・・・・(コノテンサ形成の)内部電極、8・・・
・・・誘電体グリーンシート、10・・・・・・抵抗体
、12・・・・・・積層体、13・旧・・窓部、14・
・・・・・窓部を設けた絶縁体グリ−/シート、15・
・・代理人 弁理士 内 原 晋(、’7−*−tへ東
 1 ヅ 序Z回 争″3拐
FIG. 1 is a cross-sectional view of an electrode forming layer of a conventional multilayer ceramic substrate. FIG. 2 is a sectional view of a multilayer ceramic substrate before lamination according to an embodiment of the present invention. FIG. 3 is a cutaway perspective sectional view showing the main part of FIG. 2 after completion. 4th [F] is a sectional view of a multilayer ceramic substrate before lamination according to another embodiment of the present invention. l...Internal electrode, 2...External electrode, 3
...Insulator green / sheet, 4 ... Via hole & 5 ... Internal electrode board, 6, 9
.. 11...Insulator green/sheet, 7a, 7b
...Internal electrode (of conotensa formation), 8...
... Dielectric green sheet, 10... Resistor, 12... Laminate, 13. Old... Window section, 14.
...Insulator green/sheet with window, 15.
・・Representative Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 多層セラミック積層体の最外層に露出して設けられた外
部電極と該外部電極の外形形状より小なる開口窓を有す
る絶縁シートを開口窓と外部電極とを合せて1層以上積
層していることを特徴とする多層セラミック基板。
An external electrode provided exposed on the outermost layer of a multilayer ceramic laminate and an insulating sheet having an opening window smaller than the external shape of the external electrode are laminated in one or more layers including the opening window and the external electrode. A multilayer ceramic substrate featuring:
JP1641684A 1984-01-31 1984-01-31 Multilayer ceramic board Granted JPS60160698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1641684A JPS60160698A (en) 1984-01-31 1984-01-31 Multilayer ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1641684A JPS60160698A (en) 1984-01-31 1984-01-31 Multilayer ceramic board

Publications (2)

Publication Number Publication Date
JPS60160698A true JPS60160698A (en) 1985-08-22
JPH021393B2 JPH021393B2 (en) 1990-01-11

Family

ID=11915629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1641684A Granted JPS60160698A (en) 1984-01-31 1984-01-31 Multilayer ceramic board

Country Status (1)

Country Link
JP (1) JPS60160698A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04228293A (en) * 1990-12-27 1992-08-18 Kodaka Kogyo Kk Apparatus for treating waste can
JPH0528589U (en) * 1991-09-17 1993-04-16 株式会社岩内 Crush processing equipment for empty cans
JPH07176864A (en) * 1993-12-21 1995-07-14 Fujitsu Ltd Method for manufacturing multilayer ceramic substrate
JP2002368419A (en) * 2001-06-04 2002-12-20 Sumitomo Metal Electronics Devices Inc Method for manufacturing low temperature burning ceramic multilayer substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04228293A (en) * 1990-12-27 1992-08-18 Kodaka Kogyo Kk Apparatus for treating waste can
JPH0528589U (en) * 1991-09-17 1993-04-16 株式会社岩内 Crush processing equipment for empty cans
JPH07176864A (en) * 1993-12-21 1995-07-14 Fujitsu Ltd Method for manufacturing multilayer ceramic substrate
JP2002368419A (en) * 2001-06-04 2002-12-20 Sumitomo Metal Electronics Devices Inc Method for manufacturing low temperature burning ceramic multilayer substrate

Also Published As

Publication number Publication date
JPH021393B2 (en) 1990-01-11

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term